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pll_drv.h

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00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00002 /*! \file *********************************************************************
00003  *
00004  * \brief
00005  *      This file contains the low level macros and definition for the USB PLL.
00006  *
00007  * \par Application note:
00008  *      AVR280: USB Host CDC Demonstration
00009  *
00010  * \par Documentation
00011  *      For comprehensive code documentation, supported compilers, compiler
00012  *      settings and supported devices see readme.html
00013  *
00014  * \author
00015  *      Atmel Corporation: http://www.atmel.com \n
00016  *      Support email: avr@atmel.com
00017  *
00018  * $Name:  $
00019  * $Revision: 1.1 $
00020  * $RCSfile: pll_drv.h,v $
00021  * $Date: 2008/10/14 20:16:36 $  \n
00022  * $Id: pll_drv.h,v 1.1 2008/10/14 20:16:36 c_oflynn Exp $
00023  ******************************************************************************/
00024 /* Copyright (c) 2008  ATMEL Corporation
00025    All rights reserved.
00026 
00027    Redistribution and use in source and binary forms, with or without
00028    modification, are permitted provided that the following conditions are met:
00029 
00030    * Redistributions of source code must retain the above copyright
00031      notice, this list of conditions and the following disclaimer.
00032    * Redistributions in binary form must reproduce the above copyright
00033      notice, this list of conditions and the following disclaimer in
00034      the documentation and/or other materials provided with the
00035      distribution.
00036    * Neither the name of the copyright holders nor the names of
00037      contributors may be used to endorse or promote products derived
00038      from this software without specific prior written permission.
00039 
00040   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00041   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00042   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00043   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00044   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00045   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00046   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00047   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00048   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00049   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00050   POSSIBILITY OF SUCH DAMAGE.
00051 */
00052 
00053 #ifndef PLL_DRV_H
00054 #define PLL_DRV_H
00055 
00056 //_____ I N C L U D E S ____________________________________________________
00057 
00058 /**
00059    @addtogroup usb
00060    @{
00061 */
00062 //_____ M A C R O S ________________________________________________________
00063 
00064    //! @defgroup PLL_macros PLL Macros
00065    //! These functions allow to control the PLL
00066    //! @{
00067 #define PLLx24                  ( (0<<PLLP2) | (0<<PLLP1) | (0<<PLLP0) )
00068 #define PLLx12                  ( (0<<PLLP2) | (0<<PLLP1) | (1<<PLLP0) )
00069 #define PLLx08                  ( (0<<PLLP2) | (1<<PLLP1) | (0<<PLLP0) )
00070 #define PLLx06                  ( (0<<PLLP2) | (1<<PLLP1) | (1<<PLLP0) )
00071 #define PLLx04                  ( (1<<PLLP2) | (0<<PLLP1) | (0<<PLLP0) )
00072 #define PLLx03                  ( (1<<PLLP2) | (0<<PLLP1) | (1<<PLLP0) )
00073 #define PLLx04_8        ( (1<<PLLP2) | (1<<PLLP1) | (0<<PLLP0) )
00074 #define PLLx02          ( (1<<PLLP2) | (1<<PLLP1) | (1<<PLLP0) )
00075 
00076 
00077       //! @brief Start the PLL at only 48 MHz, regarding CPU frequency
00078       //! Start the USB PLL with clockfactor
00079       //! clockfactor can be PLLx24, PLLx12, PLLx08
00080       //! PLLx06, PLLx04, PLLx03
00081 #define Start_pll(clockfactor)                                                  \
00082            (PLLCSR = ( clockfactor  | (1<<PLLE)  ))
00083 
00084       //! return 1 when PLL locked
00085 #define Is_pll_ready()       (PLLCSR & (1<<PLOCK) )
00086 
00087       //! Test PLL lock bit and wait until lock is set
00088 #define Wait_pll_ready()     while (!(PLLCSR & (1<<PLOCK)))
00089 
00090       //! Stop the PLL
00091 #define Stop_pll()           (PLLCSR  &= (~(1<<PLLE)) )
00092 
00093       // Start the PLL in autofactor mode
00094       // regarding FOSC define
00095 #if   (FOSC==2000)
00096       //! Start the PLL in autofactor mode
00097       //! regarding FOSC define
00098    #define Pll_start_auto()   Start_pll(PLLx24)
00099 #elif (FOSC==4000)
00100    #define Pll_start_auto()   Start_pll(PLLx12)
00101 #elif (FOSC==6000)
00102    #define Pll_start_auto()   Start_pll(PLLx08)
00103 #elif (FOSC==8000)
00104       //! Start the PLL in autofactor mode
00105       //! regarding FOSC define
00106    #define Pll_start_auto()   Start_pll(PLLx06)
00107 #elif (FOSC==12000)
00108    #define Pll_start_auto()   Start_pll(PLLx04)
00109 #elif (FOSC==16000)
00110    #define Pll_start_auto()   Start_pll(PLLx03)
00111 #elif (FOSC==20000)
00112    #define Pll_start_auto()   Start_pll(PLLx04_8)
00113 #elif (FOSC==24000)
00114    #define Pll_start_auto()   Start_pll(PLLx02)
00115 #else
00116    #error   "FOSC should be defined in config.h"
00117 #endif
00118 
00119    //! @}
00120 
00121 //! @}
00122 #endif  // PLL_DRV_H
00123 
00124