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00001 /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 00002 * File Name : stm32f10x_dma.h 00003 * Author : MCD Application Team 00004 * Version : V2.0.3 00005 * Date : 09/22/2008 00006 * Description : This file contains all the functions prototypes for the 00007 * DMA firmware library. 00008 ******************************************************************************** 00009 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00010 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 00011 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 00012 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 00013 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 00014 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00015 *******************************************************************************/ 00016 00017 /* Define to prevent recursive inclusion -------------------------------------*/ 00018 #ifndef __STM32F10x_DMA_H 00019 #define __STM32F10x_DMA_H 00020 00021 /* Includes ------------------------------------------------------------------*/ 00022 #include "stm32f10x_map.h" 00023 00024 /* Exported types ------------------------------------------------------------*/ 00025 /* DMA Init structure definition */ 00026 typedef struct 00027 { 00028 u32 DMA_PeripheralBaseAddr; 00029 u32 DMA_MemoryBaseAddr; 00030 u32 DMA_DIR; 00031 u32 DMA_BufferSize; 00032 u32 DMA_PeripheralInc; 00033 u32 DMA_MemoryInc; 00034 u32 DMA_PeripheralDataSize; 00035 u32 DMA_MemoryDataSize; 00036 u32 DMA_Mode; 00037 u32 DMA_Priority; 00038 u32 DMA_M2M; 00039 }DMA_InitTypeDef; 00040 00041 /* Exported constants --------------------------------------------------------*/ 00042 #define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \ 00043 ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \ 00044 ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \ 00045 ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \ 00046 ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \ 00047 ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \ 00048 ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \ 00049 ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \ 00050 ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \ 00051 ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \ 00052 ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \ 00053 ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE)) 00054 00055 /* DMA data transfer direction -----------------------------------------------*/ 00056 #define DMA_DIR_PeripheralDST ((u32)0x00000010) 00057 #define DMA_DIR_PeripheralSRC ((u32)0x00000000) 00058 00059 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ 00060 ((DIR) == DMA_DIR_PeripheralSRC)) 00061 00062 /* DMA peripheral incremented mode -------------------------------------------*/ 00063 #define DMA_PeripheralInc_Enable ((u32)0x00000040) 00064 #define DMA_PeripheralInc_Disable ((u32)0x00000000) 00065 00066 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ 00067 ((STATE) == DMA_PeripheralInc_Disable)) 00068 00069 /* DMA memory incremented mode -----------------------------------------------*/ 00070 #define DMA_MemoryInc_Enable ((u32)0x00000080) 00071 #define DMA_MemoryInc_Disable ((u32)0x00000000) 00072 00073 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ 00074 ((STATE) == DMA_MemoryInc_Disable)) 00075 00076 /* DMA peripheral data size --------------------------------------------------*/ 00077 #define DMA_PeripheralDataSize_Byte ((u32)0x00000000) 00078 #define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100) 00079 #define DMA_PeripheralDataSize_Word ((u32)0x00000200) 00080 00081 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ 00082 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ 00083 ((SIZE) == DMA_PeripheralDataSize_Word)) 00084 00085 /* DMA memory data size ------------------------------------------------------*/ 00086 #define DMA_MemoryDataSize_Byte ((u32)0x00000000) 00087 #define DMA_MemoryDataSize_HalfWord ((u32)0x00000400) 00088 #define DMA_MemoryDataSize_Word ((u32)0x00000800) 00089 00090 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ 00091 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ 00092 ((SIZE) == DMA_MemoryDataSize_Word)) 00093 00094 /* DMA circular/normal mode --------------------------------------------------*/ 00095 #define DMA_Mode_Circular ((u32)0x00000020) 00096 #define DMA_Mode_Normal ((u32)0x00000000) 00097 00098 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) 00099 00100 /* DMA priority level --------------------------------------------------------*/ 00101 #define DMA_Priority_VeryHigh ((u32)0x00003000) 00102 #define DMA_Priority_High ((u32)0x00002000) 00103 #define DMA_Priority_Medium ((u32)0x00001000) 00104 #define DMA_Priority_Low ((u32)0x00000000) 00105 00106 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ 00107 ((PRIORITY) == DMA_Priority_High) || \ 00108 ((PRIORITY) == DMA_Priority_Medium) || \ 00109 ((PRIORITY) == DMA_Priority_Low)) 00110 00111 /* DMA memory to memory ------------------------------------------------------*/ 00112 #define DMA_M2M_Enable ((u32)0x00004000) 00113 #define DMA_M2M_Disable ((u32)0x00000000) 00114 00115 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) 00116 00117 /* DMA interrupts definition -------------------------------------------------*/ 00118 #define DMA_IT_TC ((u32)0x00000002) 00119 #define DMA_IT_HT ((u32)0x00000004) 00120 #define DMA_IT_TE ((u32)0x00000008) 00121 00122 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) 00123 00124 /* For DMA1 */ 00125 #define DMA1_IT_GL1 ((u32)0x00000001) 00126 #define DMA1_IT_TC1 ((u32)0x00000002) 00127 #define DMA1_IT_HT1 ((u32)0x00000004) 00128 #define DMA1_IT_TE1 ((u32)0x00000008) 00129 #define DMA1_IT_GL2 ((u32)0x00000010) 00130 #define DMA1_IT_TC2 ((u32)0x00000020) 00131 #define DMA1_IT_HT2 ((u32)0x00000040) 00132 #define DMA1_IT_TE2 ((u32)0x00000080) 00133 #define DMA1_IT_GL3 ((u32)0x00000100) 00134 #define DMA1_IT_TC3 ((u32)0x00000200) 00135 #define DMA1_IT_HT3 ((u32)0x00000400) 00136 #define DMA1_IT_TE3 ((u32)0x00000800) 00137 #define DMA1_IT_GL4 ((u32)0x00001000) 00138 #define DMA1_IT_TC4 ((u32)0x00002000) 00139 #define DMA1_IT_HT4 ((u32)0x00004000) 00140 #define DMA1_IT_TE4 ((u32)0x00008000) 00141 #define DMA1_IT_GL5 ((u32)0x00010000) 00142 #define DMA1_IT_TC5 ((u32)0x00020000) 00143 #define DMA1_IT_HT5 ((u32)0x00040000) 00144 #define DMA1_IT_TE5 ((u32)0x00080000) 00145 #define DMA1_IT_GL6 ((u32)0x00100000) 00146 #define DMA1_IT_TC6 ((u32)0x00200000) 00147 #define DMA1_IT_HT6 ((u32)0x00400000) 00148 #define DMA1_IT_TE6 ((u32)0x00800000) 00149 #define DMA1_IT_GL7 ((u32)0x01000000) 00150 #define DMA1_IT_TC7 ((u32)0x02000000) 00151 #define DMA1_IT_HT7 ((u32)0x04000000) 00152 #define DMA1_IT_TE7 ((u32)0x08000000) 00153 /* For DMA2 */ 00154 #define DMA2_IT_GL1 ((u32)0x10000001) 00155 #define DMA2_IT_TC1 ((u32)0x10000002) 00156 #define DMA2_IT_HT1 ((u32)0x10000004) 00157 #define DMA2_IT_TE1 ((u32)0x10000008) 00158 #define DMA2_IT_GL2 ((u32)0x10000010) 00159 #define DMA2_IT_TC2 ((u32)0x10000020) 00160 #define DMA2_IT_HT2 ((u32)0x10000040) 00161 #define DMA2_IT_TE2 ((u32)0x10000080) 00162 #define DMA2_IT_GL3 ((u32)0x10000100) 00163 #define DMA2_IT_TC3 ((u32)0x10000200) 00164 #define DMA2_IT_HT3 ((u32)0x10000400) 00165 #define DMA2_IT_TE3 ((u32)0x10000800) 00166 #define DMA2_IT_GL4 ((u32)0x10001000) 00167 #define DMA2_IT_TC4 ((u32)0x10002000) 00168 #define DMA2_IT_HT4 ((u32)0x10004000) 00169 #define DMA2_IT_TE4 ((u32)0x10008000) 00170 #define DMA2_IT_GL5 ((u32)0x10010000) 00171 #define DMA2_IT_TC5 ((u32)0x10020000) 00172 #define DMA2_IT_HT5 ((u32)0x10040000) 00173 #define DMA2_IT_TE5 ((u32)0x10080000) 00174 00175 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) 00176 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ 00177 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ 00178 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ 00179 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ 00180 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ 00181 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ 00182 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ 00183 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ 00184 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ 00185 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ 00186 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ 00187 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ 00188 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ 00189 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ 00190 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ 00191 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ 00192 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ 00193 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ 00194 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ 00195 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ 00196 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ 00197 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ 00198 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ 00199 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) 00200 00201 /* DMA flags definition ------------------------------------------------------*/ 00202 /* For DMA1 */ 00203 #define DMA1_FLAG_GL1 ((u32)0x00000001) 00204 #define DMA1_FLAG_TC1 ((u32)0x00000002) 00205 #define DMA1_FLAG_HT1 ((u32)0x00000004) 00206 #define DMA1_FLAG_TE1 ((u32)0x00000008) 00207 #define DMA1_FLAG_GL2 ((u32)0x00000010) 00208 #define DMA1_FLAG_TC2 ((u32)0x00000020) 00209 #define DMA1_FLAG_HT2 ((u32)0x00000040) 00210 #define DMA1_FLAG_TE2 ((u32)0x00000080) 00211 #define DMA1_FLAG_GL3 ((u32)0x00000100) 00212 #define DMA1_FLAG_TC3 ((u32)0x00000200) 00213 #define DMA1_FLAG_HT3 ((u32)0x00000400) 00214 #define DMA1_FLAG_TE3 ((u32)0x00000800) 00215 #define DMA1_FLAG_GL4 ((u32)0x00001000) 00216 #define DMA1_FLAG_TC4 ((u32)0x00002000) 00217 #define DMA1_FLAG_HT4 ((u32)0x00004000) 00218 #define DMA1_FLAG_TE4 ((u32)0x00008000) 00219 #define DMA1_FLAG_GL5 ((u32)0x00010000) 00220 #define DMA1_FLAG_TC5 ((u32)0x00020000) 00221 #define DMA1_FLAG_HT5 ((u32)0x00040000) 00222 #define DMA1_FLAG_TE5 ((u32)0x00080000) 00223 #define DMA1_FLAG_GL6 ((u32)0x00100000) 00224 #define DMA1_FLAG_TC6 ((u32)0x00200000) 00225 #define DMA1_FLAG_HT6 ((u32)0x00400000) 00226 #define DMA1_FLAG_TE6 ((u32)0x00800000) 00227 #define DMA1_FLAG_GL7 ((u32)0x01000000) 00228 #define DMA1_FLAG_TC7 ((u32)0x02000000) 00229 #define DMA1_FLAG_HT7 ((u32)0x04000000) 00230 #define DMA1_FLAG_TE7 ((u32)0x08000000) 00231 /* For DMA2 */ 00232 #define DMA2_FLAG_GL1 ((u32)0x10000001) 00233 #define DMA2_FLAG_TC1 ((u32)0x10000002) 00234 #define DMA2_FLAG_HT1 ((u32)0x10000004) 00235 #define DMA2_FLAG_TE1 ((u32)0x10000008) 00236 #define DMA2_FLAG_GL2 ((u32)0x10000010) 00237 #define DMA2_FLAG_TC2 ((u32)0x10000020) 00238 #define DMA2_FLAG_HT2 ((u32)0x10000040) 00239 #define DMA2_FLAG_TE2 ((u32)0x10000080) 00240 #define DMA2_FLAG_GL3 ((u32)0x10000100) 00241 #define DMA2_FLAG_TC3 ((u32)0x10000200) 00242 #define DMA2_FLAG_HT3 ((u32)0x10000400) 00243 #define DMA2_FLAG_TE3 ((u32)0x10000800) 00244 #define DMA2_FLAG_GL4 ((u32)0x10001000) 00245 #define DMA2_FLAG_TC4 ((u32)0x10002000) 00246 #define DMA2_FLAG_HT4 ((u32)0x10004000) 00247 #define DMA2_FLAG_TE4 ((u32)0x10008000) 00248 #define DMA2_FLAG_GL5 ((u32)0x10010000) 00249 #define DMA2_FLAG_TC5 ((u32)0x10020000) 00250 #define DMA2_FLAG_HT5 ((u32)0x10040000) 00251 #define DMA2_FLAG_TE5 ((u32)0x10080000) 00252 00253 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) 00254 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ 00255 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ 00256 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ 00257 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ 00258 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ 00259 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ 00260 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ 00261 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ 00262 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ 00263 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ 00264 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ 00265 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ 00266 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ 00267 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ 00268 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ 00269 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ 00270 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ 00271 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ 00272 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ 00273 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ 00274 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ 00275 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ 00276 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ 00277 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) 00278 00279 /* DMA Buffer Size -----------------------------------------------------------*/ 00280 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 00281 00282 /* Exported macro ------------------------------------------------------------*/ 00283 /* Exported functions ------------------------------------------------------- */ 00284 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); 00285 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); 00286 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); 00287 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); 00288 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState); 00289 u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); 00290 FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG); 00291 void DMA_ClearFlag(u32 DMA_FLAG); 00292 ITStatus DMA_GetITStatus(u32 DMA_IT); 00293 void DMA_ClearITPendingBit(u32 DMA_IT); 00294 00295 #endif /*__STM32F10x_DMA_H */ 00296 00297 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/