Contiki 2.6

cc2430_sfr.h

Go to the documentation of this file.
00001 /**
00002  *
00003  * \file cc2430_sfr.h
00004  * \brief CC2430 registers header file for CC2430.
00005  *
00006  *  Definitions for CC2430 SFR registers.
00007  *   
00008  *      
00009  */
00010 
00011 #ifndef REG_CC2430_H
00012 #define REG_CC2430_H
00013 
00014 #include "8051def.h"
00015 
00016 /*  BYTE Register  */
00017 
00018 __sfr __at (0x80) P0   ;
00019 /* P0 */
00020 __sbit __at (0x87) P0_7 ;
00021 __sbit __at (0x86) P0_6 ;
00022 __sbit __at (0x85) P0_5 ;
00023 __sbit __at (0x84) P0_4 ;
00024 __sbit __at (0x83) P0_3 ;
00025 __sbit __at (0x82) P0_2 ;
00026 __sbit __at (0x81) P0_1 ;
00027 __sbit __at (0x80) P0_0 ;
00028 
00029 __sfr __at (0x81) SP   ;
00030 __sfr __at (0x82) DPL0  ;
00031 __sfr __at (0x83) DPH0  ;
00032 /*DPL and DPH correspond DPL0 and DPH0 (82-83)*/
00033 __sfr __at (0x84)   DPL1;
00034 __sfr __at (0x85)   DPH1;
00035 __sfr __at (0x86)   U0CSR;
00036 #define U_MODE  0x80
00037 #define U_RE    0x40
00038 #define U_SLAVE 0x20
00039 #define U_FE    0x10
00040 #define U_ERR   0x08
00041 #define U_RXB   0x04
00042 #define U_TXB   0x02
00043 #define U_ACTIVE 0x01
00044 
00045 __sfr __at (0x87) PCON ;
00046 /*  PCON (0x87) */
00047 #define IDLE 0x01
00048 
00049 __sfr __at (0x88) TCON ;
00050 /*  TCON (0x88) */
00051 __sbit __at (0x8F) TCON_URX1IF;
00052 /*__sbit __at (0x8E) RES;*/
00053 __sbit __at (0x8D) TCON_ADCIF;
00054 /*__sbit __at (0x8C) RES;*/
00055 __sbit __at (0x8B) TCON_URX0IF;
00056 __sbit __at (0x8A) TCON_IT1;
00057 __sbit __at (0x89) TCON_RFERRIF;
00058 __sbit __at (0x88) TCON_IT0;
00059 
00060 
00061 __sfr __at (0x89)   P0IFG;
00062 __sfr __at (0x8A)   P1IFG;
00063 __sfr __at (0x8B)   P2IFG;
00064 __sfr __at (0x8C)   PICTL;
00065 /*PICTL bits*/
00066 #define PADSC   0x40
00067 #define P2IEN   0x20
00068 #define P0IENH  0x10
00069 #define P0IENL  0x08
00070 #define P2ICON  0x04
00071 #define P1ICON  0x02
00072 #define P0ICON  0x01
00073 
00074 __sfr __at (0x8D)   P1IEN;
00075 __sfr __at (0x8F)   P0INP;
00076 
00077 __sfr __at (0x90) P1   ;
00078 /* P1 */
00079 __sbit __at (0x90) P1_0 ;
00080 __sbit __at (0x91) P1_1 ;
00081 __sbit __at (0x92) P1_2 ;
00082 __sbit __at (0x93) P1_3 ;
00083 __sbit __at (0x94) P1_4 ;
00084 __sbit __at (0x95) P1_5 ;
00085 __sbit __at (0x96) P1_6 ;
00086 __sbit __at (0x97) P1_7 ;
00087 
00088 __sfr __at (0x91)   RFIM;
00089 __sfr __at (0x92)   DPS;
00090 __sfr __at (0x93)   _XPAGE; /*MPAGE as paging register for sdcc*/
00091 __sfr __at (0x94)   T2CMP;
00092 __sfr __at (0x95)   ST0;
00093 __sfr __at (0x96)   ST1;
00094 __sfr __at (0x97)   ST2;
00095 __sfr __at (0x98)   S0CON ;
00096 
00097 __sbit __at (0x99) S0CON_ENCIF_1;
00098 __sbit __at (0x98) S0CON_ENCIF_0;
00099 
00100 __sfr __at (0x99)   HSRC;
00101 __sfr __at (0x9A)   IEN2;
00102 /*IEN2 bits*/
00103 #define WDTIE   0x20
00104 #define P1IE    0x10
00105 #define UTX1IE  0x08
00106 #define UTX0IE  0x04
00107 #define P2IE    0x02
00108 #define RFIE    0x01
00109 __sfr __at (0x9B)   S1CON;
00110 /*S1CON bits*/
00111 #define RFIF_1  0x02
00112 #define RFIF_0  0x01
00113 __sfr __at (0x9C)   T2PEROF0;
00114 __sfr __at (0x9D)   T2PEROF1;
00115 __sfr __at (0x9E)   T2PEROF2;
00116 /*T2PEROF2 bits*/
00117 #define CMPIM   0x80
00118 #define PERIM   0x40
00119 #define OFCMPIM 0x20
00120 
00121 #define PEROF23 0x08
00122 #define PEROF22 0x04
00123 #define PEROF21 0x02
00124 #define PEROF20 0x01
00125 
00126 __sfr __at (0x9F) FMAP;
00127 __sfr __at (0x9F) PSBANK;
00128 
00129 __sfr __at (0xA0) P2   ;
00130 /* P2 */
00131 __sbit __at (0xA0) P2_0 ;
00132 __sbit __at (0xA1) P2_1 ;
00133 __sbit __at (0xA2) P2_2 ;
00134 __sbit __at (0xA3) P2_3 ;
00135 __sbit __at (0xA4) P2_4 ;
00136 /*__sbit __at (0xA5) P2_5 ;
00137 __sbit __at (0xA6) P2_6 ;
00138 __sbit __at (0xA7) P2_7 ;*/
00139 
00140 __sfr __at (0xA1)   T2OF0;
00141 __sfr __at (0xA2)   T2OF1;
00142 __sfr __at (0xA3)   T2OF2;
00143 __sfr __at (0xA4)   T2CAPLPL;
00144 __sfr __at (0xA5)   T2CAPHPH;
00145 __sfr __at (0xA6)   T2TLD;
00146 __sfr __at (0xA7)   T2THD;
00147 
00148 __sfr __at (0xA8) IE   ;
00149 __sfr __at (0xA8)   IEN0;
00150 /*IEN0 bits*/
00151 #define IEN0_EA_MASK    0x80
00152 #define STIE    0x20
00153 #define ENCIE   0x10
00154 #define URX1IE  0x08
00155 #define URX0IE  0x04
00156 #define ADCIE   0x02
00157 #define RFERRIE 0x01
00158 /*  IEN0 (0xA8) */
00159 __sbit __at (0xAF) EA;
00160 __sbit __at (0xAF) IEN0_EA;
00161 /*__sbit __at (0xAE) RES;*/
00162 __sbit __at (0xAD) IEN0_STIE;
00163 __sbit __at (0xAC) IEN0_ENCIE;
00164 __sbit __at (0xAB) IEN0_URX1IE;
00165 __sbit __at (0xAA) IEN0_URX0IE;
00166 __sbit __at (0xA9) IEN0_ADCIE;
00167 __sbit __at (0xA8) IEN0_RFERRIE;
00168 
00169 __sfr __at (0xA9)   IP0;
00170 /*IP0 bits*/
00171 #define IP0_5   0x20
00172 #define IP0_4   0x10
00173 #define IP0_3   0x08
00174 #define IP0_2   0x04
00175 #define IP0_1   0x02
00176 #define IP0_0   0x01
00177 __sfr __at (0xAB)   FWT;
00178 __sfr __at (0xAC)   FADDRL;
00179 __sfr __at (0xAD)   FADDRH;
00180 
00181 __sfr __at (0xAE)   FCTL;
00182 #define F_BUSY  0x80
00183 #define F_SWBSY 0x40
00184 #define F_CONTRD 0x10
00185 #define F_WRITE 0x02
00186 #define F_ERASE 0x01
00187 __sfr __at (0xAF)   FWDATA;
00188 
00189 /*No port 3 (0xB0)*/
00190 __sfr __at (0xB1)   ENCDI;
00191 __sfr __at (0xB2)   ENCDO;
00192 __sfr __at (0xB3)   ENCCS;
00193 #define CCS_MODE2       0x40
00194 #define CCS_MODE1       0x20
00195 #define CCS_MODE0       0x10
00196 #define CCS_RDY         0x08
00197 #define CCS_CMD1        0x04
00198 #define CCS_CMD0        0x02
00199 #define CCS_ST          0x01
00200 __sfr __at (0xB4)   ADCCON1;
00201 /*ADCCON1 bits*/
00202 #define ADEOC   0x80
00203 #define ADST    0x40
00204 #define ADSTS1  0x20
00205 #define ADSTS0  0x10
00206 #define ADRCTRL1        0x08
00207 #define ADRCTRL0        0x04
00208 __sfr __at (0xB5)   ADCCON2;
00209 /*ADCCON2 bits*/
00210 #define ADSREF1 0x80
00211 #define ADSREF0 0x40
00212 #define ADSDIV1 0x20
00213 #define ADSDIV0 0x10
00214 #define ADSCH3  0x08
00215 #define ADSCH2  0x04
00216 #define ADSCH1  0x02
00217 #define ADSCH0  0x01
00218 __sfr __at (0xB6)   ADCCON3;
00219 /*ADCCON3 bits*/
00220 #define ADEREF1 0x80
00221 #define ADEREF0 0x40
00222 #define ADEDIV1 0x20
00223 #define ADEDIV0 0x10
00224 #define ADECH3  0x08
00225 #define ADECH2  0x04
00226 #define ADECH1  0x02
00227 #define ADECH0  0x01
00228 
00229 __sfr __at (0xB7)   RCCTL;
00230 #undef IP  /*this is 0xb8 in base core*/
00231 
00232 __sfr __at (0xB8)   IEN1;
00233 /*IEN1 bits*/
00234 #define P0IE    0x20
00235 #define T4IE    0x10
00236 #define T3IE    0x08
00237 #define T2IE    0x04
00238 #define T1IE    0x02
00239 #define DMAIE   0x01
00240 /*  IEN1 (0xB8) */
00241 /*__sbit __at (0xBF) IEN1_RES;*/
00242 /*__sbit __at (0xBE) RES;*/
00243 __sbit __at (0xBD) IEN1_P0IE;
00244 __sbit __at (0xBC) IEN1_T4IE;
00245 __sbit __at (0xBB) IEN1_T3IE;
00246 __sbit __at (0xBA) IEN1_T2IE;
00247 __sbit __at (0xB9) IEN1_T1IE;
00248 __sbit __at (0xB8) IEN1_DMAIE;
00249 
00250 __sfr __at (0xB9)   IP1;
00251 /*IP1 bits*/
00252 #define IP1_5   0x20
00253 #define IP1_4   0x10
00254 #define IP1_3   0x08
00255 #define IP1_2   0x04
00256 #define IP1_1   0x02
00257 #define IP1_0   0x01
00258 
00259 __sfr __at (0xBA)   ADCL;
00260 __sfr __at (0xBB)   ADCH;
00261 __sfr __at (0xBC)   RNDL;
00262 __sfr __at (0xBD)   RNDH;
00263 
00264 __sfr __at (0xBE)   SLEEP;
00265 #define OSC32K_CALDIS  0x80
00266 #define XOSC_STB        0x40
00267 #define HFRC_STB        0x20
00268 #define RST1            0x10
00269 #define RST0            0x08
00270 #define OSC_PD          0x04
00271 #define SLEEP_MODE1     0x02
00272 #define SLEEP_MODE0     0x01
00273 
00274 __sfr __at (0xC0)   IRCON;
00275 /*IRCON bits*/
00276 #define STIF    0x80
00277 #define P0IF    0x20
00278 #define T4IF    0x10
00279 #define T3IF    0x08
00280 #define T2IF    0x04
00281 #define T1IF    0x02
00282 #define DMAIF   0x01
00283 /* IRCON */
00284 __sbit __at (0xC7) IRCON_STIF ;
00285 /*__sbit __at (0x86) IRCON_6 ;*/
00286 __sbit __at (0xC5) IRCON_P0IF;
00287 __sbit __at (0xC4) IRCON_T4IF;
00288 __sbit __at (0xC3) IRCON_T3IF;
00289 __sbit __at (0xC2) IRCON_T2IF;
00290 __sbit __at (0xC1) IRCON_T1IF;
00291 __sbit __at (0xC0) IRCON_DMAIF;
00292 
00293 __sfr __at (0xC1)   U0BUF;
00294 
00295 __sfr __at (0xC2)   U0BAUD;
00296 __sfr __at (0xC3)   T2CNF;
00297 /*T2SEL bits*/
00298 #define CMPIF   0x80
00299 #define PERIF   0x40
00300 #define OFCMPIF 0x20
00301 
00302 #define CMSEL   0x08
00303 
00304 #define SYNC    0x02
00305 #define RUN     0x01
00306 
00307 __sfr __at (0xC4)   U0UCR;
00308 #define U_FLUSH         0x80
00309 #define U_FLOW          0x40
00310 #define U_D9            0x20
00311 #define U_BIT9          0x10
00312 #define U_PARITY        0x08
00313 #define U_SPB           0x04
00314 #define U_STOP          0x02
00315 #define U_START         0x01
00316 
00317 __sfr __at (0xC5)   U0GCR;
00318 #define U_CPOL          0x80
00319 #define U_CPHA          0x40
00320 #define U_ORDER         0x20
00321 #define U_BAUD_E4       0x10
00322 #define U_BAUD_E3       0x08
00323 #define U_BAUD_E2       0x04
00324 #define U_BAUD_E1       0x02
00325 #define U_BAUD_E0       0x01
00326 
00327 __sfr __at (0xC6)   CLKCON;
00328 #define OSC32K          0x80
00329 #define OSC             0x40
00330 #define TICKSPD2        0x20
00331 #define TICKSPD1        0x10
00332 #define TICKSPD0        0x08
00333 #define CLKSPD          0x01
00334 
00335 __sfr __at (0xC7)   MEMCTR;
00336 #define MUNIF    0x40
00337 __sfr __at (0xC8)   T2CON;
00338 
00339 __sfr __at (0xC9)   WDCTL;
00340 #define WDT_CLR3 0x80
00341 #define WDT_CLR2 0x40
00342 #define WDT_CLR1 0x20
00343 #define WDT_CLR0 0x10
00344 #define WDT_EN   0x08
00345 #define WDT_MODE 0x04
00346 #define WDT_INT1 0x02
00347 #define WDT_INT0 0x01
00348 
00349 __sfr __at (0xCA)   T3CNT;
00350 
00351 __sfr __at (0xCB)   T3CTL;
00352 /*T3CTL bits*/
00353 #define T3DIV2  0x80
00354 #define T3DIV1  0x40
00355 #define T3DIV0  0x20
00356 #define T3START 0x10
00357 #define T3OVFIM 0x08
00358 #define T3CLR   0x04
00359 #define T3MODE1 0x02
00360 #define T3MODE0 0x01
00361 
00362 __sfr __at (0xCC)   T3CCTL0;
00363 /*T3CCTL0 bits*/
00364 #define T3IM    0x40
00365 #define T3CMP2  0x20
00366 #define T3CMP1  0x10
00367 #define T3CMP0  0x08
00368 #define T3MODE  0x04
00369 #define T3CAP1  0x02
00370 #define T3CAP0  0x01
00371 
00372 __sfr __at (0xCD)   T3CC0;
00373 __sfr __at (0xCE)   T3CCTL1;
00374 /*T3CCTL0 bits apply*/
00375 __sfr __at (0xCF)   T3CC1;
00376 
00377 __sfr __at (0xD0) PSW  ;
00378 /*  PSW   */
00379 __sbit __at (0xD0) P    ;
00380 __sbit __at (0xD1) F1   ;
00381 __sbit __at (0xD2) OV   ;
00382 __sbit __at (0xD3) RS0  ;
00383 __sbit __at (0xD4) RS1  ;
00384 __sbit __at (0xD5) F0   ;
00385 __sbit __at (0xD6) AC   ;
00386 __sbit __at (0xD7) CY   ;
00387 
00388 __sfr __at (0xD1)   DMAIRQ;
00389 /*DMAIRQ bits*/
00390 #define DMAIF4  0x10
00391 #define DMAIF3  0x08
00392 #define DMAIF2  0x04
00393 #define DMAIF1  0x02
00394 #define DMAIF0  0x01
00395 
00396 __sfr __at (0xD2)   DMA1CFGL;
00397 __sfr __at (0xD3)   DMA1CFGH;
00398 __sfr __at (0xD4)   DMA0CFGL;
00399 __sfr __at (0xD5)   DMA0CFGH;
00400 
00401 __sfr __at (0xD6)   DMAARM;
00402 /*DMAARM bits*/
00403 #define ABORT   0x80
00404 #define DMAARM4 0x10
00405 #define DMAARM3 0x08
00406 #define DMAARM2 0x04
00407 #define DMAARM1 0x02
00408 #define DMAARM0 0x01
00409 
00410 __sfr __at (0xD7)   DMAREQ;
00411 /*DMAREQ bits*/
00412 #define DMAREQ4 0x10
00413 #define DMAREQ3 0x08
00414 #define DMAREQ2 0x04
00415 #define DMAREQ1 0x02
00416 #define DMAREQ0 0x01
00417 
00418 __sfr __at (0xD8)   TIMIF;
00419 /*TIMIF bits*/
00420 #define OVFIM   0x40
00421 #define T4CH1IF 0x20
00422 #define T4CH0IF 0x10
00423 #define T4OVFIF 0x08
00424 #define T3CH1IF 0x04
00425 #define T3CH0IF 0x02
00426 #define T3OVFIF 0x01
00427 
00428 __sfr __at (0xD9)   RFD;
00429 __sfr __at (0xDA)   T1CC0L;
00430 __sfr __at (0xDB)   T1CC0H;
00431 __sfr __at (0xDC)   T1CC1L;
00432 __sfr __at (0xDD)   T1CC1H;
00433 __sfr __at (0xDE)   T1CC2L;
00434 __sfr __at (0xDF)   T1CC2H;
00435 
00436 __sfr __at (0xE0)   ACC;
00437 __sfr __at (0xE1)   RFST;
00438 __sfr __at (0xE2)   T1CNTL;
00439 __sfr __at (0xE3)   T1CNTH;
00440 
00441 __sfr __at (0xE4)   T1CTL;
00442 /*T1CTL bits*/
00443 #define CH2IF   0x80
00444 #define CH1IF   0x40
00445 #define CH0IF   0x20
00446 #define OVFIF   0x10
00447 #define T1DIV1  0x08
00448 #define T1DIV0  0x04
00449 #define T1MODE1 0x02
00450 #define T1MODE0 0x01
00451 
00452 __sfr __at (0xE5)   T1CCTL0;
00453 /*T1CCTL0 bits*/
00454 #define T1CPSEL 0x80
00455 #define T1IM    0x40
00456 #define T1CMP2  0x20
00457 #define T1CMP1  0x10
00458 #define T1CMP0  0x08
00459 #define T1MODE  0x04
00460 #define T1CAP1  0x02
00461 #define T1CAP0  0x01
00462 
00463 __sfr __at (0xE6)   T1CCTL1;
00464 /*Bits defined in T1CCTL0 */
00465 __sfr __at (0xE7)   T1CCTL2;
00466 /*Bits defined in T1CCTL0 */
00467 __sfr __at (0xE8)   IRCON2;
00468 /*IRCON2 bits*/
00469 #define WDTIF   0x10
00470 #define P1IF    0x08
00471 #define UTX1IF  0x04
00472 #define UTX0IF  0x02
00473 #define P2IF    0x01
00474 /* IRCON 2 */ 
00475 /*__sbit __at (0xEF) IRCON2_P1_7 ;
00476 __sbit __at (0xEE) IRCON2_P1_6 ;
00477 __sbit __at (0xED) IRCON2_P1_5 ;*/
00478 __sbit __at (0xEC) IRCON2_WDTIF ;
00479 __sbit __at (0xEB) IRCON2_P1IF ;
00480 __sbit __at (0xEA) IRCON2_UTX1IF ;
00481 __sbit __at (0xE9) IRCON2_UTX0IF ;
00482 __sbit __at (0xE8) IRCON2_P2IF;
00483 
00484 
00485 __sfr __at (0xE9)   RFIF;
00486 /*RFIF bits*/
00487 #define IRQ_RREG_ON     0x80
00488 #define IRQ_TXDONE      0x40
00489 #define IRQ_FIFOP       0x20
00490 #define IRQ_SFD         0x10
00491 #define IRQ_CCA         0x08
00492 #define IRQ_CSP_WT      0x04
00493 #define IRQ_CSP_STOP    0x02
00494 #define IRQ_CSP_INT     0x01
00495 
00496 __sfr __at (0xEA)   T4CNT;
00497 __sfr __at (0xEB)   T4CTL;
00498 /*T4CTL bits*/
00499 #define T4DIV2  0x80
00500 #define T4DIV1  0x40
00501 #define T4DIV0  0x20
00502 #define T4START 0x10
00503 #define T4OVFIM 0x08
00504 #define T4CLR   0x04
00505 #define T4MODE1 0x02
00506 #define T4MODE0 0x01
00507 
00508 __sfr __at (0xEC)   T4CCTL0;
00509 /*T4CCTL0 bits*/
00510 #define T4IM    0x40
00511 #define T4CMP2  0x20
00512 #define T4CMP1  0x10
00513 #define T4CMP0  0x08
00514 #define T4MODE  0x04
00515 #define T4CAP1  0x02
00516 #define T4CAP0  0x01
00517 
00518 __sfr __at (0xED)   T4CC0;
00519 __sfr __at (0xEE)   T4CCTL1;
00520 /*T4CCTL0 bits apply*/
00521 __sfr __at (0xEF)   T4CC1;
00522 
00523 __sfr __at (0xF0) B    ;
00524 __sfr __at (0xF1)   PERCFG;
00525 /*PERCFG bits*/
00526 #define T1CFG   0x40
00527 #define T3CFG   0x20
00528 #define T4CFG   0x10
00529 #define U1CFG   0x02
00530 #define U0CFG   0x01
00531 
00532 __sfr __at (0xF2)   ADCCFG;
00533 /*ADCCFG bits*/
00534 #define ADC7EN  0x80
00535 #define ADC6EN  0x40
00536 #define ADC5EN  0x20
00537 #define ADC4EN  0x10
00538 #define ADC3EN  0x08
00539 #define ADC2EN  0x04
00540 #define ADC1EN  0x02
00541 #define ADC0EN  0x01
00542 
00543 __sfr __at (0xF3)   P0SEL;
00544 __sfr __at (0xF4)   P1SEL;
00545 __sfr __at (0xF5)   P2SEL;
00546 /*P2SEL bits*/
00547 #define PRI3P1  0x40
00548 #define PRI2P1  0x20
00549 #define PRI1P1  0x10
00550 #define PRI0P1  0x08
00551 #define SELP2_4 0x04
00552 #define SELP2_3 0x02
00553 #define SELP2_0 0x01
00554 
00555 __sfr __at (0xF6)   P1INP;
00556 
00557 __sfr __at (0xF7)   P2INP;
00558 /*P2INP bits*/
00559 #define PDUP2   0x80
00560 #define PDUP1   0x40
00561 #define PDUP0   0x20
00562 #define MDP2_4  0x10
00563 #define MDP2_3  0x08
00564 #define MDP2_2  0x04
00565 #define MDP2_1  0x02
00566 #define MDP2_0  0x01
00567 
00568 __sfr __at (0xF8)   U1CSR;
00569 __sfr __at (0xF9)   U1BUF;
00570 __sfr __at (0xFA)   U1BAUD;
00571 __sfr __at (0xFB)   U1UCR;
00572 __sfr __at (0xFC)   U1GCR;
00573 __sfr __at (0xFD)   P0DIR;
00574 __sfr __at (0xFE)   P1DIR;
00575 
00576 __sfr __at (0xFF)   P2DIR;
00577 /*P2DIR bits*/
00578 #define PRI1P0  0x80
00579 #define PRI0P0  0x40
00580 #define DIRP2_4 0x10
00581 #define DIRP2_3 0x08
00582 #define DIRP2_2 0x04
00583 #define DIRP2_1 0x02
00584 #define DIRP2_0 0x01
00585 
00586 /*  IEN0  */
00587 /*__sbit __at (0xA8) EA   ;
00588 __sbit __at (0x99) TI   ;
00589 __sbit __at (0x9A) RB8  ;
00590 __sbit __at (0x9B) TB8  ;
00591 __sbit __at (0x9C) REN  ;
00592 __sbit __at (0x9D) SM2  ;
00593 __sbit __at (0x9E) SM1  ;
00594 __sbit __at (0x9F) SM0  ;*/
00595 
00596 
00597 
00598 /* Interrupt numbers: address = (number * 8) + 3 */
00599 /*#undef IE0_VECTOR
00600 #undef TF0_VECTOR
00601 #undef IE1_VECTOR
00602 #undef TF1_VECTOR
00603 #undef SI0_VECTOR*/
00604 
00605 /* CC2430 interrupt vectors */
00606 #define RFERR_VECTOR    0
00607 #define ADC_VECTOR      1
00608 #define URX0_VECTOR     2
00609 #define URX1_VECTOR     3
00610 #define ENC_VECTOR      4
00611 #define ST_VECTOR       5
00612 #define P2INT_VECTOR    6
00613 #define UTX0_VECTOR     7
00614 #define DMA_VECTOR      8
00615 #define T1_VECTOR       9
00616 #define T2_VECTOR       10
00617 #define T3_VECTOR       11
00618 #define T4_VECTOR       12
00619 #define P0INT_VECTOR    13
00620 #define UTX1_VECTOR     14
00621 #define P1INT_VECTOR    15
00622 #define RF_VECTOR       16
00623 #define WDT_VECTOR      17
00624 
00625 /* RF control registers*/
00626 __xdata __at (0xDF02) unsigned char MDMCTRL0H;
00627 __xdata __at (0xDF03) unsigned char MDMCTRL0L;
00628 __xdata __at (0xDF04) unsigned char MDMCTRL1H;
00629 __xdata __at (0xDF05) unsigned char MDMCTRL1L;
00630 __xdata __at (0xDF06) unsigned char RSSIH;
00631 __xdata __at (0xDF07) unsigned char RSSIL;
00632 __xdata __at (0xDF08) unsigned char SYNCWORDH;
00633 __xdata __at (0xDF09) unsigned char SYNCWORDL;
00634 __xdata __at (0xDF0A) unsigned char TXCTRLH;
00635 __xdata __at (0xDF0B) unsigned char TXCTRLL;
00636 __xdata __at (0xDF0C) unsigned char RXCTRL0H;
00637 __xdata __at (0xDF0D) unsigned char RXCTRL0L;
00638 __xdata __at (0xDF0E) unsigned char RXCTRL1H;
00639 __xdata __at (0xDF0F) unsigned char RXCTRL1L;
00640 __xdata __at (0xDF10) unsigned char FSCTRLH;
00641 __xdata __at (0xDF11) unsigned char FSCTRLL;
00642 __xdata __at (0xDF12) unsigned char CSPX;
00643 __xdata __at (0xDF13) unsigned char CSPY;
00644 __xdata __at (0xDF14) unsigned char CSPZ;
00645 __xdata __at (0xDF15) unsigned char CSPCTRL;
00646 __xdata __at (0xDF16) unsigned char CSPT;
00647 __xdata __at (0xDF17) unsigned char RFPWR;
00648 #define ADI_RADIO_PD    0x10
00649 #define RREG_RADIO_PD   0x08
00650 #define RREG_DELAY_MASK 0x07
00651 
00652 __xdata __at (0xDF20) unsigned char FSMTCH;
00653 __xdata __at (0xDF21) unsigned char FSMTCL;
00654 __xdata __at (0xDF22) unsigned char MANANDH;
00655 __xdata __at (0xDF23) unsigned char MANANDL;
00656 __xdata __at (0xDF24) unsigned char MANORH;
00657 __xdata __at (0xDF25) unsigned char MANORL;
00658 __xdata __at (0xDF26) unsigned char AGCCTRLH;
00659 __xdata __at (0xDF27) unsigned char AGCCTRLL;
00660 
00661 __xdata __at (0xDF39) unsigned char FSMSTATE;
00662 __xdata __at (0xDF3A) unsigned char ADCTSTH;
00663 __xdata __at (0xDF3B) unsigned char ADCTSTL;
00664 __xdata __at (0xDF3C) unsigned char DACTSTH;
00665 __xdata __at (0xDF3D) unsigned char DACTSTL;
00666 
00667 __xdata __at (0xDF43) unsigned char IEEE_ADDR0;
00668 __xdata __at (0xDF44) unsigned char IEEE_ADDR1;
00669 __xdata __at (0xDF45) unsigned char IEEE_ADDR2;
00670 __xdata __at (0xDF46) unsigned char IEEE_ADDR3;
00671 __xdata __at (0xDF47) unsigned char IEEE_ADDR4;
00672 __xdata __at (0xDF48) unsigned char IEEE_ADDR5;
00673 __xdata __at (0xDF49) unsigned char IEEE_ADDR6;
00674 __xdata __at (0xDF4A) unsigned char IEEE_ADDR7;
00675 __xdata __at (0xDF4B) unsigned char PANIDH;
00676 __xdata __at (0xDF4C) unsigned char PANIDL;
00677 __xdata __at (0xDF4D) unsigned char SHORTADDRH;
00678 __xdata __at (0xDF4E) unsigned char SHORTADDRL;
00679 __xdata __at (0xDF4F) unsigned char IOCFG0;
00680 __xdata __at (0xDF50) unsigned char IOCFG1;
00681 __xdata __at (0xDF51) unsigned char IOCFG2;
00682 __xdata __at (0xDF52) unsigned char IOCFG3;
00683 __xdata __at (0xDF53) unsigned char RXFIFOCNT;
00684 __xdata __at (0xDF54) unsigned char FSMTC1;
00685 #define ABORTRX_ON_SRXON 0x20
00686 #define RX_INTERRUPTED  0x10
00687 #define AUTO_TX2RX_OFF  0x08
00688 #define RX2RX_TIME_OFF  0x04
00689 #define PENDING_OR      0x02
00690 #define ACCEPT_ACKPKT   0x01
00691 
00692 __xdata __at (0xDF60) unsigned char CHVER;
00693 __xdata __at (0xDF61) unsigned char CHIPID;
00694 __xdata __at (0xDF62) unsigned char RFSTATUS;
00695 #define TX_ACTIVE       0x10
00696 #define FIFO            0x08
00697 #define FIFOP           0x04
00698 #define SFD             0x02
00699 #define CCA             0x01
00700 
00701 __xdata __at (0xDFC1) unsigned char   U0BUF_SHADOW;
00702 
00703 __xdata __at (0xDFD9) unsigned char RFD_SHADOW;
00704 
00705 __xdata __at (0xDFF9) unsigned char U1BUF_SHADOW;
00706 
00707 __xdata __at (0xDFBA) unsigned int ADC_SHADOW;
00708 
00709 #endif /*REG_CC2430*/