Contiki 2.6

dma.c

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00001 /*
00002  * Copyright (c) 2007, Swedish Institute of Computer Science
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the Institute nor the names of its contributors
00014  *    may be used to endorse or promote products derived from this software
00015  *    without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
00018  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00020  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
00021  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00022  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00023  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00024  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00027  * SUCH DAMAGE.
00028  *
00029  * This file is part of the Contiki operating system.
00030  *
00031  */
00032 
00033 /**
00034  * \file
00035  *      DMA interrupt handling.
00036  * \author
00037  *      Nicolas Tsiftes <nvt@sics.se>
00038  */
00039 #include "contiki.h"
00040 
00041 #include "contiki-msb430.h"
00042 #include "dev/cc1020.h"
00043 #include "dev/dma.h"
00044 #include "isr_compat.h"
00045 
00046 static void (*callbacks[DMA_LINES])(void);
00047 
00048 ISR(DACDMA, irq_dacdma)
00049 {
00050   if(DMA0CTL & DMAIFG) {
00051     DMA0CTL &= ~(DMAIFG | DMAIE);
00052     if(callbacks[0] != NULL) {
00053       callbacks[0]();
00054     }
00055     _BIC_SR_IRQ(LPM3_bits);
00056   }
00057 
00058   if(DMA1CTL & DMAIFG) {
00059     DMA1CTL &= ~(DMAIFG | DMAIE);
00060     if(callbacks[1] != NULL) {
00061       callbacks[1]();
00062     }
00063     _BIC_SR_IRQ(LPM3_bits);
00064   }
00065 
00066   if(DMA2CTL & DMAIFG) {
00067     DMA2CTL &= ~(DMAIFG | DMAIE);
00068     if(callbacks[2] != NULL) {
00069       callbacks[2]();
00070     }
00071     _BIC_SR_IRQ(LPM3_bits);
00072   }
00073 
00074   if(DAC12_0CTL & DAC12IFG) {
00075     DAC12_0CTL &= ~(DAC12IFG | DAC12IE);
00076   }
00077 
00078   if(DAC12_1CTL & DAC12IFG) {
00079     DAC12_1CTL &= ~(DAC12IFG | DAC12IE);
00080   }
00081 }
00082 
00083 int
00084 dma_subscribe(int line, void (*callback)(void))
00085 {
00086   if(line >= DMA_LINES) {
00087     return -1;
00088   }
00089 
00090   callbacks[line] = callback;
00091   return 0;
00092 }
00093 
00094 void
00095 dma_transfer(unsigned char *dst, unsigned char *src, unsigned len)
00096 {
00097   /* Configure DMA Channel 0 for UART0 TXIFG. */
00098   DMACTL0 = DMA0TSEL_4;
00099 
00100   /* No DMAONFETCH, ROUNDROBIN, ENNMI. */
00101   DMACTL1 = 0x0000;
00102 
00103   /*
00104    * Set single transfer mode with byte-per-byte transfers.
00105    *
00106    * The source address is incremented for each byte, while the 
00107    * destination address remains constant.
00108    *
00109    * In order to avoid missing the first rising edge of the trigger
00110    * signal, it is important to use the level-sensitive trigger when 
00111    * using USART transfer interrupts.
00112    */
00113   DMA0CTL = DMADT_0 | DMADSTINCR_0 | DMASRCINCR_3 | DMASBDB | DMALEVEL;
00114 
00115   DMA0SA = (unsigned) src;
00116   DMA0DA = (unsigned) dst;
00117   DMA0SZ = len;
00118 
00119   DMA0CTL |= DMAEN | DMAIE;     /* enable DMA and interrupts */
00120   U0CTL &= ~SWRST;              /* enable the UART state machine */
00121 }