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00001 /* 00002 * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors 00003 * to the MC1322x project (http://mc1322x.devl.org) 00004 * All rights reserved. 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 1. Redistributions of source code must retain the above copyright 00010 * notice, this list of conditions and the following disclaimer. 00011 * 2. Redistributions in binary form must reproduce the above copyright 00012 * notice, this list of conditions and the following disclaimer in the 00013 * documentation and/or other materials provided with the distribution. 00014 * 3. Neither the name of the Institute nor the names of its contributors 00015 * may be used to endorse or promote products derived from this software 00016 * without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 00019 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00020 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00021 * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 00022 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00023 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 00024 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 00025 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00026 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00027 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00028 * SUCH DAMAGE. 00029 * 00030 * This file is part of libmc1322x: see http://mc1322x.devl.org 00031 * for details. 00032 * 00033 * 00034 */ 00035 00036 #include <mc1322x.h> 00037 #include <stdint.h> 00038 00039 static void (*tmr_isr_funcs[4])(void) = { 00040 tmr0_isr, 00041 tmr1_isr, 00042 tmr2_isr, 00043 tmr3_isr 00044 }; 00045 00046 void irq_register_timer_handler(int timer, void (*isr)(void)) 00047 { 00048 tmr_isr_funcs[timer] = isr; 00049 } 00050 00051 00052 __attribute__ ((section (".irq"))) 00053 __attribute__ ((interrupt("IRQ"))) 00054 void irq(void) 00055 { 00056 uint32_t pending; 00057 00058 while ((pending = *NIPEND)) { 00059 00060 if(bit_is_set(pending, INT_NUM_TMR)) { 00061 /* dispatch to individual timer isrs if they exist */ 00062 /* timer isrs are responsible for determining if they 00063 * caused an interrupt */ 00064 /* and clearing their own interrupt flags */ 00065 if (tmr_isr_funcs[0] != 0) { (tmr_isr_funcs[0])(); } 00066 if (tmr_isr_funcs[1] != 0) { (tmr_isr_funcs[1])(); } 00067 if (tmr_isr_funcs[2] != 0) { (tmr_isr_funcs[2])(); } 00068 if (tmr_isr_funcs[3] != 0) { (tmr_isr_funcs[3])(); } 00069 } 00070 00071 if(bit_is_set(pending, INT_NUM_MACA)) { 00072 if(maca_isr != 0) { maca_isr(); } 00073 } 00074 if(bit_is_set(pending, INT_NUM_UART1)) { 00075 if(uart1_isr != 0) { uart1_isr(); } 00076 } 00077 if(bit_is_set(pending, INT_NUM_UART2)) { 00078 if(uart2_isr != 0) { uart2_isr(); } 00079 } 00080 if(bit_is_set(pending, INT_NUM_CRM)) { 00081 if(rtc_wu_evt() && (rtc_isr != 0)) { rtc_isr(); } 00082 if(kbi_evnt(4) && (kbi4_isr != 0)) { kbi4_isr(); } 00083 if(kbi_evnt(5) && (kbi5_isr != 0)) { kbi5_isr(); } 00084 if(kbi_evnt(6) && (kbi6_isr != 0)) { kbi6_isr(); } 00085 if(kbi_evnt(7) && (kbi7_isr != 0)) { kbi7_isr(); } 00086 00087 if (CRM->STATUSbits.CAL_DONE && CRM->CAL_CNTLbits.CAL_IEN && cal_isr) 00088 { 00089 CRM->STATUSbits.CAL_DONE = 0; 00090 cal_isr(); 00091 } 00092 } 00093 if(bit_is_set(pending, INT_NUM_ASM)) { 00094 if(asm_isr != 0) { asm_isr(); } 00095 } 00096 if (bit_is_set(pending, INT_NUM_I2C)) { 00097 if (i2c_isr != 0) { i2c_isr(); } 00098 } 00099 00100 *INTFRC = 0; /* stop forcing interrupts */ 00101 00102 } 00103 }