Contiki 2.6
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00001 #ifndef __REGS_H__ 00002 #define __REGS_H__ 1 00003 00004 00005 #define ReadRegister(a) a 00006 #define WriteRegister(a, b) a = b 00007 00008 /* FLASH_BASE block */ 00009 #define DATA_FLASH_BASE_BASE (0x00000000u) 00010 #define DATA_FLASH_BASE_END (0x0001FFFFu) 00011 #define DATA_FLASH_BASE_SIZE (DATA_FLASH_BASE_END - DATA_FLASH_BASE_BASE + 1) 00012 00013 /* FLASH block */ 00014 #define DATA_FLASH_BASE (0x08000000u) 00015 #define DATA_FLASH_END (0x0801FFFFu) 00016 #define DATA_FLASH_SIZE (DATA_FLASH_END - DATA_FLASH_BASE + 1) 00017 00018 /* BIG_INFO_BASE block */ 00019 #define DATA_BIG_INFO_BASE_BASE (0x00000000u) 00020 #define DATA_BIG_INFO_BASE_END (0x000007FFu) 00021 #define DATA_BIG_INFO_BASE_SIZE (DATA_BIG_INFO_BASE_END - DATA_BIG_INFO_BASE_BASE + 1) 00022 00023 /* BIG_INFO block */ 00024 #define DATA_BIG_INFO_BASE (0x08040000u) 00025 #define DATA_BIG_INFO_END (0x080407FFu) 00026 #define DATA_BIG_INFO_SIZE (DATA_BIG_INFO_END - DATA_BIG_INFO_BASE + 1) 00027 00028 /* SMALL_INFO block */ 00029 #define DATA_SMALL_INFO_BASE (0x08040800u) 00030 #define DATA_SMALL_INFO_END (0x080409FFu) 00031 #define DATA_SMALL_INFO_SIZE (DATA_SMALL_INFO_END - DATA_SMALL_INFO_BASE + 1) 00032 00033 /* SRAM block */ 00034 #define DATA_SRAM_BASE (0x20000000u) 00035 #define DATA_SRAM_END (0x20001FFFu) 00036 #define DATA_SRAM_SIZE (DATA_SRAM_END - DATA_SRAM_BASE + 1) 00037 00038 /* CM_HV block */ 00039 #define DATA_CM_HV_BASE (0x40000000u) 00040 #define DATA_CM_HV_END (0x40000044u) 00041 #define DATA_CM_HV_SIZE (DATA_CM_HV_END - DATA_CM_HV_BASE + 1) 00042 00043 #define HV_SPARE *((volatile int32u *)0x40000000u) 00044 #define HV_SPARE_REG *((volatile int32u *)0x40000000u) 00045 #define HV_SPARE_ADDR (0x40000000u) 00046 #define HV_SPARE_RESET (0x00000000u) 00047 /* HV_SPARE field */ 00048 #define HV_SPARE_HV_SPARE (0x000000FFu) 00049 #define HV_SPARE_HV_SPARE_MASK (0x000000FFu) 00050 #define HV_SPARE_HV_SPARE_BIT (0) 00051 #define HV_SPARE_HV_SPARE_BITS (8) 00052 00053 #define EVENT_CTRL *((volatile int32u *)0x40000004u) 00054 #define EVENT_CTRL_REG *((volatile int32u *)0x40000004u) 00055 #define EVENT_CTRL_ADDR (0x40000004u) 00056 #define EVENT_CTRL_RESET (0x00000000u) 00057 /* LV_FREEZE field */ 00058 #define LV_FREEZE (0x00000002u) 00059 #define LV_FREEZE_MASK (0x00000002u) 00060 #define LV_FREEZE_BIT (1) 00061 #define LV_FREEZE_BITS (1) 00062 00063 #define SLEEPTMR_CLKEN *((volatile int32u *)0x40000008u) 00064 #define SLEEPTMR_CLKEN_REG *((volatile int32u *)0x40000008u) 00065 #define SLEEPTMR_CLKEN_ADDR (0x40000008u) 00066 #define SLEEPTMR_CLKEN_RESET (0x00000002u) 00067 /* SLEEPTMR_CLK10KEN field */ 00068 #define SLEEPTMR_CLK10KEN (0x00000002u) 00069 #define SLEEPTMR_CLK10KEN_MASK (0x00000002u) 00070 #define SLEEPTMR_CLK10KEN_BIT (1) 00071 #define SLEEPTMR_CLK10KEN_BITS (1) 00072 /* SLEEPTMR_CLK32KEN field */ 00073 #define SLEEPTMR_CLK32KEN (0x00000001u) 00074 #define SLEEPTMR_CLK32KEN_MASK (0x00000001u) 00075 #define SLEEPTMR_CLK32KEN_BIT (0) 00076 #define SLEEPTMR_CLK32KEN_BITS (1) 00077 00078 #define CLKRC_TUNE *((volatile int32u *)0x4000000Cu) 00079 #define CLKRC_TUNE_REG *((volatile int32u *)0x4000000Cu) 00080 #define CLKRC_TUNE_ADDR (0x4000000Cu) 00081 #define CLKRC_TUNE_RESET (0x00000000u) 00082 /* CLKRC_TUNE_FIELD field */ 00083 #define CLKRC_TUNE_FIELD (0x0000000Fu) 00084 #define CLKRC_TUNE_FIELD_MASK (0x0000000Fu) 00085 #define CLKRC_TUNE_FIELD_BIT (0) 00086 #define CLKRC_TUNE_FIELD_BITS (4) 00087 00088 #define CLK1K_CAL *((volatile int32u *)0x40000010u) 00089 #define CLK1K_CAL_REG *((volatile int32u *)0x40000010u) 00090 #define CLK1K_CAL_ADDR (0x40000010u) 00091 #define CLK1K_CAL_RESET (0x00005000u) 00092 /* CLK1K_INTEGER field */ 00093 #define CLK1K_INTEGER (0x0000F800u) 00094 #define CLK1K_INTEGER_MASK (0x0000F800u) 00095 #define CLK1K_INTEGER_BIT (11) 00096 #define CLK1K_INTEGER_BITS (5) 00097 /* CLK1K_FRACTIONAL field */ 00098 #define CLK1K_FRACTIONAL (0x000007FFu) 00099 #define CLK1K_FRACTIONAL_MASK (0x000007FFu) 00100 #define CLK1K_FRACTIONAL_BIT (0) 00101 #define CLK1K_FRACTIONAL_BITS (11) 00102 00103 #define REGEN_DSLEEP *((volatile int32u *)0x40000014u) 00104 #define REGEN_DSLEEP_REG *((volatile int32u *)0x40000014u) 00105 #define REGEN_DSLEEP_ADDR (0x40000014u) 00106 #define REGEN_DSLEEP_RESET (0x00000001u) 00107 /* REGEN_DSLEEP_FIELD field */ 00108 #define REGEN_DSLEEP_FIELD (0x00000001u) 00109 #define REGEN_DSLEEP_FIELD_MASK (0x00000001u) 00110 #define REGEN_DSLEEP_FIELD_BIT (0) 00111 #define REGEN_DSLEEP_FIELD_BITS (1) 00112 00113 #define VREG *((volatile int32u *)0x40000018u) 00114 #define VREG_REG *((volatile int32u *)0x40000018u) 00115 #define VREG_ADDR (0x40000018u) 00116 #define VREG_RESET (0x00000207u) 00117 /* VREF_EN field */ 00118 #define VREG_VREF_EN (0x00008000u) 00119 #define VREG_VREF_EN_MASK (0x00008000u) 00120 #define VREG_VREF_EN_BIT (15) 00121 #define VREG_VREF_EN_BITS (1) 00122 /* VREF_TEST field */ 00123 #define VREG_VREF_TEST (0x00004000u) 00124 #define VREG_VREF_TEST_MASK (0x00004000u) 00125 #define VREG_VREF_TEST_BIT (14) 00126 #define VREG_VREF_TEST_BITS (1) 00127 /* VREG_1V8_EN field */ 00128 #define VREG_VREG_1V8_EN (0x00000800u) 00129 #define VREG_VREG_1V8_EN_MASK (0x00000800u) 00130 #define VREG_VREG_1V8_EN_BIT (11) 00131 #define VREG_VREG_1V8_EN_BITS (1) 00132 /* VREG_1V8_TEST field */ 00133 #define VREG_VREG_1V8_TEST (0x00000400u) 00134 #define VREG_VREG_1V8_TEST_MASK (0x00000400u) 00135 #define VREG_VREG_1V8_TEST_BIT (10) 00136 #define VREG_VREG_1V8_TEST_BITS (1) 00137 /* VREG_1V8_TRIM field */ 00138 #define VREG_VREG_1V8_TRIM (0x00000380u) 00139 #define VREG_VREG_1V8_TRIM_MASK (0x00000380u) 00140 #define VREG_VREG_1V8_TRIM_BIT (7) 00141 #define VREG_VREG_1V8_TRIM_BITS (3) 00142 /* VREG_1V2_EN field */ 00143 #define VREG_VREG_1V2_EN (0x00000010u) 00144 #define VREG_VREG_1V2_EN_MASK (0x00000010u) 00145 #define VREG_VREG_1V2_EN_BIT (4) 00146 #define VREG_VREG_1V2_EN_BITS (1) 00147 /* VREG_1V2_TEST field */ 00148 #define VREG_VREG_1V2_TEST (0x00000008u) 00149 #define VREG_VREG_1V2_TEST_MASK (0x00000008u) 00150 #define VREG_VREG_1V2_TEST_BIT (3) 00151 #define VREG_VREG_1V2_TEST_BITS (1) 00152 /* VREG_1V2_TRIM field */ 00153 #define VREG_VREG_1V2_TRIM (0x00000007u) 00154 #define VREG_VREG_1V2_TRIM_MASK (0x00000007u) 00155 #define VREG_VREG_1V2_TRIM_BIT (0) 00156 #define VREG_VREG_1V2_TRIM_BITS (3) 00157 00158 #define WAKE_SEL *((volatile int32u *)0x40000020u) 00159 #define WAKE_SEL_REG *((volatile int32u *)0x40000020u) 00160 #define WAKE_SEL_ADDR (0x40000020u) 00161 #define WAKE_SEL_RESET (0x00000200u) 00162 /* WAKE_CSYSPWRUPREQ field */ 00163 #define WAKE_CSYSPWRUPREQ (0x00000200u) 00164 #define WAKE_CSYSPWRUPREQ_MASK (0x00000200u) 00165 #define WAKE_CSYSPWRUPREQ_BIT (9) 00166 #define WAKE_CSYSPWRUPREQ_BITS (1) 00167 /* WAKE_CDBGPWRUPREQ field */ 00168 #define WAKE_CDBGPWRUPREQ (0x00000100u) 00169 #define WAKE_CDBGPWRUPREQ_MASK (0x00000100u) 00170 #define WAKE_CDBGPWRUPREQ_BIT (8) 00171 #define WAKE_CDBGPWRUPREQ_BITS (1) 00172 /* WAKE_WAKE_CORE field */ 00173 #define WAKE_WAKE_CORE (0x00000080u) 00174 #define WAKE_WAKE_CORE_MASK (0x00000080u) 00175 #define WAKE_WAKE_CORE_BIT (7) 00176 #define WAKE_WAKE_CORE_BITS (1) 00177 /* WAKE_SLEEPTMRWRAP field */ 00178 #define WAKE_SLEEPTMRWRAP (0x00000040u) 00179 #define WAKE_SLEEPTMRWRAP_MASK (0x00000040u) 00180 #define WAKE_SLEEPTMRWRAP_BIT (6) 00181 #define WAKE_SLEEPTMRWRAP_BITS (1) 00182 /* WAKE_SLEEPTMRCMPB field */ 00183 #define WAKE_SLEEPTMRCMPB (0x00000020u) 00184 #define WAKE_SLEEPTMRCMPB_MASK (0x00000020u) 00185 #define WAKE_SLEEPTMRCMPB_BIT (5) 00186 #define WAKE_SLEEPTMRCMPB_BITS (1) 00187 /* WAKE_SLEEPTMRCMPA field */ 00188 #define WAKE_SLEEPTMRCMPA (0x00000010u) 00189 #define WAKE_SLEEPTMRCMPA_MASK (0x00000010u) 00190 #define WAKE_SLEEPTMRCMPA_BIT (4) 00191 #define WAKE_SLEEPTMRCMPA_BITS (1) 00192 /* WAKE_IRQD field */ 00193 #define WAKE_IRQD (0x00000008u) 00194 #define WAKE_IRQD_MASK (0x00000008u) 00195 #define WAKE_IRQD_BIT (3) 00196 #define WAKE_IRQD_BITS (1) 00197 /* WAKE_SC2 field */ 00198 #define WAKE_SC2 (0x00000004u) 00199 #define WAKE_SC2_MASK (0x00000004u) 00200 #define WAKE_SC2_BIT (2) 00201 #define WAKE_SC2_BITS (1) 00202 /* WAKE_SC1 field */ 00203 #define WAKE_SC1 (0x00000002u) 00204 #define WAKE_SC1_MASK (0x00000002u) 00205 #define WAKE_SC1_BIT (1) 00206 #define WAKE_SC1_BITS (1) 00207 /* GPIO_WAKE field */ 00208 #define GPIO_WAKE (0x00000001u) 00209 #define GPIO_WAKE_MASK (0x00000001u) 00210 #define GPIO_WAKE_BIT (0) 00211 #define GPIO_WAKE_BITS (1) 00212 00213 #define WAKE_CORE *((volatile int32u *)0x40000024u) 00214 #define WAKE_CORE_REG *((volatile int32u *)0x40000024u) 00215 #define WAKE_CORE_ADDR (0x40000024u) 00216 #define WAKE_CORE_RESET (0x00000000u) 00217 /* WAKE_CORE_FIELD field */ 00218 #define WAKE_CORE_FIELD (0x00000020u) 00219 #define WAKE_CORE_FIELD_MASK (0x00000020u) 00220 #define WAKE_CORE_FIELD_BIT (5) 00221 #define WAKE_CORE_FIELD_BITS (1) 00222 00223 #define PWRUP_EVENT *((volatile int32u *)0x40000028u) 00224 #define PWRUP_EVENT_REG *((volatile int32u *)0x40000028u) 00225 #define PWRUP_EVENT_ADDR (0x40000028u) 00226 #define PWRUP_EVENT_RESET (0x00000000u) 00227 /* PWRUP_CSYSPWRUPREQ field */ 00228 #define PWRUP_CSYSPWRUPREQ (0x00000200u) 00229 #define PWRUP_CSYSPWRUPREQ_MASK (0x00000200u) 00230 #define PWRUP_CSYSPWRUPREQ_BIT (9) 00231 #define PWRUP_CSYSPWRUPREQ_BITS (1) 00232 /* PWRUP_CDBGPWRUPREQ field */ 00233 #define PWRUP_CDBGPWRUPREQ (0x00000100u) 00234 #define PWRUP_CDBGPWRUPREQ_MASK (0x00000100u) 00235 #define PWRUP_CDBGPWRUPREQ_BIT (8) 00236 #define PWRUP_CDBGPWRUPREQ_BITS (1) 00237 /* PWRUP_WAKECORE field */ 00238 #define PWRUP_WAKECORE (0x00000080u) 00239 #define PWRUP_WAKECORE_MASK (0x00000080u) 00240 #define PWRUP_WAKECORE_BIT (7) 00241 #define PWRUP_WAKECORE_BITS (1) 00242 /* PWRUP_SLEEPTMRWRAP field */ 00243 #define PWRUP_SLEEPTMRWRAP (0x00000040u) 00244 #define PWRUP_SLEEPTMRWRAP_MASK (0x00000040u) 00245 #define PWRUP_SLEEPTMRWRAP_BIT (6) 00246 #define PWRUP_SLEEPTMRWRAP_BITS (1) 00247 /* PWRUP_SLEEPTMRCOMPB field */ 00248 #define PWRUP_SLEEPTMRCOMPB (0x00000020u) 00249 #define PWRUP_SLEEPTMRCOMPB_MASK (0x00000020u) 00250 #define PWRUP_SLEEPTMRCOMPB_BIT (5) 00251 #define PWRUP_SLEEPTMRCOMPB_BITS (1) 00252 /* PWRUP_SLEEPTMRCOMPA field */ 00253 #define PWRUP_SLEEPTMRCOMPA (0x00000010u) 00254 #define PWRUP_SLEEPTMRCOMPA_MASK (0x00000010u) 00255 #define PWRUP_SLEEPTMRCOMPA_BIT (4) 00256 #define PWRUP_SLEEPTMRCOMPA_BITS (1) 00257 /* PWRUP_IRQD field */ 00258 #define PWRUP_IRQD (0x00000008u) 00259 #define PWRUP_IRQD_MASK (0x00000008u) 00260 #define PWRUP_IRQD_BIT (3) 00261 #define PWRUP_IRQD_BITS (1) 00262 /* PWRUP_SC2 field */ 00263 #define PWRUP_SC2 (0x00000004u) 00264 #define PWRUP_SC2_MASK (0x00000004u) 00265 #define PWRUP_SC2_BIT (2) 00266 #define PWRUP_SC2_BITS (1) 00267 /* PWRUP_SC1 field */ 00268 #define PWRUP_SC1 (0x00000002u) 00269 #define PWRUP_SC1_MASK (0x00000002u) 00270 #define PWRUP_SC1_BIT (1) 00271 #define PWRUP_SC1_BITS (1) 00272 /* PWRUP_GPIO field */ 00273 #define PWRUP_GPIO (0x00000001u) 00274 #define PWRUP_GPIO_MASK (0x00000001u) 00275 #define PWRUP_GPIO_BIT (0) 00276 #define PWRUP_GPIO_BITS (1) 00277 00278 #define RESET_EVENT *((volatile int32u *)0x4000002Cu) 00279 #define RESET_EVENT_REG *((volatile int32u *)0x4000002Cu) 00280 #define RESET_EVENT_ADDR (0x4000002Cu) 00281 #define RESET_EVENT_RESET (0x00000001u) 00282 /* RESET_CPULOCKUP field */ 00283 #define RESET_CPULOCKUP (0x00000080u) 00284 #define RESET_CPULOCKUP_MASK (0x00000080u) 00285 #define RESET_CPULOCKUP_BIT (7) 00286 #define RESET_CPULOCKUP_BITS (1) 00287 /* RESET_OPTBYTEFAIL field */ 00288 #define RESET_OPTBYTEFAIL (0x00000040u) 00289 #define RESET_OPTBYTEFAIL_MASK (0x00000040u) 00290 #define RESET_OPTBYTEFAIL_BIT (6) 00291 #define RESET_OPTBYTEFAIL_BITS (1) 00292 /* RESET_DSLEEP field */ 00293 #define RESET_DSLEEP (0x00000020u) 00294 #define RESET_DSLEEP_MASK (0x00000020u) 00295 #define RESET_DSLEEP_BIT (5) 00296 #define RESET_DSLEEP_BITS (1) 00297 /* RESET_SW field */ 00298 #define RESET_SW (0x00000010u) 00299 #define RESET_SW_MASK (0x00000010u) 00300 #define RESET_SW_BIT (4) 00301 #define RESET_SW_BITS (1) 00302 /* RESET_WDOG field */ 00303 #define RESET_WDOG (0x00000008u) 00304 #define RESET_WDOG_MASK (0x00000008u) 00305 #define RESET_WDOG_BIT (3) 00306 #define RESET_WDOG_BITS (1) 00307 /* RESET_NRESET field */ 00308 #define RESET_NRESET (0x00000004u) 00309 #define RESET_NRESET_MASK (0x00000004u) 00310 #define RESET_NRESET_BIT (2) 00311 #define RESET_NRESET_BITS (1) 00312 /* RESET_PWRLV field */ 00313 #define RESET_PWRLV (0x00000002u) 00314 #define RESET_PWRLV_MASK (0x00000002u) 00315 #define RESET_PWRLV_BIT (1) 00316 #define RESET_PWRLV_BITS (1) 00317 /* RESET_PWRHV field */ 00318 #define RESET_PWRHV (0x00000001u) 00319 #define RESET_PWRHV_MASK (0x00000001u) 00320 #define RESET_PWRHV_BIT (0) 00321 #define RESET_PWRHV_BITS (1) 00322 00323 #define DBG_MBOX *((volatile int32u *)0x40000030u) 00324 #define DBG_MBOX_REG *((volatile int32u *)0x40000030u) 00325 #define DBG_MBOX_ADDR (0x40000030u) 00326 #define DBG_MBOX_RESET (0x00000000u) 00327 /* DBG_MBOX field */ 00328 #define DBG_MBOX_DBG_MBOX (0x0000FFFFu) 00329 #define DBG_MBOX_DBG_MBOX_MASK (0x0000FFFFu) 00330 #define DBG_MBOX_DBG_MBOX_BIT (0) 00331 #define DBG_MBOX_DBG_MBOX_BITS (16) 00332 00333 #define CPWRUPREQ_STATUS *((volatile int32u *)0x40000034u) 00334 #define CPWRUPREQ_STATUS_REG *((volatile int32u *)0x40000034u) 00335 #define CPWRUPREQ_STATUS_ADDR (0x40000034u) 00336 #define CPWRUPREQ_STATUS_RESET (0x00000000u) 00337 /* CPWRUPREQ field */ 00338 #define CPWRUPREQ_STATUS_CPWRUPREQ (0x00000001u) 00339 #define CPWRUPREQ_STATUS_CPWRUPREQ_MASK (0x00000001u) 00340 #define CPWRUPREQ_STATUS_CPWRUPREQ_BIT (0) 00341 #define CPWRUPREQ_STATUS_CPWRUPREQ_BITS (1) 00342 00343 #define CSYSPWRUPREQ_STATUS *((volatile int32u *)0x40000038u) 00344 #define CSYSPWRUPREQ_STATUS_REG *((volatile int32u *)0x40000038u) 00345 #define CSYSPWRUPREQ_STATUS_ADDR (0x40000038u) 00346 #define CSYSPWRUPREQ_STATUS_RESET (0x00000000u) 00347 /* CSYSPWRUPREQ field */ 00348 #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ (0x00000001u) 00349 #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_MASK (0x00000001u) 00350 #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT (0) 00351 #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS (1) 00352 00353 #define CSYSPWRUPACK_STATUS *((volatile int32u *)0x4000003Cu) 00354 #define CSYSPWRUPACK_STATUS_REG *((volatile int32u *)0x4000003Cu) 00355 #define CSYSPWRUPACK_STATUS_ADDR (0x4000003Cu) 00356 #define CSYSPWRUPACK_STATUS_RESET (0x00000000u) 00357 /* CSYSPWRUPACK field */ 00358 #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK (0x00000001u) 00359 #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_MASK (0x00000001u) 00360 #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT (0) 00361 #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS (1) 00362 00363 #define CSYSPWRUPACK_INHIBIT *((volatile int32u *)0x40000040u) 00364 #define CSYSPWRUPACK_INHIBIT_REG *((volatile int32u *)0x40000040u) 00365 #define CSYSPWRUPACK_INHIBIT_ADDR (0x40000040u) 00366 #define CSYSPWRUPACK_INHIBIT_RESET (0x00000000u) 00367 /* CSYSPWRUPACK_INHIBIT field */ 00368 #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT (0x00000001u) 00369 #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_MASK (0x00000001u) 00370 #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT (0) 00371 #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS (1) 00372 00373 #define OPT_ERR_MAINTAIN_WAKE *((volatile int32u *)0x40000044u) 00374 #define OPT_ERR_MAINTAIN_WAKE_REG *((volatile int32u *)0x40000044u) 00375 #define OPT_ERR_MAINTAIN_WAKE_ADDR (0x40000044u) 00376 #define OPT_ERR_MAINTAIN_WAKE_RESET (0x00000000u) 00377 /* OPT_ERR_MAINTAIN_WAKE field */ 00378 #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE (0x00000001u) 00379 #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_MASK (0x00000001u) 00380 #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BIT (0) 00381 #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BITS (1) 00382 00383 /* BASEBAND block */ 00384 #define DATA_BASEBAND_BASE (0x40001000u) 00385 #define DATA_BASEBAND_END (0x40001114u) 00386 #define DATA_BASEBAND_SIZE (DATA_BASEBAND_END - DATA_BASEBAND_BASE + 1) 00387 00388 #define MOD_CAL_CTRL *((volatile int32u *)0x40001000u) 00389 #define MOD_CAL_CTRL_REG *((volatile int32u *)0x40001000u) 00390 #define MOD_CAL_CTRL_ADDR (0x40001000u) 00391 #define MOD_CAL_CTRL_RESET (0x00000000u) 00392 /* MOD_CAL_GO field */ 00393 #define MOD_CAL_CTRL_MOD_CAL_GO (0x00008000u) 00394 #define MOD_CAL_CTRL_MOD_CAL_GO_MASK (0x00008000u) 00395 #define MOD_CAL_CTRL_MOD_CAL_GO_BIT (15) 00396 #define MOD_CAL_CTRL_MOD_CAL_GO_BITS (1) 00397 /* MOD_CAL_DONE field */ 00398 #define MOD_CAL_CTRL_MOD_CAL_DONE (0x00000010u) 00399 #define MOD_CAL_CTRL_MOD_CAL_DONE_MASK (0x00000010u) 00400 #define MOD_CAL_CTRL_MOD_CAL_DONE_BIT (4) 00401 #define MOD_CAL_CTRL_MOD_CAL_DONE_BITS (1) 00402 /* MOD_CAL_CYCLES field */ 00403 #define MOD_CAL_CTRL_MOD_CAL_CYCLES (0x00000003u) 00404 #define MOD_CAL_CTRL_MOD_CAL_CYCLES_MASK (0x00000003u) 00405 #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT (0) 00406 #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS (2) 00407 00408 #define MOD_CAL_COUNT_H *((volatile int32u *)0x40001004u) 00409 #define MOD_CAL_COUNT_H_REG *((volatile int32u *)0x40001004u) 00410 #define MOD_CAL_COUNT_H_ADDR (0x40001004u) 00411 #define MOD_CAL_COUNT_H_RESET (0x00000000u) 00412 /* MOD_CAL_COUNT_H field */ 00413 #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H (0x000000FFu) 00414 #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_MASK (0x000000FFu) 00415 #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT (0) 00416 #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS (8) 00417 00418 #define MOD_CAL_COUNT_L *((volatile int32u *)0x40001008u) 00419 #define MOD_CAL_COUNT_L_REG *((volatile int32u *)0x40001008u) 00420 #define MOD_CAL_COUNT_L_ADDR (0x40001008u) 00421 #define MOD_CAL_COUNT_L_RESET (0x00000000u) 00422 /* MOD_CAL_COUNT_L field */ 00423 #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L (0x0000FFFFu) 00424 #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_MASK (0x0000FFFFu) 00425 #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT (0) 00426 #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS (16) 00427 00428 #define RSSI_ROLLING *((volatile int32u *)0x4000100Cu) 00429 #define RSSI_ROLLING_REG *((volatile int32u *)0x4000100Cu) 00430 #define RSSI_ROLLING_ADDR (0x4000100Cu) 00431 #define RSSI_ROLLING_RESET (0x00000000u) 00432 /* RSSI_ROLLING field */ 00433 #define RSSI_ROLLING_RSSI_ROLLING (0x00003FFFu) 00434 #define RSSI_ROLLING_RSSI_ROLLING_MASK (0x00003FFFu) 00435 #define RSSI_ROLLING_RSSI_ROLLING_BIT (0) 00436 #define RSSI_ROLLING_RSSI_ROLLING_BITS (14) 00437 00438 #define RSSI_PKT *((volatile int32u *)0x40001010u) 00439 #define RSSI_PKT_REG *((volatile int32u *)0x40001010u) 00440 #define RSSI_PKT_ADDR (0x40001010u) 00441 #define RSSI_PKT_RESET (0x00000000u) 00442 /* RSSI_PKT field */ 00443 #define RSSI_PKT_RSSI_PKT (0x000000FFu) 00444 #define RSSI_PKT_RSSI_PKT_MASK (0x000000FFu) 00445 #define RSSI_PKT_RSSI_PKT_BIT (0) 00446 #define RSSI_PKT_RSSI_PKT_BITS (8) 00447 00448 #define RX_ADC *((volatile int32u *)0x40001014u) 00449 #define RX_ADC_REG *((volatile int32u *)0x40001014u) 00450 #define RX_ADC_ADDR (0x40001014u) 00451 #define RX_ADC_RESET (0x00000024u) 00452 /* RX_ADC field */ 00453 #define RX_ADC_RX_ADC (0x0000007Fu) 00454 #define RX_ADC_RX_ADC_MASK (0x0000007Fu) 00455 #define RX_ADC_RX_ADC_BIT (0) 00456 #define RX_ADC_RX_ADC_BITS (7) 00457 00458 #define DEBUG_BB_MODE *((volatile int32u *)0x40001018u) 00459 #define DEBUG_BB_MODE_REG *((volatile int32u *)0x40001018u) 00460 #define DEBUG_BB_MODE_ADDR (0x40001018u) 00461 #define DEBUG_BB_MODE_RESET (0x00000000u) 00462 /* DEBUG_BB_MODE_EN field */ 00463 #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN (0x00008000u) 00464 #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_MASK (0x00008000u) 00465 #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BIT (15) 00466 #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BITS (1) 00467 /* DEBUG_BB_MODE field */ 00468 #define DEBUG_BB_MODE_DEBUG_BB_MODE (0x00000003u) 00469 #define DEBUG_BB_MODE_DEBUG_BB_MODE_MASK (0x00000003u) 00470 #define DEBUG_BB_MODE_DEBUG_BB_MODE_BIT (0) 00471 #define DEBUG_BB_MODE_DEBUG_BB_MODE_BITS (2) 00472 00473 #define BB_DEBUG *((volatile int32u *)0x4000101Cu) 00474 #define BB_DEBUG_REG *((volatile int32u *)0x4000101Cu) 00475 #define BB_DEBUG_ADDR (0x4000101Cu) 00476 #define BB_DEBUG_RESET (0x00000002u) 00477 /* SYNC_REG_EN field */ 00478 #define BB_DEBUG_SYNC_REG_EN (0x00008000u) 00479 #define BB_DEBUG_SYNC_REG_EN_MASK (0x00008000u) 00480 #define BB_DEBUG_SYNC_REG_EN_BIT (15) 00481 #define BB_DEBUG_SYNC_REG_EN_BITS (1) 00482 /* DEBUG_MUX_ADDR field */ 00483 #define BB_DEBUG_DEBUG_MUX_ADDR (0x000000F0u) 00484 #define BB_DEBUG_DEBUG_MUX_ADDR_MASK (0x000000F0u) 00485 #define BB_DEBUG_DEBUG_MUX_ADDR_BIT (4) 00486 #define BB_DEBUG_DEBUG_MUX_ADDR_BITS (4) 00487 /* BB_DEBUG_SEL field */ 00488 #define BB_DEBUG_BB_DEBUG_SEL (0x00000003u) 00489 #define BB_DEBUG_BB_DEBUG_SEL_MASK (0x00000003u) 00490 #define BB_DEBUG_BB_DEBUG_SEL_BIT (0) 00491 #define BB_DEBUG_BB_DEBUG_SEL_BITS (2) 00492 00493 #define BB_DEBUG_VIEW *((volatile int32u *)0x40001020u) 00494 #define BB_DEBUG_VIEW_REG *((volatile int32u *)0x40001020u) 00495 #define BB_DEBUG_VIEW_ADDR (0x40001020u) 00496 #define BB_DEBUG_VIEW_RESET (0x00000000u) 00497 /* BB_DEBUG_VIEW field */ 00498 #define BB_DEBUG_VIEW_BB_DEBUG_VIEW (0x0000FFFFu) 00499 #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_MASK (0x0000FFFFu) 00500 #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT (0) 00501 #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS (16) 00502 00503 #define IF_FREQ *((volatile int32u *)0x40001024u) 00504 #define IF_FREQ_REG *((volatile int32u *)0x40001024u) 00505 #define IF_FREQ_ADDR (0x40001024u) 00506 #define IF_FREQ_RESET (0x00000155u) 00507 /* TIMING_CORR_EN field */ 00508 #define IF_FREQ_TIMING_CORR_EN (0x00008000u) 00509 #define IF_FREQ_TIMING_CORR_EN_MASK (0x00008000u) 00510 #define IF_FREQ_TIMING_CORR_EN_BIT (15) 00511 #define IF_FREQ_TIMING_CORR_EN_BITS (1) 00512 /* IF_FREQ field */ 00513 #define IF_FREQ_IF_FREQ (0x000001FFu) 00514 #define IF_FREQ_IF_FREQ_MASK (0x000001FFu) 00515 #define IF_FREQ_IF_FREQ_BIT (0) 00516 #define IF_FREQ_IF_FREQ_BITS (9) 00517 00518 #define MOD_EN *((volatile int32u *)0x40001028u) 00519 #define MOD_EN_REG *((volatile int32u *)0x40001028u) 00520 #define MOD_EN_ADDR (0x40001028u) 00521 #define MOD_EN_RESET (0x00000001u) 00522 /* MOD_EN field */ 00523 #define MOD_EN_MOD_EN (0x00000001u) 00524 #define MOD_EN_MOD_EN_MASK (0x00000001u) 00525 #define MOD_EN_MOD_EN_BIT (0) 00526 #define MOD_EN_MOD_EN_BITS (1) 00527 00528 #define PRESCALE_CTRL *((volatile int32u *)0x4000102Cu) 00529 #define PRESCALE_CTRL_REG *((volatile int32u *)0x4000102Cu) 00530 #define PRESCALE_CTRL_ADDR (0x4000102Cu) 00531 #define PRESCALE_CTRL_RESET (0x00000000u) 00532 /* PRESCALE_SET field */ 00533 #define PRESCALE_CTRL_PRESCALE_SET (0x00008000u) 00534 #define PRESCALE_CTRL_PRESCALE_SET_MASK (0x00008000u) 00535 #define PRESCALE_CTRL_PRESCALE_SET_BIT (15) 00536 #define PRESCALE_CTRL_PRESCALE_SET_BITS (1) 00537 /* PRESCALE_VAL field */ 00538 #define PRESCALE_CTRL_PRESCALE_VAL (0x00000007u) 00539 #define PRESCALE_CTRL_PRESCALE_VAL_MASK (0x00000007u) 00540 #define PRESCALE_CTRL_PRESCALE_VAL_BIT (0) 00541 #define PRESCALE_CTRL_PRESCALE_VAL_BITS (3) 00542 00543 #define ADC_BYPASS_EN *((volatile int32u *)0x40001030u) 00544 #define ADC_BYPASS_EN_REG *((volatile int32u *)0x40001030u) 00545 #define ADC_BYPASS_EN_ADDR (0x40001030u) 00546 #define ADC_BYPASS_EN_RESET (0x00000000u) 00547 /* ADC_BYPASS_EN field */ 00548 #define ADC_BYPASS_EN_ADC_BYPASS_EN (0x00000001u) 00549 #define ADC_BYPASS_EN_ADC_BYPASS_EN_MASK (0x00000001u) 00550 #define ADC_BYPASS_EN_ADC_BYPASS_EN_BIT (0) 00551 #define ADC_BYPASS_EN_ADC_BYPASS_EN_BITS (1) 00552 00553 #define FIXED_CODE_EN *((volatile int32u *)0x40001034u) 00554 #define FIXED_CODE_EN_REG *((volatile int32u *)0x40001034u) 00555 #define FIXED_CODE_EN_ADDR (0x40001034u) 00556 #define FIXED_CODE_EN_RESET (0x00000000u) 00557 /* FIXED_CODE_EN field */ 00558 #define FIXED_CODE_EN_FIXED_CODE_EN (0x00000001u) 00559 #define FIXED_CODE_EN_FIXED_CODE_EN_MASK (0x00000001u) 00560 #define FIXED_CODE_EN_FIXED_CODE_EN_BIT (0) 00561 #define FIXED_CODE_EN_FIXED_CODE_EN_BITS (1) 00562 00563 #define FIXED_CODE_H *((volatile int32u *)0x40001038u) 00564 #define FIXED_CODE_H_REG *((volatile int32u *)0x40001038u) 00565 #define FIXED_CODE_H_ADDR (0x40001038u) 00566 #define FIXED_CODE_H_RESET (0x00000000u) 00567 /* FIXED_CODE_H field */ 00568 #define FIXED_CODE_H_FIXED_CODE_H (0x0000FFFFu) 00569 #define FIXED_CODE_H_FIXED_CODE_H_MASK (0x0000FFFFu) 00570 #define FIXED_CODE_H_FIXED_CODE_H_BIT (0) 00571 #define FIXED_CODE_H_FIXED_CODE_H_BITS (16) 00572 00573 #define FIXED_CODE_L *((volatile int32u *)0x4000103Cu) 00574 #define FIXED_CODE_L_REG *((volatile int32u *)0x4000103Cu) 00575 #define FIXED_CODE_L_ADDR (0x4000103Cu) 00576 #define FIXED_CODE_L_RESET (0x00000000u) 00577 /* FIXED_CODE_L field */ 00578 #define FIXED_CODE_L_FIXED_CODE_L (0x0000FFFFu) 00579 #define FIXED_CODE_L_FIXED_CODE_L_MASK (0x0000FFFFu) 00580 #define FIXED_CODE_L_FIXED_CODE_L_BIT (0) 00581 #define FIXED_CODE_L_FIXED_CODE_L_BITS (16) 00582 00583 #define FIXED_CODE_L_SHADOW *((volatile int32u *)0x40001040u) 00584 #define FIXED_CODE_L_SHADOW_REG *((volatile int32u *)0x40001040u) 00585 #define FIXED_CODE_L_SHADOW_ADDR (0x40001040u) 00586 #define FIXED_CODE_L_SHADOW_RESET (0x00000000u) 00587 /* FIXED_CODE_L_SHADOW field */ 00588 #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW (0x0000FFFFu) 00589 #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_MASK (0x0000FFFFu) 00590 #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT (0) 00591 #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS (16) 00592 00593 #define RX_GAIN_CTRL *((volatile int32u *)0x40001044u) 00594 #define RX_GAIN_CTRL_REG *((volatile int32u *)0x40001044u) 00595 #define RX_GAIN_CTRL_ADDR (0x40001044u) 00596 #define RX_GAIN_CTRL_RESET (0x00000000u) 00597 /* RX_GAIN_MUX field */ 00598 #define RX_GAIN_CTRL_RX_GAIN_MUX (0x00008000u) 00599 #define RX_GAIN_CTRL_RX_GAIN_MUX_MASK (0x00008000u) 00600 #define RX_GAIN_CTRL_RX_GAIN_MUX_BIT (15) 00601 #define RX_GAIN_CTRL_RX_GAIN_MUX_BITS (1) 00602 /* RX_RF_GAIN_TEST field */ 00603 #define RX_GAIN_CTRL_RX_RF_GAIN_TEST (0x00000080u) 00604 #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_MASK (0x00000080u) 00605 #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BIT (7) 00606 #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BITS (1) 00607 /* RX_MIXER_GAIN_TEST field */ 00608 #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST (0x00000040u) 00609 #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_MASK (0x00000040u) 00610 #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BIT (6) 00611 #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BITS (1) 00612 /* RX_FILTER_GAIN_TEST field */ 00613 #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST (0x00000030u) 00614 #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_MASK (0x00000030u) 00615 #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BIT (4) 00616 #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BITS (2) 00617 /* RX_IF_GAIN_TEST field */ 00618 #define RX_GAIN_CTRL_RX_IF_GAIN_TEST (0x0000000Fu) 00619 #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_MASK (0x0000000Fu) 00620 #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT (0) 00621 #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS (4) 00622 00623 #define PD_DITHER_EN *((volatile int32u *)0x40001048u) 00624 #define PD_DITHER_EN_REG *((volatile int32u *)0x40001048u) 00625 #define PD_DITHER_EN_ADDR (0x40001048u) 00626 #define PD_DITHER_EN_RESET (0x00000001u) 00627 /* PD_DITHER_EN field */ 00628 #define PD_DITHER_EN_PD_DITHER_EN (0x00000001u) 00629 #define PD_DITHER_EN_PD_DITHER_EN_MASK (0x00000001u) 00630 #define PD_DITHER_EN_PD_DITHER_EN_BIT (0) 00631 #define PD_DITHER_EN_PD_DITHER_EN_BITS (1) 00632 00633 #define RX_ERR_THRESH *((volatile int32u *)0x4000104Cu) 00634 #define RX_ERR_THRESH_REG *((volatile int32u *)0x4000104Cu) 00635 #define RX_ERR_THRESH_ADDR (0x4000104Cu) 00636 #define RX_ERR_THRESH_RESET (0x00004608u) 00637 /* LPF_RX_ERR_COEFF field */ 00638 #define RX_ERR_THRESH_LPF_RX_ERR_COEFF (0x0000E000u) 00639 #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_MASK (0x0000E000u) 00640 #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BIT (13) 00641 #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BITS (3) 00642 /* LPF_RX_ERR_THRESH field */ 00643 #define RX_ERR_THRESH_LPF_RX_ERR_THRESH (0x00001F00u) 00644 #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_MASK (0x00001F00u) 00645 #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BIT (8) 00646 #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BITS (5) 00647 /* RX_ERR_THRESH field */ 00648 #define RX_ERR_THRESH_RX_ERR_THRESH (0x0000001Fu) 00649 #define RX_ERR_THRESH_RX_ERR_THRESH_MASK (0x0000001Fu) 00650 #define RX_ERR_THRESH_RX_ERR_THRESH_BIT (0) 00651 #define RX_ERR_THRESH_RX_ERR_THRESH_BITS (5) 00652 00653 #define CARRIER_THRESH *((volatile int32u *)0x40001050u) 00654 #define CARRIER_THRESH_REG *((volatile int32u *)0x40001050u) 00655 #define CARRIER_THRESH_ADDR (0x40001050u) 00656 #define CARRIER_THRESH_RESET (0x00002332u) 00657 /* CARRIER_SPIKE_THRESH field */ 00658 #define CARRIER_THRESH_CARRIER_SPIKE_THRESH (0x0000FF00u) 00659 #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_MASK (0x0000FF00u) 00660 #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BIT (8) 00661 #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BITS (8) 00662 /* CARRIER_THRESH field */ 00663 #define CARRIER_THRESH_CARRIER_THRESH (0x000000FFu) 00664 #define CARRIER_THRESH_CARRIER_THRESH_MASK (0x000000FFu) 00665 #define CARRIER_THRESH_CARRIER_THRESH_BIT (0) 00666 #define CARRIER_THRESH_CARRIER_THRESH_BITS (8) 00667 00668 #define RSSI_THRESH *((volatile int32u *)0x40001054u) 00669 #define RSSI_THRESH_REG *((volatile int32u *)0x40001054u) 00670 #define RSSI_THRESH_ADDR (0x40001054u) 00671 #define RSSI_THRESH_RESET (0x00000100u) 00672 /* RSSI_THRESH field */ 00673 #define RSSI_THRESH_RSSI_THRESH (0x0000FFFFu) 00674 #define RSSI_THRESH_RSSI_THRESH_MASK (0x0000FFFFu) 00675 #define RSSI_THRESH_RSSI_THRESH_BIT (0) 00676 #define RSSI_THRESH_RSSI_THRESH_BITS (16) 00677 00678 #define SYNTH_START *((volatile int32u *)0x40001058u) 00679 #define SYNTH_START_REG *((volatile int32u *)0x40001058u) 00680 #define SYNTH_START_ADDR (0x40001058u) 00681 #define SYNTH_START_RESET (0x00006464u) 00682 /* SYNTH_WARM_START field */ 00683 #define SYNTH_START_SYNTH_WARM_START (0x0000FF00u) 00684 #define SYNTH_START_SYNTH_WARM_START_MASK (0x0000FF00u) 00685 #define SYNTH_START_SYNTH_WARM_START_BIT (8) 00686 #define SYNTH_START_SYNTH_WARM_START_BITS (8) 00687 /* SYNTH_COLD_START field */ 00688 #define SYNTH_START_SYNTH_COLD_START (0x000000FFu) 00689 #define SYNTH_START_SYNTH_COLD_START_MASK (0x000000FFu) 00690 #define SYNTH_START_SYNTH_COLD_START_BIT (0) 00691 #define SYNTH_START_SYNTH_COLD_START_BITS (8) 00692 00693 #define IN_LOCK_EN *((volatile int32u *)0x4000105Cu) 00694 #define IN_LOCK_EN_REG *((volatile int32u *)0x4000105Cu) 00695 #define IN_LOCK_EN_ADDR (0x4000105Cu) 00696 #define IN_LOCK_EN_RESET (0x00000001u) 00697 /* IN_LOCK_EN field */ 00698 #define IN_LOCK_EN_IN_LOCK_EN (0x00000001u) 00699 #define IN_LOCK_EN_IN_LOCK_EN_MASK (0x00000001u) 00700 #define IN_LOCK_EN_IN_LOCK_EN_BIT (0) 00701 #define IN_LOCK_EN_IN_LOCK_EN_BITS (1) 00702 00703 #define DITHER_AMPLITUDE *((volatile int32u *)0x40001060u) 00704 #define DITHER_AMPLITUDE_REG *((volatile int32u *)0x40001060u) 00705 #define DITHER_AMPLITUDE_ADDR (0x40001060u) 00706 #define DITHER_AMPLITUDE_RESET (0x0000003Fu) 00707 /* DITHER_AMP field */ 00708 #define DITHER_AMPLITUDE_DITHER_AMP (0x0000003Fu) 00709 #define DITHER_AMPLITUDE_DITHER_AMP_MASK (0x0000003Fu) 00710 #define DITHER_AMPLITUDE_DITHER_AMP_BIT (0) 00711 #define DITHER_AMPLITUDE_DITHER_AMP_BITS (6) 00712 00713 #define TX_STEP_TIME *((volatile int32u *)0x40001064u) 00714 #define TX_STEP_TIME_REG *((volatile int32u *)0x40001064u) 00715 #define TX_STEP_TIME_ADDR (0x40001064u) 00716 #define TX_STEP_TIME_RESET (0x00000000u) 00717 /* TX_STEP_TIME field */ 00718 #define TX_STEP_TIME_TX_STEP_TIME (0x000000FFu) 00719 #define TX_STEP_TIME_TX_STEP_TIME_MASK (0x000000FFu) 00720 #define TX_STEP_TIME_TX_STEP_TIME_BIT (0) 00721 #define TX_STEP_TIME_TX_STEP_TIME_BITS (8) 00722 00723 #define GAIN_THRESH_MAX *((volatile int32u *)0x40001068u) 00724 #define GAIN_THRESH_MAX_REG *((volatile int32u *)0x40001068u) 00725 #define GAIN_THRESH_MAX_ADDR (0x40001068u) 00726 #define GAIN_THRESH_MAX_RESET (0x00000060u) 00727 /* GAIN_THRESH_MAX field */ 00728 #define GAIN_THRESH_MAX_GAIN_THRESH_MAX (0x000000FFu) 00729 #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_MASK (0x000000FFu) 00730 #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT (0) 00731 #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS (8) 00732 00733 #define GAIN_THRESH_MID *((volatile int32u *)0x4000106Cu) 00734 #define GAIN_THRESH_MID_REG *((volatile int32u *)0x4000106Cu) 00735 #define GAIN_THRESH_MID_ADDR (0x4000106Cu) 00736 #define GAIN_THRESH_MID_RESET (0x00000030u) 00737 /* GAIN_THRESH_MID field */ 00738 #define GAIN_THRESH_MID_GAIN_THRESH_MID (0x000000FFu) 00739 #define GAIN_THRESH_MID_GAIN_THRESH_MID_MASK (0x000000FFu) 00740 #define GAIN_THRESH_MID_GAIN_THRESH_MID_BIT (0) 00741 #define GAIN_THRESH_MID_GAIN_THRESH_MID_BITS (8) 00742 00743 #define GAIN_THRESH_MIN *((volatile int32u *)0x40001070u) 00744 #define GAIN_THRESH_MIN_REG *((volatile int32u *)0x40001070u) 00745 #define GAIN_THRESH_MIN_ADDR (0x40001070u) 00746 #define GAIN_THRESH_MIN_RESET (0x00000018u) 00747 /* GAIN_THRESH_MIN field */ 00748 #define GAIN_THRESH_MIN_GAIN_THRESH_MIN (0x000000FFu) 00749 #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_MASK (0x000000FFu) 00750 #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT (0) 00751 #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS (8) 00752 00753 #define GAIN_SETTING_0 *((volatile int32u *)0x40001074u) 00754 #define GAIN_SETTING_0_REG *((volatile int32u *)0x40001074u) 00755 #define GAIN_SETTING_0_ADDR (0x40001074u) 00756 #define GAIN_SETTING_0_RESET (0x00000000u) 00757 /* RX_MIXER_GAIN_0 field */ 00758 #define GAIN_SETTING_0_RX_MIXER_GAIN_0 (0x00000040u) 00759 #define GAIN_SETTING_0_RX_MIXER_GAIN_0_MASK (0x00000040u) 00760 #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BIT (6) 00761 #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BITS (1) 00762 /* RX_FILTER_GAIN_0 field */ 00763 #define GAIN_SETTING_0_RX_FILTER_GAIN_0 (0x00000030u) 00764 #define GAIN_SETTING_0_RX_FILTER_GAIN_0_MASK (0x00000030u) 00765 #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BIT (4) 00766 #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BITS (2) 00767 /* RX_IF_GAIN_0 field */ 00768 #define GAIN_SETTING_0_RX_IF_GAIN_0 (0x0000000Fu) 00769 #define GAIN_SETTING_0_RX_IF_GAIN_0_MASK (0x0000000Fu) 00770 #define GAIN_SETTING_0_RX_IF_GAIN_0_BIT (0) 00771 #define GAIN_SETTING_0_RX_IF_GAIN_0_BITS (4) 00772 00773 #define GAIN_SETTING_1 *((volatile int32u *)0x40001078u) 00774 #define GAIN_SETTING_1_REG *((volatile int32u *)0x40001078u) 00775 #define GAIN_SETTING_1_ADDR (0x40001078u) 00776 #define GAIN_SETTING_1_RESET (0x00000010u) 00777 /* RX_MIXER_GAIN_1 field */ 00778 #define GAIN_SETTING_1_RX_MIXER_GAIN_1 (0x00000040u) 00779 #define GAIN_SETTING_1_RX_MIXER_GAIN_1_MASK (0x00000040u) 00780 #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BIT (6) 00781 #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BITS (1) 00782 /* RX_FILTER_GAIN_1 field */ 00783 #define GAIN_SETTING_1_RX_FILTER_GAIN_1 (0x00000030u) 00784 #define GAIN_SETTING_1_RX_FILTER_GAIN_1_MASK (0x00000030u) 00785 #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BIT (4) 00786 #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BITS (2) 00787 /* RX_IF_GAIN_1 field */ 00788 #define GAIN_SETTING_1_RX_IF_GAIN_1 (0x0000000Fu) 00789 #define GAIN_SETTING_1_RX_IF_GAIN_1_MASK (0x0000000Fu) 00790 #define GAIN_SETTING_1_RX_IF_GAIN_1_BIT (0) 00791 #define GAIN_SETTING_1_RX_IF_GAIN_1_BITS (4) 00792 00793 #define GAIN_SETTING_2 *((volatile int32u *)0x4000107Cu) 00794 #define GAIN_SETTING_2_REG *((volatile int32u *)0x4000107Cu) 00795 #define GAIN_SETTING_2_ADDR (0x4000107Cu) 00796 #define GAIN_SETTING_2_RESET (0x00000030u) 00797 /* RX_MIXER_GAIN_2 field */ 00798 #define GAIN_SETTING_2_RX_MIXER_GAIN_2 (0x00000040u) 00799 #define GAIN_SETTING_2_RX_MIXER_GAIN_2_MASK (0x00000040u) 00800 #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BIT (6) 00801 #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BITS (1) 00802 /* RX_FILTER_GAIN_2 field */ 00803 #define GAIN_SETTING_2_RX_FILTER_GAIN_2 (0x00000030u) 00804 #define GAIN_SETTING_2_RX_FILTER_GAIN_2_MASK (0x00000030u) 00805 #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BIT (4) 00806 #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BITS (2) 00807 /* RX_IF_GAIN_2 field */ 00808 #define GAIN_SETTING_2_RX_IF_GAIN_2 (0x0000000Fu) 00809 #define GAIN_SETTING_2_RX_IF_GAIN_2_MASK (0x0000000Fu) 00810 #define GAIN_SETTING_2_RX_IF_GAIN_2_BIT (0) 00811 #define GAIN_SETTING_2_RX_IF_GAIN_2_BITS (4) 00812 00813 #define GAIN_SETTING_3 *((volatile int32u *)0x40001080u) 00814 #define GAIN_SETTING_3_REG *((volatile int32u *)0x40001080u) 00815 #define GAIN_SETTING_3_ADDR (0x40001080u) 00816 #define GAIN_SETTING_3_RESET (0x00000031u) 00817 /* RX_MIXER_GAIN_3 field */ 00818 #define GAIN_SETTING_3_RX_MIXER_GAIN_3 (0x00000040u) 00819 #define GAIN_SETTING_3_RX_MIXER_GAIN_3_MASK (0x00000040u) 00820 #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BIT (6) 00821 #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BITS (1) 00822 /* RX_FILTER_GAIN_3 field */ 00823 #define GAIN_SETTING_3_RX_FILTER_GAIN_3 (0x00000030u) 00824 #define GAIN_SETTING_3_RX_FILTER_GAIN_3_MASK (0x00000030u) 00825 #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BIT (4) 00826 #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BITS (2) 00827 /* RX_IF_GAIN_3 field */ 00828 #define GAIN_SETTING_3_RX_IF_GAIN_3 (0x0000000Fu) 00829 #define GAIN_SETTING_3_RX_IF_GAIN_3_MASK (0x0000000Fu) 00830 #define GAIN_SETTING_3_RX_IF_GAIN_3_BIT (0) 00831 #define GAIN_SETTING_3_RX_IF_GAIN_3_BITS (4) 00832 00833 #define GAIN_SETTING_4 *((volatile int32u *)0x40001084u) 00834 #define GAIN_SETTING_4_REG *((volatile int32u *)0x40001084u) 00835 #define GAIN_SETTING_4_ADDR (0x40001084u) 00836 #define GAIN_SETTING_4_RESET (0x00000032u) 00837 /* RX_MIXER_GAIN_4 field */ 00838 #define GAIN_SETTING_4_RX_MIXER_GAIN_4 (0x00000040u) 00839 #define GAIN_SETTING_4_RX_MIXER_GAIN_4_MASK (0x00000040u) 00840 #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BIT (6) 00841 #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BITS (1) 00842 /* RX_FILTER_GAIN_4 field */ 00843 #define GAIN_SETTING_4_RX_FILTER_GAIN_4 (0x00000030u) 00844 #define GAIN_SETTING_4_RX_FILTER_GAIN_4_MASK (0x00000030u) 00845 #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BIT (4) 00846 #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BITS (2) 00847 /* RX_IF_GAIN_4 field */ 00848 #define GAIN_SETTING_4_RX_IF_GAIN_4 (0x0000000Fu) 00849 #define GAIN_SETTING_4_RX_IF_GAIN_4_MASK (0x0000000Fu) 00850 #define GAIN_SETTING_4_RX_IF_GAIN_4_BIT (0) 00851 #define GAIN_SETTING_4_RX_IF_GAIN_4_BITS (4) 00852 00853 #define GAIN_SETTING_5 *((volatile int32u *)0x40001088u) 00854 #define GAIN_SETTING_5_REG *((volatile int32u *)0x40001088u) 00855 #define GAIN_SETTING_5_ADDR (0x40001088u) 00856 #define GAIN_SETTING_5_RESET (0x00000033u) 00857 /* RX_MIXER_GAIN_5 field */ 00858 #define GAIN_SETTING_5_RX_MIXER_GAIN_5 (0x00000040u) 00859 #define GAIN_SETTING_5_RX_MIXER_GAIN_5_MASK (0x00000040u) 00860 #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BIT (6) 00861 #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BITS (1) 00862 /* RX_FILTER_GAIN_5 field */ 00863 #define GAIN_SETTING_5_RX_FILTER_GAIN_5 (0x00000030u) 00864 #define GAIN_SETTING_5_RX_FILTER_GAIN_5_MASK (0x00000030u) 00865 #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BIT (4) 00866 #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BITS (2) 00867 /* RX_IF_GAIN_5 field */ 00868 #define GAIN_SETTING_5_RX_IF_GAIN_5 (0x0000000Fu) 00869 #define GAIN_SETTING_5_RX_IF_GAIN_5_MASK (0x0000000Fu) 00870 #define GAIN_SETTING_5_RX_IF_GAIN_5_BIT (0) 00871 #define GAIN_SETTING_5_RX_IF_GAIN_5_BITS (4) 00872 00873 #define GAIN_SETTING_6 *((volatile int32u *)0x4000108Cu) 00874 #define GAIN_SETTING_6_REG *((volatile int32u *)0x4000108Cu) 00875 #define GAIN_SETTING_6_ADDR (0x4000108Cu) 00876 #define GAIN_SETTING_6_RESET (0x00000034u) 00877 /* RX_MIXER_GAIN_6 field */ 00878 #define GAIN_SETTING_6_RX_MIXER_GAIN_6 (0x00000040u) 00879 #define GAIN_SETTING_6_RX_MIXER_GAIN_6_MASK (0x00000040u) 00880 #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BIT (6) 00881 #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BITS (1) 00882 /* RX_FILTER_GAIN_6 field */ 00883 #define GAIN_SETTING_6_RX_FILTER_GAIN_6 (0x00000030u) 00884 #define GAIN_SETTING_6_RX_FILTER_GAIN_6_MASK (0x00000030u) 00885 #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BIT (4) 00886 #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BITS (2) 00887 /* RX_IF_GAIN_6 field */ 00888 #define GAIN_SETTING_6_RX_IF_GAIN_6 (0x0000000Fu) 00889 #define GAIN_SETTING_6_RX_IF_GAIN_6_MASK (0x0000000Fu) 00890 #define GAIN_SETTING_6_RX_IF_GAIN_6_BIT (0) 00891 #define GAIN_SETTING_6_RX_IF_GAIN_6_BITS (4) 00892 00893 #define GAIN_SETTING_7 *((volatile int32u *)0x40001090u) 00894 #define GAIN_SETTING_7_REG *((volatile int32u *)0x40001090u) 00895 #define GAIN_SETTING_7_ADDR (0x40001090u) 00896 #define GAIN_SETTING_7_RESET (0x00000035u) 00897 /* RX_MIXER_GAIN_7 field */ 00898 #define GAIN_SETTING_7_RX_MIXER_GAIN_7 (0x00000040u) 00899 #define GAIN_SETTING_7_RX_MIXER_GAIN_7_MASK (0x00000040u) 00900 #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BIT (6) 00901 #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BITS (1) 00902 /* RX_FILTER_GAIN_7 field */ 00903 #define GAIN_SETTING_7_RX_FILTER_GAIN_7 (0x00000030u) 00904 #define GAIN_SETTING_7_RX_FILTER_GAIN_7_MASK (0x00000030u) 00905 #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BIT (4) 00906 #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BITS (2) 00907 /* RX_IF_GAIN_7 field */ 00908 #define GAIN_SETTING_7_RX_IF_GAIN_7 (0x0000000Fu) 00909 #define GAIN_SETTING_7_RX_IF_GAIN_7_MASK (0x0000000Fu) 00910 #define GAIN_SETTING_7_RX_IF_GAIN_7_BIT (0) 00911 #define GAIN_SETTING_7_RX_IF_GAIN_7_BITS (4) 00912 00913 #define GAIN_SETTING_8 *((volatile int32u *)0x40001094u) 00914 #define GAIN_SETTING_8_REG *((volatile int32u *)0x40001094u) 00915 #define GAIN_SETTING_8_ADDR (0x40001094u) 00916 #define GAIN_SETTING_8_RESET (0x00000036u) 00917 /* RX_MIXER_GAIN_8 field */ 00918 #define GAIN_SETTING_8_RX_MIXER_GAIN_8 (0x00000040u) 00919 #define GAIN_SETTING_8_RX_MIXER_GAIN_8_MASK (0x00000040u) 00920 #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BIT (6) 00921 #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BITS (1) 00922 /* RX_FILTER_GAIN_8 field */ 00923 #define GAIN_SETTING_8_RX_FILTER_GAIN_8 (0x00000030u) 00924 #define GAIN_SETTING_8_RX_FILTER_GAIN_8_MASK (0x00000030u) 00925 #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BIT (4) 00926 #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BITS (2) 00927 /* RX_IF_GAIN_8 field */ 00928 #define GAIN_SETTING_8_RX_IF_GAIN_8 (0x0000000Fu) 00929 #define GAIN_SETTING_8_RX_IF_GAIN_8_MASK (0x0000000Fu) 00930 #define GAIN_SETTING_8_RX_IF_GAIN_8_BIT (0) 00931 #define GAIN_SETTING_8_RX_IF_GAIN_8_BITS (4) 00932 00933 #define GAIN_SETTING_9 *((volatile int32u *)0x40001098u) 00934 #define GAIN_SETTING_9_REG *((volatile int32u *)0x40001098u) 00935 #define GAIN_SETTING_9_ADDR (0x40001098u) 00936 #define GAIN_SETTING_9_RESET (0x00000076u) 00937 /* RX_MIXER_GAIN_9 field */ 00938 #define GAIN_SETTING_9_RX_MIXER_GAIN_9 (0x00000040u) 00939 #define GAIN_SETTING_9_RX_MIXER_GAIN_9_MASK (0x00000040u) 00940 #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BIT (6) 00941 #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BITS (1) 00942 /* RX_FILTER_GAIN_9 field */ 00943 #define GAIN_SETTING_9_RX_FILTER_GAIN_9 (0x00000030u) 00944 #define GAIN_SETTING_9_RX_FILTER_GAIN_9_MASK (0x00000030u) 00945 #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BIT (4) 00946 #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BITS (2) 00947 /* RX_IF_GAIN_9 field */ 00948 #define GAIN_SETTING_9_RX_IF_GAIN_9 (0x0000000Fu) 00949 #define GAIN_SETTING_9_RX_IF_GAIN_9_MASK (0x0000000Fu) 00950 #define GAIN_SETTING_9_RX_IF_GAIN_9_BIT (0) 00951 #define GAIN_SETTING_9_RX_IF_GAIN_9_BITS (4) 00952 00953 #define GAIN_SETTING_10 *((volatile int32u *)0x4000109Cu) 00954 #define GAIN_SETTING_10_REG *((volatile int32u *)0x4000109Cu) 00955 #define GAIN_SETTING_10_ADDR (0x4000109Cu) 00956 #define GAIN_SETTING_10_RESET (0x00000077u) 00957 /* RX_MIXER_GAIN_10 field */ 00958 #define GAIN_SETTING_10_RX_MIXER_GAIN_10 (0x00000040u) 00959 #define GAIN_SETTING_10_RX_MIXER_GAIN_10_MASK (0x00000040u) 00960 #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BIT (6) 00961 #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BITS (1) 00962 /* RX_FILTER_GAIN_10 field */ 00963 #define GAIN_SETTING_10_RX_FILTER_GAIN_10 (0x00000030u) 00964 #define GAIN_SETTING_10_RX_FILTER_GAIN_10_MASK (0x00000030u) 00965 #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BIT (4) 00966 #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BITS (2) 00967 /* RX_IF_GAIN_10 field */ 00968 #define GAIN_SETTING_10_RX_IF_GAIN_10 (0x0000000Fu) 00969 #define GAIN_SETTING_10_RX_IF_GAIN_10_MASK (0x0000000Fu) 00970 #define GAIN_SETTING_10_RX_IF_GAIN_10_BIT (0) 00971 #define GAIN_SETTING_10_RX_IF_GAIN_10_BITS (4) 00972 00973 #define GAIN_SETTING_11 *((volatile int32u *)0x400010A0u) 00974 #define GAIN_SETTING_11_REG *((volatile int32u *)0x400010A0u) 00975 #define GAIN_SETTING_11_ADDR (0x400010A0u) 00976 #define GAIN_SETTING_11_RESET (0x00000078u) 00977 /* RX_MIXER_GAIN_11 field */ 00978 #define GAIN_SETTING_11_RX_MIXER_GAIN_11 (0x00000040u) 00979 #define GAIN_SETTING_11_RX_MIXER_GAIN_11_MASK (0x00000040u) 00980 #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BIT (6) 00981 #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BITS (1) 00982 /* RX_FILTER_GAIN_11 field */ 00983 #define GAIN_SETTING_11_RX_FILTER_GAIN_11 (0x00000030u) 00984 #define GAIN_SETTING_11_RX_FILTER_GAIN_11_MASK (0x00000030u) 00985 #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BIT (4) 00986 #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BITS (2) 00987 /* RX_IF_GAIN_11 field */ 00988 #define GAIN_SETTING_11_RX_IF_GAIN_11 (0x0000000Fu) 00989 #define GAIN_SETTING_11_RX_IF_GAIN_11_MASK (0x0000000Fu) 00990 #define GAIN_SETTING_11_RX_IF_GAIN_11_BIT (0) 00991 #define GAIN_SETTING_11_RX_IF_GAIN_11_BITS (4) 00992 00993 #define GAIN_CTRL_MIN_RF *((volatile int32u *)0x400010A4u) 00994 #define GAIN_CTRL_MIN_RF_REG *((volatile int32u *)0x400010A4u) 00995 #define GAIN_CTRL_MIN_RF_ADDR (0x400010A4u) 00996 #define GAIN_CTRL_MIN_RF_RESET (0x000000F0u) 00997 /* GAIN_CTRL_MIN_RF field */ 00998 #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF (0x000001FFu) 00999 #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_MASK (0x000001FFu) 01000 #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT (0) 01001 #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS (9) 01002 01003 #define GAIN_CTRL_MAX_RF *((volatile int32u *)0x400010A8u) 01004 #define GAIN_CTRL_MAX_RF_REG *((volatile int32u *)0x400010A8u) 01005 #define GAIN_CTRL_MAX_RF_ADDR (0x400010A8u) 01006 #define GAIN_CTRL_MAX_RF_RESET (0x000000FCu) 01007 /* GAIN_CTRL_MAX_RF field */ 01008 #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF (0x000001FFu) 01009 #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_MASK (0x000001FFu) 01010 #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT (0) 01011 #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS (9) 01012 01013 #define MIXER_GAIN_STEP *((volatile int32u *)0x400010ACu) 01014 #define MIXER_GAIN_STEP_REG *((volatile int32u *)0x400010ACu) 01015 #define MIXER_GAIN_STEP_ADDR (0x400010ACu) 01016 #define MIXER_GAIN_STEP_RESET (0x0000000Cu) 01017 /* MIXER_GAIN_STEP field */ 01018 #define MIXER_GAIN_STEP_MIXER_GAIN_STEP (0x0000000Fu) 01019 #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_MASK (0x0000000Fu) 01020 #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT (0) 01021 #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS (4) 01022 01023 #define PREAMBLE_EVENT *((volatile int32u *)0x400010B0u) 01024 #define PREAMBLE_EVENT_REG *((volatile int32u *)0x400010B0u) 01025 #define PREAMBLE_EVENT_ADDR (0x400010B0u) 01026 #define PREAMBLE_EVENT_RESET (0x00005877u) 01027 /* PREAMBLE_CONFIRM_THRESH field */ 01028 #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH (0x0000FF00u) 01029 #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_MASK (0x0000FF00u) 01030 #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BIT (8) 01031 #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BITS (8) 01032 /* PREAMBLE_EVENT_THRESH field */ 01033 #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH (0x000000FFu) 01034 #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_MASK (0x000000FFu) 01035 #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT (0) 01036 #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS (8) 01037 01038 #define PREAMBLE_ABORT_THRESH *((volatile int32u *)0x400010B4u) 01039 #define PREAMBLE_ABORT_THRESH_REG *((volatile int32u *)0x400010B4u) 01040 #define PREAMBLE_ABORT_THRESH_ADDR (0x400010B4u) 01041 #define PREAMBLE_ABORT_THRESH_RESET (0x00000071u) 01042 /* PREAMBLE_ABORT_THRESH field */ 01043 #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH (0x000000FFu) 01044 #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_MASK (0x000000FFu) 01045 #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT (0) 01046 #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS (8) 01047 01048 #define PREAMBLE_ACCEPT_WINDOW *((volatile int32u *)0x400010B8u) 01049 #define PREAMBLE_ACCEPT_WINDOW_REG *((volatile int32u *)0x400010B8u) 01050 #define PREAMBLE_ACCEPT_WINDOW_ADDR (0x400010B8u) 01051 #define PREAMBLE_ACCEPT_WINDOW_RESET (0x00000003u) 01052 /* PREAMBLE_ACCEPT_WINDOW field */ 01053 #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW (0x0000007Fu) 01054 #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_MASK (0x0000007Fu) 01055 #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT (0) 01056 #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS (7) 01057 01058 #define CCA_MODE *((volatile int32u *)0x400010BCu) 01059 #define CCA_MODE_REG *((volatile int32u *)0x400010BCu) 01060 #define CCA_MODE_ADDR (0x400010BCu) 01061 #define CCA_MODE_RESET (0x00000000u) 01062 /* CCA_MODE field */ 01063 #define CCA_MODE_CCA_MODE (0x00000003u) 01064 #define CCA_MODE_CCA_MODE_MASK (0x00000003u) 01065 #define CCA_MODE_CCA_MODE_BIT (0) 01066 #define CCA_MODE_CCA_MODE_BITS (2) 01067 01068 #define TX_POWER_MAX *((volatile int32u *)0x400010C0u) 01069 #define TX_POWER_MAX_REG *((volatile int32u *)0x400010C0u) 01070 #define TX_POWER_MAX_ADDR (0x400010C0u) 01071 #define TX_POWER_MAX_RESET (0x00000000u) 01072 /* MANUAL_POWER field */ 01073 #define TX_POWER_MAX_MANUAL_POWER (0x00008000u) 01074 #define TX_POWER_MAX_MANUAL_POWER_MASK (0x00008000u) 01075 #define TX_POWER_MAX_MANUAL_POWER_BIT (15) 01076 #define TX_POWER_MAX_MANUAL_POWER_BITS (1) 01077 /* TX_POWER_MAX field */ 01078 #define TX_POWER_MAX_TX_POWER_MAX (0x0000001Fu) 01079 #define TX_POWER_MAX_TX_POWER_MAX_MASK (0x0000001Fu) 01080 #define TX_POWER_MAX_TX_POWER_MAX_BIT (0) 01081 #define TX_POWER_MAX_TX_POWER_MAX_BITS (5) 01082 01083 #define SYNTH_FREQ_H *((volatile int32u *)0x400010C4u) 01084 #define SYNTH_FREQ_H_REG *((volatile int32u *)0x400010C4u) 01085 #define SYNTH_FREQ_H_ADDR (0x400010C4u) 01086 #define SYNTH_FREQ_H_RESET (0x00000003u) 01087 /* SYNTH_FREQ_H field */ 01088 #define SYNTH_FREQ_H_SYNTH_FREQ_H (0x00000003u) 01089 #define SYNTH_FREQ_H_SYNTH_FREQ_H_MASK (0x00000003u) 01090 #define SYNTH_FREQ_H_SYNTH_FREQ_H_BIT (0) 01091 #define SYNTH_FREQ_H_SYNTH_FREQ_H_BITS (2) 01092 01093 #define SYNTH_FREQ_L *((volatile int32u *)0x400010C8u) 01094 #define SYNTH_FREQ_L_REG *((volatile int32u *)0x400010C8u) 01095 #define SYNTH_FREQ_L_ADDR (0x400010C8u) 01096 #define SYNTH_FREQ_L_RESET (0x00003800u) 01097 /* SYNTH_FREQ_L field */ 01098 #define SYNTH_FREQ_L_SYNTH_FREQ_L (0x0000FFFFu) 01099 #define SYNTH_FREQ_L_SYNTH_FREQ_L_MASK (0x0000FFFFu) 01100 #define SYNTH_FREQ_L_SYNTH_FREQ_L_BIT (0) 01101 #define SYNTH_FREQ_L_SYNTH_FREQ_L_BITS (16) 01102 01103 #define RSSI_INST *((volatile int32u *)0x400010CCu) 01104 #define RSSI_INST_REG *((volatile int32u *)0x400010CCu) 01105 #define RSSI_INST_ADDR (0x400010CCu) 01106 #define RSSI_INST_RESET (0x00000000u) 01107 /* NEW_RSSI_INST field */ 01108 #define RSSI_INST_NEW_RSSI_INST (0x00000200u) 01109 #define RSSI_INST_NEW_RSSI_INST_MASK (0x00000200u) 01110 #define RSSI_INST_NEW_RSSI_INST_BIT (9) 01111 #define RSSI_INST_NEW_RSSI_INST_BITS (1) 01112 /* RSSI_INST field */ 01113 #define RSSI_INST_RSSI_INST (0x000001FFu) 01114 #define RSSI_INST_RSSI_INST_MASK (0x000001FFu) 01115 #define RSSI_INST_RSSI_INST_BIT (0) 01116 #define RSSI_INST_RSSI_INST_BITS (9) 01117 01118 #define FREQ_MEAS_CTRL1 *((volatile int32u *)0x400010D0u) 01119 #define FREQ_MEAS_CTRL1_REG *((volatile int32u *)0x400010D0u) 01120 #define FREQ_MEAS_CTRL1_ADDR (0x400010D0u) 01121 #define FREQ_MEAS_CTRL1_RESET (0x00000160u) 01122 /* AUTO_TUNE_EN field */ 01123 #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN (0x00008000u) 01124 #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_MASK (0x00008000u) 01125 #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BIT (15) 01126 #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BITS (1) 01127 /* FREQ_MEAS_EN field */ 01128 #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN (0x00004000u) 01129 #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_MASK (0x00004000u) 01130 #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BIT (14) 01131 #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BITS (1) 01132 /* OPEN_LOOP_MANUAL field */ 01133 #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL (0x00002000u) 01134 #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_MASK (0x00002000u) 01135 #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BIT (13) 01136 #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BITS (1) 01137 /* OPEN_LOOP field */ 01138 #define FREQ_MEAS_CTRL1_OPEN_LOOP (0x00001000u) 01139 #define FREQ_MEAS_CTRL1_OPEN_LOOP_MASK (0x00001000u) 01140 #define FREQ_MEAS_CTRL1_OPEN_LOOP_BIT (12) 01141 #define FREQ_MEAS_CTRL1_OPEN_LOOP_BITS (1) 01142 /* DELAY_FIRST_MEAS field */ 01143 #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS (0x00000400u) 01144 #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_MASK (0x00000400u) 01145 #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BIT (10) 01146 #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BITS (1) 01147 /* DELAY_ALL_MEAS field */ 01148 #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS (0x00000200u) 01149 #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_MASK (0x00000200u) 01150 #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BIT (9) 01151 #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BITS (1) 01152 /* BIN_SEARCH_MSB field */ 01153 #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB (0x000001C0u) 01154 #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_MASK (0x000001C0u) 01155 #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BIT (6) 01156 #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BITS (3) 01157 /* TUNE_VCO_INIT field */ 01158 #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT (0x0000003Fu) 01159 #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_MASK (0x0000003Fu) 01160 #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT (0) 01161 #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS (6) 01162 01163 #define FREQ_MEAS_CTRL2 *((volatile int32u *)0x400010D4u) 01164 #define FREQ_MEAS_CTRL2_REG *((volatile int32u *)0x400010D4u) 01165 #define FREQ_MEAS_CTRL2_ADDR (0x400010D4u) 01166 #define FREQ_MEAS_CTRL2_RESET (0x0000201Eu) 01167 /* FREQ_MEAS_TIMER field */ 01168 #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER (0x0000FF00u) 01169 #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_MASK (0x0000FF00u) 01170 #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BIT (8) 01171 #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BITS (8) 01172 /* TARGET_PERIOD field */ 01173 #define FREQ_MEAS_CTRL2_TARGET_PERIOD (0x000000FFu) 01174 #define FREQ_MEAS_CTRL2_TARGET_PERIOD_MASK (0x000000FFu) 01175 #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT (0) 01176 #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS (8) 01177 01178 #define FREQ_MEAS_SHIFT *((volatile int32u *)0x400010D8u) 01179 #define FREQ_MEAS_SHIFT_REG *((volatile int32u *)0x400010D8u) 01180 #define FREQ_MEAS_SHIFT_ADDR (0x400010D8u) 01181 #define FREQ_MEAS_SHIFT_RESET (0x00000035u) 01182 /* FREQ_MEAS_SHIFT field */ 01183 #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT (0x000000FFu) 01184 #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_MASK (0x000000FFu) 01185 #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT (0) 01186 #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS (8) 01187 01188 #define FREQ_MEAS_STATUS1 *((volatile int32u *)0x400010DCu) 01189 #define FREQ_MEAS_STATUS1_REG *((volatile int32u *)0x400010DCu) 01190 #define FREQ_MEAS_STATUS1_ADDR (0x400010DCu) 01191 #define FREQ_MEAS_STATUS1_RESET (0x00000000u) 01192 /* INVALID_EDGE field */ 01193 #define FREQ_MEAS_STATUS1_INVALID_EDGE (0x00008000u) 01194 #define FREQ_MEAS_STATUS1_INVALID_EDGE_MASK (0x00008000u) 01195 #define FREQ_MEAS_STATUS1_INVALID_EDGE_BIT (15) 01196 #define FREQ_MEAS_STATUS1_INVALID_EDGE_BITS (1) 01197 /* SIGN_FOUND field */ 01198 #define FREQ_MEAS_STATUS1_SIGN_FOUND (0x00004000u) 01199 #define FREQ_MEAS_STATUS1_SIGN_FOUND_MASK (0x00004000u) 01200 #define FREQ_MEAS_STATUS1_SIGN_FOUND_BIT (14) 01201 #define FREQ_MEAS_STATUS1_SIGN_FOUND_BITS (1) 01202 /* FREQ_SIGN field */ 01203 #define FREQ_MEAS_STATUS1_FREQ_SIGN (0x00002000u) 01204 #define FREQ_MEAS_STATUS1_FREQ_SIGN_MASK (0x00002000u) 01205 #define FREQ_MEAS_STATUS1_FREQ_SIGN_BIT (13) 01206 #define FREQ_MEAS_STATUS1_FREQ_SIGN_BITS (1) 01207 /* PERIOD_FOUND field */ 01208 #define FREQ_MEAS_STATUS1_PERIOD_FOUND (0x00001000u) 01209 #define FREQ_MEAS_STATUS1_PERIOD_FOUND_MASK (0x00001000u) 01210 #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BIT (12) 01211 #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BITS (1) 01212 /* NEAREST_DIFF field */ 01213 #define FREQ_MEAS_STATUS1_NEAREST_DIFF (0x000003FFu) 01214 #define FREQ_MEAS_STATUS1_NEAREST_DIFF_MASK (0x000003FFu) 01215 #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT (0) 01216 #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS (10) 01217 01218 #define FREQ_MEAS_STATUS2 *((volatile int32u *)0x400010E0u) 01219 #define FREQ_MEAS_STATUS2_REG *((volatile int32u *)0x400010E0u) 01220 #define FREQ_MEAS_STATUS2_ADDR (0x400010E0u) 01221 #define FREQ_MEAS_STATUS2_RESET (0x00000000u) 01222 /* BEAT_TIMER field */ 01223 #define FREQ_MEAS_STATUS2_BEAT_TIMER (0x0000FFC0u) 01224 #define FREQ_MEAS_STATUS2_BEAT_TIMER_MASK (0x0000FFC0u) 01225 #define FREQ_MEAS_STATUS2_BEAT_TIMER_BIT (6) 01226 #define FREQ_MEAS_STATUS2_BEAT_TIMER_BITS (10) 01227 /* BEATS field */ 01228 #define FREQ_MEAS_STATUS2_BEATS (0x0000003Fu) 01229 #define FREQ_MEAS_STATUS2_BEATS_MASK (0x0000003Fu) 01230 #define FREQ_MEAS_STATUS2_BEATS_BIT (0) 01231 #define FREQ_MEAS_STATUS2_BEATS_BITS (6) 01232 01233 #define FREQ_MEAS_STATUS3 *((volatile int32u *)0x400010E4u) 01234 #define FREQ_MEAS_STATUS3_REG *((volatile int32u *)0x400010E4u) 01235 #define FREQ_MEAS_STATUS3_ADDR (0x400010E4u) 01236 #define FREQ_MEAS_STATUS3_RESET (0x00000020u) 01237 /* TUNE_VCO field */ 01238 #define FREQ_MEAS_STATUS3_TUNE_VCO (0x0000003Fu) 01239 #define FREQ_MEAS_STATUS3_TUNE_VCO_MASK (0x0000003Fu) 01240 #define FREQ_MEAS_STATUS3_TUNE_VCO_BIT (0) 01241 #define FREQ_MEAS_STATUS3_TUNE_VCO_BITS (6) 01242 01243 #define SCR_CTRL *((volatile int32u *)0x400010E8u) 01244 #define SCR_CTRL_REG *((volatile int32u *)0x400010E8u) 01245 #define SCR_CTRL_ADDR (0x400010E8u) 01246 #define SCR_CTRL_RESET (0x00000004u) 01247 /* SCR_RESET field */ 01248 #define SCR_CTRL_SCR_RESET (0x00000004u) 01249 #define SCR_CTRL_SCR_RESET_MASK (0x00000004u) 01250 #define SCR_CTRL_SCR_RESET_BIT (2) 01251 #define SCR_CTRL_SCR_RESET_BITS (1) 01252 /* SCR_WRITE field */ 01253 #define SCR_CTRL_SCR_WRITE (0x00000002u) 01254 #define SCR_CTRL_SCR_WRITE_MASK (0x00000002u) 01255 #define SCR_CTRL_SCR_WRITE_BIT (1) 01256 #define SCR_CTRL_SCR_WRITE_BITS (1) 01257 /* SCR_READ field */ 01258 #define SCR_CTRL_SCR_READ (0x00000001u) 01259 #define SCR_CTRL_SCR_READ_MASK (0x00000001u) 01260 #define SCR_CTRL_SCR_READ_BIT (0) 01261 #define SCR_CTRL_SCR_READ_BITS (1) 01262 01263 #define SCR_BUSY *((volatile int32u *)0x400010ECu) 01264 #define SCR_BUSY_REG *((volatile int32u *)0x400010ECu) 01265 #define SCR_BUSY_ADDR (0x400010ECu) 01266 #define SCR_BUSY_RESET (0x00000000u) 01267 /* SCR_BUSY field */ 01268 #define SCR_BUSY_SCR_BUSY (0x00000001u) 01269 #define SCR_BUSY_SCR_BUSY_MASK (0x00000001u) 01270 #define SCR_BUSY_SCR_BUSY_BIT (0) 01271 #define SCR_BUSY_SCR_BUSY_BITS (1) 01272 01273 #define SCR_ADDR *((volatile int32u *)0x400010F0u) 01274 #define SCR_ADDR_REG *((volatile int32u *)0x400010F0u) 01275 #define SCR_ADDR_ADDR (0x400010F0u) 01276 #define SCR_ADDR_RESET (0x00000000u) 01277 /* SCR_ADDR field */ 01278 #define SCR_ADDR_SCR_ADDR (0x000000FFu) 01279 #define SCR_ADDR_SCR_ADDR_MASK (0x000000FFu) 01280 #define SCR_ADDR_SCR_ADDR_BIT (0) 01281 #define SCR_ADDR_SCR_ADDR_BITS (8) 01282 01283 #define SCR_WRITE *((volatile int32u *)0x400010F4u) 01284 #define SCR_WRITE_REG *((volatile int32u *)0x400010F4u) 01285 #define SCR_WRITE_ADDR (0x400010F4u) 01286 #define SCR_WRITE_RESET (0x00000000u) 01287 /* SCR_WRITE field */ 01288 #define SCR_WRITE_SCR_WRITE (0x0000FFFFu) 01289 #define SCR_WRITE_SCR_WRITE_MASK (0x0000FFFFu) 01290 #define SCR_WRITE_SCR_WRITE_BIT (0) 01291 #define SCR_WRITE_SCR_WRITE_BITS (16) 01292 01293 #define SCR_READ *((volatile int32u *)0x400010F8u) 01294 #define SCR_READ_REG *((volatile int32u *)0x400010F8u) 01295 #define SCR_READ_ADDR (0x400010F8u) 01296 #define SCR_READ_RESET (0x00000000u) 01297 /* SCR_READ field */ 01298 #define SCR_READ_SCR_READ (0x0000FFFFu) 01299 #define SCR_READ_SCR_READ_MASK (0x0000FFFFu) 01300 #define SCR_READ_SCR_READ_BIT (0) 01301 #define SCR_READ_SCR_READ_BITS (16) 01302 01303 #define SYNTH_LOCK *((volatile int32u *)0x400010FCu) 01304 #define SYNTH_LOCK_REG *((volatile int32u *)0x400010FCu) 01305 #define SYNTH_LOCK_ADDR (0x400010FCu) 01306 #define SYNTH_LOCK_RESET (0x00000000u) 01307 /* IN_LOCK field */ 01308 #define SYNTH_LOCK_IN_LOCK (0x00000001u) 01309 #define SYNTH_LOCK_IN_LOCK_MASK (0x00000001u) 01310 #define SYNTH_LOCK_IN_LOCK_BIT (0) 01311 #define SYNTH_LOCK_IN_LOCK_BITS (1) 01312 01313 #define AN_CAL_STATUS *((volatile int32u *)0x40001100u) 01314 #define AN_CAL_STATUS_REG *((volatile int32u *)0x40001100u) 01315 #define AN_CAL_STATUS_ADDR (0x40001100u) 01316 #define AN_CAL_STATUS_RESET (0x00000000u) 01317 /* VCO_CTRL field */ 01318 #define AN_CAL_STATUS_VCO_CTRL (0x0000000Cu) 01319 #define AN_CAL_STATUS_VCO_CTRL_MASK (0x0000000Cu) 01320 #define AN_CAL_STATUS_VCO_CTRL_BIT (2) 01321 #define AN_CAL_STATUS_VCO_CTRL_BITS (2) 01322 01323 #define BIAS_CAL_STATUS *((volatile int32u *)0x40001104u) 01324 #define BIAS_CAL_STATUS_REG *((volatile int32u *)0x40001104u) 01325 #define BIAS_CAL_STATUS_ADDR (0x40001104u) 01326 #define BIAS_CAL_STATUS_RESET (0x00000000u) 01327 /* VCOMP field */ 01328 #define BIAS_CAL_STATUS_VCOMP (0x00000002u) 01329 #define BIAS_CAL_STATUS_VCOMP_MASK (0x00000002u) 01330 #define BIAS_CAL_STATUS_VCOMP_BIT (1) 01331 #define BIAS_CAL_STATUS_VCOMP_BITS (1) 01332 /* ICOMP field */ 01333 #define BIAS_CAL_STATUS_ICOMP (0x00000001u) 01334 #define BIAS_CAL_STATUS_ICOMP_MASK (0x00000001u) 01335 #define BIAS_CAL_STATUS_ICOMP_BIT (0) 01336 #define BIAS_CAL_STATUS_ICOMP_BITS (1) 01337 01338 #define ATEST_SEL *((volatile int32u *)0x40001108u) 01339 #define ATEST_SEL_REG *((volatile int32u *)0x40001108u) 01340 #define ATEST_SEL_ADDR (0x40001108u) 01341 #define ATEST_SEL_RESET (0x00000000u) 01342 /* ATEST_CTRL field */ 01343 #define ATEST_SEL_ATEST_CTRL (0x0000FF00u) 01344 #define ATEST_SEL_ATEST_CTRL_MASK (0x0000FF00u) 01345 #define ATEST_SEL_ATEST_CTRL_BIT (8) 01346 #define ATEST_SEL_ATEST_CTRL_BITS (8) 01347 /* ATEST_SEL field */ 01348 #define ATEST_SEL_ATEST_SEL (0x0000001Fu) 01349 #define ATEST_SEL_ATEST_SEL_MASK (0x0000001Fu) 01350 #define ATEST_SEL_ATEST_SEL_BIT (0) 01351 #define ATEST_SEL_ATEST_SEL_BITS (5) 01352 01353 #define AN_EN_TEST *((volatile int32u *)0x4000110Cu) 01354 #define AN_EN_TEST_REG *((volatile int32u *)0x4000110Cu) 01355 #define AN_EN_TEST_ADDR (0x4000110Cu) 01356 #define AN_EN_TEST_RESET (0x00000000u) 01357 /* AN_TEST_MODE field */ 01358 #define AN_EN_TEST_AN_TEST_MODE (0x00008000u) 01359 #define AN_EN_TEST_AN_TEST_MODE_MASK (0x00008000u) 01360 #define AN_EN_TEST_AN_TEST_MODE_BIT (15) 01361 #define AN_EN_TEST_AN_TEST_MODE_BITS (1) 01362 /* PFD_EN field */ 01363 #define AN_EN_TEST_PFD_EN (0x00004000u) 01364 #define AN_EN_TEST_PFD_EN_MASK (0x00004000u) 01365 #define AN_EN_TEST_PFD_EN_BIT (14) 01366 #define AN_EN_TEST_PFD_EN_BITS (1) 01367 /* ADC_EN field */ 01368 #define AN_EN_TEST_ADC_EN (0x00002000u) 01369 #define AN_EN_TEST_ADC_EN_MASK (0x00002000u) 01370 #define AN_EN_TEST_ADC_EN_BIT (13) 01371 #define AN_EN_TEST_ADC_EN_BITS (1) 01372 /* UNUSED field */ 01373 #define AN_EN_TEST_UNUSED (0x00001000u) 01374 #define AN_EN_TEST_UNUSED_MASK (0x00001000u) 01375 #define AN_EN_TEST_UNUSED_BIT (12) 01376 #define AN_EN_TEST_UNUSED_BITS (1) 01377 /* PRE_FILT_EN field */ 01378 #define AN_EN_TEST_PRE_FILT_EN (0x00000800u) 01379 #define AN_EN_TEST_PRE_FILT_EN_MASK (0x00000800u) 01380 #define AN_EN_TEST_PRE_FILT_EN_BIT (11) 01381 #define AN_EN_TEST_PRE_FILT_EN_BITS (1) 01382 /* IF_AMP_EN field */ 01383 #define AN_EN_TEST_IF_AMP_EN (0x00000400u) 01384 #define AN_EN_TEST_IF_AMP_EN_MASK (0x00000400u) 01385 #define AN_EN_TEST_IF_AMP_EN_BIT (10) 01386 #define AN_EN_TEST_IF_AMP_EN_BITS (1) 01387 /* LNA_EN field */ 01388 #define AN_EN_TEST_LNA_EN (0x00000200u) 01389 #define AN_EN_TEST_LNA_EN_MASK (0x00000200u) 01390 #define AN_EN_TEST_LNA_EN_BIT (9) 01391 #define AN_EN_TEST_LNA_EN_BITS (1) 01392 /* MIXER_EN field */ 01393 #define AN_EN_TEST_MIXER_EN (0x00000100u) 01394 #define AN_EN_TEST_MIXER_EN_MASK (0x00000100u) 01395 #define AN_EN_TEST_MIXER_EN_BIT (8) 01396 #define AN_EN_TEST_MIXER_EN_BITS (1) 01397 /* CH_FILT_EN field */ 01398 #define AN_EN_TEST_CH_FILT_EN (0x00000080u) 01399 #define AN_EN_TEST_CH_FILT_EN_MASK (0x00000080u) 01400 #define AN_EN_TEST_CH_FILT_EN_BIT (7) 01401 #define AN_EN_TEST_CH_FILT_EN_BITS (1) 01402 /* MOD_DAC_EN field */ 01403 #define AN_EN_TEST_MOD_DAC_EN (0x00000040u) 01404 #define AN_EN_TEST_MOD_DAC_EN_MASK (0x00000040u) 01405 #define AN_EN_TEST_MOD_DAC_EN_BIT (6) 01406 #define AN_EN_TEST_MOD_DAC_EN_BITS (1) 01407 /* PA_EN field */ 01408 #define AN_EN_TEST_PA_EN (0x00000010u) 01409 #define AN_EN_TEST_PA_EN_MASK (0x00000010u) 01410 #define AN_EN_TEST_PA_EN_BIT (4) 01411 #define AN_EN_TEST_PA_EN_BITS (1) 01412 /* PRESCALER_EN field */ 01413 #define AN_EN_TEST_PRESCALER_EN (0x00000008u) 01414 #define AN_EN_TEST_PRESCALER_EN_MASK (0x00000008u) 01415 #define AN_EN_TEST_PRESCALER_EN_BIT (3) 01416 #define AN_EN_TEST_PRESCALER_EN_BITS (1) 01417 /* VCO_EN field */ 01418 #define AN_EN_TEST_VCO_EN (0x00000004u) 01419 #define AN_EN_TEST_VCO_EN_MASK (0x00000004u) 01420 #define AN_EN_TEST_VCO_EN_BIT (2) 01421 #define AN_EN_TEST_VCO_EN_BITS (1) 01422 /* BIAS_EN field */ 01423 #define AN_EN_TEST_BIAS_EN (0x00000001u) 01424 #define AN_EN_TEST_BIAS_EN_MASK (0x00000001u) 01425 #define AN_EN_TEST_BIAS_EN_BIT (0) 01426 #define AN_EN_TEST_BIAS_EN_BITS (1) 01427 01428 #define TUNE_FILTER_CTRL *((volatile int32u *)0x40001110u) 01429 #define TUNE_FILTER_CTRL_REG *((volatile int32u *)0x40001110u) 01430 #define TUNE_FILTER_CTRL_ADDR (0x40001110u) 01431 #define TUNE_FILTER_CTRL_RESET (0x00000000u) 01432 /* TUNE_FILTER_EN field */ 01433 #define TUNE_FILTER_CTRL_TUNE_FILTER_EN (0x00000002u) 01434 #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_MASK (0x00000002u) 01435 #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BIT (1) 01436 #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BITS (1) 01437 /* TUNE_FILTER_RESET field */ 01438 #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET (0x00000001u) 01439 #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_MASK (0x00000001u) 01440 #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT (0) 01441 #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS (1) 01442 01443 #define NOISE_EN *((volatile int32u *)0x40001114u) 01444 #define NOISE_EN_REG *((volatile int32u *)0x40001114u) 01445 #define NOISE_EN_ADDR (0x40001114u) 01446 #define NOISE_EN_RESET (0x00000000u) 01447 /* NOISE_EN field */ 01448 #define NOISE_EN_NOISE_EN (0x00000001u) 01449 #define NOISE_EN_NOISE_EN_MASK (0x00000001u) 01450 #define NOISE_EN_NOISE_EN_BIT (0) 01451 #define NOISE_EN_NOISE_EN_BITS (1) 01452 01453 /* MAC block */ 01454 #define DATA_MAC_BASE (0x40002000u) 01455 #define DATA_MAC_END (0x400020C8u) 01456 #define DATA_MAC_SIZE (DATA_MAC_END - DATA_MAC_BASE + 1) 01457 01458 #define MAC_RX_ST_ADDR_A *((volatile int32u *)0x40002000u) 01459 #define MAC_RX_ST_ADDR_A_REG *((volatile int32u *)0x40002000u) 01460 #define MAC_RX_ST_ADDR_A_ADDR (0x40002000u) 01461 #define MAC_RX_ST_ADDR_A_RESET (0x20000000u) 01462 /* MAC_RAM_OFFS field */ 01463 #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) 01464 #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01465 #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) 01466 #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) 01467 /* MAC_RX_ST_ADDR_A field */ 01468 #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A (0x00001FFEu) 01469 #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_MASK (0x00001FFEu) 01470 #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT (1) 01471 #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS (12) 01472 01473 #define MAC_RX_END_ADDR_A *((volatile int32u *)0x40002004u) 01474 #define MAC_RX_END_ADDR_A_REG *((volatile int32u *)0x40002004u) 01475 #define MAC_RX_END_ADDR_A_ADDR (0x40002004u) 01476 #define MAC_RX_END_ADDR_A_RESET (0x20000088u) 01477 /* MAC_RAM_OFFS field */ 01478 #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) 01479 #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01480 #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) 01481 #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) 01482 /* MAC_RX_END_ADDR_A field */ 01483 #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A (0x00001FFEu) 01484 #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_MASK (0x00001FFEu) 01485 #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT (1) 01486 #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS (12) 01487 01488 #define MAC_RX_ST_ADDR_B *((volatile int32u *)0x40002008u) 01489 #define MAC_RX_ST_ADDR_B_REG *((volatile int32u *)0x40002008u) 01490 #define MAC_RX_ST_ADDR_B_ADDR (0x40002008u) 01491 #define MAC_RX_ST_ADDR_B_RESET (0x20000000u) 01492 /* MAC_RAM_OFFS field */ 01493 #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) 01494 #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01495 #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) 01496 #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) 01497 /* MAC_RX_ST_ADDR_B field */ 01498 #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B (0x00001FFEu) 01499 #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_MASK (0x00001FFEu) 01500 #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT (1) 01501 #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS (12) 01502 01503 #define MAC_RX_END_ADDR_B *((volatile int32u *)0x4000200Cu) 01504 #define MAC_RX_END_ADDR_B_REG *((volatile int32u *)0x4000200Cu) 01505 #define MAC_RX_END_ADDR_B_ADDR (0x4000200Cu) 01506 #define MAC_RX_END_ADDR_B_RESET (0x20000088u) 01507 /* MAC_RAM_OFFS field */ 01508 #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) 01509 #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01510 #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) 01511 #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) 01512 /* MAC_RX_END_ADDR_B field */ 01513 #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B (0x00001FFEu) 01514 #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_MASK (0x00001FFEu) 01515 #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT (1) 01516 #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS (12) 01517 01518 #define MAC_TX_ST_ADDR_A *((volatile int32u *)0x40002010u) 01519 #define MAC_TX_ST_ADDR_A_REG *((volatile int32u *)0x40002010u) 01520 #define MAC_TX_ST_ADDR_A_ADDR (0x40002010u) 01521 #define MAC_TX_ST_ADDR_A_RESET (0x20000000u) 01522 /* MAC_RAM_OFFS field */ 01523 #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) 01524 #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01525 #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) 01526 #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) 01527 /* MAC_TX_ST_ADDR_A field */ 01528 #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A (0x00001FFEu) 01529 #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_MASK (0x00001FFEu) 01530 #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT (1) 01531 #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS (12) 01532 01533 #define MAC_TX_END_ADDR_A *((volatile int32u *)0x40002014u) 01534 #define MAC_TX_END_ADDR_A_REG *((volatile int32u *)0x40002014u) 01535 #define MAC_TX_END_ADDR_A_ADDR (0x40002014u) 01536 #define MAC_TX_END_ADDR_A_RESET (0x20000000u) 01537 /* MAC_RAM_OFFS field */ 01538 #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) 01539 #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01540 #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) 01541 #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) 01542 /* MAC_TX_END_ADDR_A field */ 01543 #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A (0x00001FFEu) 01544 #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_MASK (0x00001FFEu) 01545 #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT (1) 01546 #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS (12) 01547 01548 #define MAC_TX_ST_ADDR_B *((volatile int32u *)0x40002018u) 01549 #define MAC_TX_ST_ADDR_B_REG *((volatile int32u *)0x40002018u) 01550 #define MAC_TX_ST_ADDR_B_ADDR (0x40002018u) 01551 #define MAC_TX_ST_ADDR_B_RESET (0x20000000u) 01552 /* MAC_RAM_OFFS field */ 01553 #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) 01554 #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01555 #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) 01556 #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) 01557 /* MAC_TX_ST_ADDR_B field */ 01558 #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B (0x00001FFEu) 01559 #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_MASK (0x00001FFEu) 01560 #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT (1) 01561 #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS (12) 01562 01563 #define MAC_TX_END_ADDR_B *((volatile int32u *)0x4000201Cu) 01564 #define MAC_TX_END_ADDR_B_REG *((volatile int32u *)0x4000201Cu) 01565 #define MAC_TX_END_ADDR_B_ADDR (0x4000201Cu) 01566 #define MAC_TX_END_ADDR_B_RESET (0x20000000u) 01567 /* MAC_RAM_OFFS field */ 01568 #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) 01569 #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) 01570 #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) 01571 #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) 01572 /* MAC_TX_END_ADDR_B field */ 01573 #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B (0x00001FFEu) 01574 #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_MASK (0x00001FFEu) 01575 #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT (1) 01576 #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS (12) 01577 01578 #define RX_A_COUNT *((volatile int32u *)0x40002020u) 01579 #define RX_A_COUNT_REG *((volatile int32u *)0x40002020u) 01580 #define RX_A_COUNT_ADDR (0x40002020u) 01581 #define RX_A_COUNT_RESET (0x00000000u) 01582 /* RX_A_COUNT field */ 01583 #define RX_A_COUNT_RX_A_COUNT (0x000007FFu) 01584 #define RX_A_COUNT_RX_A_COUNT_MASK (0x000007FFu) 01585 #define RX_A_COUNT_RX_A_COUNT_BIT (0) 01586 #define RX_A_COUNT_RX_A_COUNT_BITS (11) 01587 01588 #define RX_B_COUNT *((volatile int32u *)0x40002024u) 01589 #define RX_B_COUNT_REG *((volatile int32u *)0x40002024u) 01590 #define RX_B_COUNT_ADDR (0x40002024u) 01591 #define RX_B_COUNT_RESET (0x00000000u) 01592 /* RX_B_COUNT field */ 01593 #define RX_B_COUNT_RX_B_COUNT (0x000007FFu) 01594 #define RX_B_COUNT_RX_B_COUNT_MASK (0x000007FFu) 01595 #define RX_B_COUNT_RX_B_COUNT_BIT (0) 01596 #define RX_B_COUNT_RX_B_COUNT_BITS (11) 01597 01598 #define TX_COUNT *((volatile int32u *)0x40002028u) 01599 #define TX_COUNT_REG *((volatile int32u *)0x40002028u) 01600 #define TX_COUNT_ADDR (0x40002028u) 01601 #define TX_COUNT_RESET (0x00000000u) 01602 /* TX_COUNT field */ 01603 #define TX_COUNT_TX_COUNT (0x000007FFu) 01604 #define TX_COUNT_TX_COUNT_MASK (0x000007FFu) 01605 #define TX_COUNT_TX_COUNT_BIT (0) 01606 #define TX_COUNT_TX_COUNT_BITS (11) 01607 01608 #define MAC_DMA_STATUS *((volatile int32u *)0x4000202Cu) 01609 #define MAC_DMA_STATUS_REG *((volatile int32u *)0x4000202Cu) 01610 #define MAC_DMA_STATUS_ADDR (0x4000202Cu) 01611 #define MAC_DMA_STATUS_RESET (0x00000000u) 01612 /* TX_ACTIVE_B field */ 01613 #define MAC_DMA_STATUS_TX_ACTIVE_B (0x00000008u) 01614 #define MAC_DMA_STATUS_TX_ACTIVE_B_MASK (0x00000008u) 01615 #define MAC_DMA_STATUS_TX_ACTIVE_B_BIT (3) 01616 #define MAC_DMA_STATUS_TX_ACTIVE_B_BITS (1) 01617 /* TX_ACTIVE_A field */ 01618 #define MAC_DMA_STATUS_TX_ACTIVE_A (0x00000004u) 01619 #define MAC_DMA_STATUS_TX_ACTIVE_A_MASK (0x00000004u) 01620 #define MAC_DMA_STATUS_TX_ACTIVE_A_BIT (2) 01621 #define MAC_DMA_STATUS_TX_ACTIVE_A_BITS (1) 01622 /* RX_ACTIVE_B field */ 01623 #define MAC_DMA_STATUS_RX_ACTIVE_B (0x00000002u) 01624 #define MAC_DMA_STATUS_RX_ACTIVE_B_MASK (0x00000002u) 01625 #define MAC_DMA_STATUS_RX_ACTIVE_B_BIT (1) 01626 #define MAC_DMA_STATUS_RX_ACTIVE_B_BITS (1) 01627 /* RX_ACTIVE_A field */ 01628 #define MAC_DMA_STATUS_RX_ACTIVE_A (0x00000001u) 01629 #define MAC_DMA_STATUS_RX_ACTIVE_A_MASK (0x00000001u) 01630 #define MAC_DMA_STATUS_RX_ACTIVE_A_BIT (0) 01631 #define MAC_DMA_STATUS_RX_ACTIVE_A_BITS (1) 01632 01633 #define MAC_DMA_CONFIG *((volatile int32u *)0x40002030u) 01634 #define MAC_DMA_CONFIG_REG *((volatile int32u *)0x40002030u) 01635 #define MAC_DMA_CONFIG_ADDR (0x40002030u) 01636 #define MAC_DMA_CONFIG_RESET (0x00000000u) 01637 /* TX_DMA_RESET field */ 01638 #define MAC_DMA_CONFIG_TX_DMA_RESET (0x00000020u) 01639 #define MAC_DMA_CONFIG_TX_DMA_RESET_MASK (0x00000020u) 01640 #define MAC_DMA_CONFIG_TX_DMA_RESET_BIT (5) 01641 #define MAC_DMA_CONFIG_TX_DMA_RESET_BITS (1) 01642 /* RX_DMA_RESET field */ 01643 #define MAC_DMA_CONFIG_RX_DMA_RESET (0x00000010u) 01644 #define MAC_DMA_CONFIG_RX_DMA_RESET_MASK (0x00000010u) 01645 #define MAC_DMA_CONFIG_RX_DMA_RESET_BIT (4) 01646 #define MAC_DMA_CONFIG_RX_DMA_RESET_BITS (1) 01647 /* TX_LOAD_B field */ 01648 #define MAC_DMA_CONFIG_TX_LOAD_B (0x00000008u) 01649 #define MAC_DMA_CONFIG_TX_LOAD_B_MASK (0x00000008u) 01650 #define MAC_DMA_CONFIG_TX_LOAD_B_BIT (3) 01651 #define MAC_DMA_CONFIG_TX_LOAD_B_BITS (1) 01652 /* TX_LOAD_A field */ 01653 #define MAC_DMA_CONFIG_TX_LOAD_A (0x00000004u) 01654 #define MAC_DMA_CONFIG_TX_LOAD_A_MASK (0x00000004u) 01655 #define MAC_DMA_CONFIG_TX_LOAD_A_BIT (2) 01656 #define MAC_DMA_CONFIG_TX_LOAD_A_BITS (1) 01657 /* RX_LOAD_B field */ 01658 #define MAC_DMA_CONFIG_RX_LOAD_B (0x00000002u) 01659 #define MAC_DMA_CONFIG_RX_LOAD_B_MASK (0x00000002u) 01660 #define MAC_DMA_CONFIG_RX_LOAD_B_BIT (1) 01661 #define MAC_DMA_CONFIG_RX_LOAD_B_BITS (1) 01662 /* RX_LOAD_A field */ 01663 #define MAC_DMA_CONFIG_RX_LOAD_A (0x00000001u) 01664 #define MAC_DMA_CONFIG_RX_LOAD_A_MASK (0x00000001u) 01665 #define MAC_DMA_CONFIG_RX_LOAD_A_BIT (0) 01666 #define MAC_DMA_CONFIG_RX_LOAD_A_BITS (1) 01667 01668 #define MAC_TIMER *((volatile int32u *)0x40002038u) 01669 #define MAC_TIMER_REG *((volatile int32u *)0x40002038u) 01670 #define MAC_TIMER_ADDR (0x40002038u) 01671 #define MAC_TIMER_RESET (0x00000000u) 01672 /* MAC_TIMER field */ 01673 #define MAC_TIMER_MAC_TIMER (0x000FFFFFu) 01674 #define MAC_TIMER_MAC_TIMER_MASK (0x000FFFFFu) 01675 #define MAC_TIMER_MAC_TIMER_BIT (0) 01676 #define MAC_TIMER_MAC_TIMER_BITS (20) 01677 01678 #define MAC_TIMER_COMPARE_A_H *((volatile int32u *)0x40002040u) 01679 #define MAC_TIMER_COMPARE_A_H_REG *((volatile int32u *)0x40002040u) 01680 #define MAC_TIMER_COMPARE_A_H_ADDR (0x40002040u) 01681 #define MAC_TIMER_COMPARE_A_H_RESET (0x00000000u) 01682 /* MAC_COMPARE_A_H field */ 01683 #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H (0x0000000Fu) 01684 #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_MASK (0x0000000Fu) 01685 #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT (0) 01686 #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS (4) 01687 01688 #define MAC_TIMER_COMPARE_A_L *((volatile int32u *)0x40002044u) 01689 #define MAC_TIMER_COMPARE_A_L_REG *((volatile int32u *)0x40002044u) 01690 #define MAC_TIMER_COMPARE_A_L_ADDR (0x40002044u) 01691 #define MAC_TIMER_COMPARE_A_L_RESET (0x00000000u) 01692 /* MAC_COMPARE_A_L field */ 01693 #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L (0x0000FFFFu) 01694 #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_MASK (0x0000FFFFu) 01695 #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT (0) 01696 #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS (16) 01697 01698 #define MAC_TIMER_COMPARE_B_H *((volatile int32u *)0x40002048u) 01699 #define MAC_TIMER_COMPARE_B_H_REG *((volatile int32u *)0x40002048u) 01700 #define MAC_TIMER_COMPARE_B_H_ADDR (0x40002048u) 01701 #define MAC_TIMER_COMPARE_B_H_RESET (0x00000000u) 01702 /* MAC_COMPARE_B_H field */ 01703 #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H (0x0000000Fu) 01704 #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_MASK (0x0000000Fu) 01705 #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT (0) 01706 #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS (4) 01707 01708 #define MAC_TIMER_COMPARE_B_L *((volatile int32u *)0x4000204Cu) 01709 #define MAC_TIMER_COMPARE_B_L_REG *((volatile int32u *)0x4000204Cu) 01710 #define MAC_TIMER_COMPARE_B_L_ADDR (0x4000204Cu) 01711 #define MAC_TIMER_COMPARE_B_L_RESET (0x00000000u) 01712 /* MAC_COMPARE_B_L field */ 01713 #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L (0x0000FFFFu) 01714 #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_MASK (0x0000FFFFu) 01715 #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT (0) 01716 #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS (16) 01717 01718 #define MAC_TIMER_CAPTURE_H *((volatile int32u *)0x40002050u) 01719 #define MAC_TIMER_CAPTURE_H_REG *((volatile int32u *)0x40002050u) 01720 #define MAC_TIMER_CAPTURE_H_ADDR (0x40002050u) 01721 #define MAC_TIMER_CAPTURE_H_RESET (0x00000000u) 01722 /* MAC_SFD_CAPTURE_HIGH field */ 01723 #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH (0x0000000Fu) 01724 #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_MASK (0x0000000Fu) 01725 #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT (0) 01726 #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS (4) 01727 01728 #define MAC_TIMER_CAPTURE_L *((volatile int32u *)0x40002054u) 01729 #define MAC_TIMER_CAPTURE_L_REG *((volatile int32u *)0x40002054u) 01730 #define MAC_TIMER_CAPTURE_L_ADDR (0x40002054u) 01731 #define MAC_TIMER_CAPTURE_L_RESET (0x00000000u) 01732 /* MAC_SFD_CAPTURE_LOW field */ 01733 #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW (0x0000FFFFu) 01734 #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_MASK (0x0000FFFFu) 01735 #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT (0) 01736 #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS (16) 01737 01738 #define MAC_BO_TIMER *((volatile int32u *)0x40002058u) 01739 #define MAC_BO_TIMER_REG *((volatile int32u *)0x40002058u) 01740 #define MAC_BO_TIMER_ADDR (0x40002058u) 01741 #define MAC_BO_TIMER_RESET (0x00000000u) 01742 /* MAC_BO_TIMER field */ 01743 #define MAC_BO_TIMER_MAC_BO_TIMER (0x00000FFFu) 01744 #define MAC_BO_TIMER_MAC_BO_TIMER_MASK (0x00000FFFu) 01745 #define MAC_BO_TIMER_MAC_BO_TIMER_BIT (0) 01746 #define MAC_BO_TIMER_MAC_BO_TIMER_BITS (12) 01747 01748 #define MAC_BOP_TIMER *((volatile int32u *)0x4000205Cu) 01749 #define MAC_BOP_TIMER_REG *((volatile int32u *)0x4000205Cu) 01750 #define MAC_BOP_TIMER_ADDR (0x4000205Cu) 01751 #define MAC_BOP_TIMER_RESET (0x00000000u) 01752 /* MAC_BOP_TIMER field */ 01753 #define MAC_BOP_TIMER_MAC_BOP_TIMER (0x0000007Fu) 01754 #define MAC_BOP_TIMER_MAC_BOP_TIMER_MASK (0x0000007Fu) 01755 #define MAC_BOP_TIMER_MAC_BOP_TIMER_BIT (0) 01756 #define MAC_BOP_TIMER_MAC_BOP_TIMER_BITS (7) 01757 01758 #define MAC_TX_STROBE *((volatile int32u *)0x40002060u) 01759 #define MAC_TX_STROBE_REG *((volatile int32u *)0x40002060u) 01760 #define MAC_TX_STROBE_ADDR (0x40002060u) 01761 #define MAC_TX_STROBE_RESET (0x00000000u) 01762 /* AUTO_CRC_TX field */ 01763 #define MAC_TX_STROBE_AUTO_CRC_TX (0x00000008u) 01764 #define MAC_TX_STROBE_AUTO_CRC_TX_MASK (0x00000008u) 01765 #define MAC_TX_STROBE_AUTO_CRC_TX_BIT (3) 01766 #define MAC_TX_STROBE_AUTO_CRC_TX_BITS (1) 01767 /* CCA_ON field */ 01768 #define MAC_TX_STROBE_CCA_ON (0x00000004u) 01769 #define MAC_TX_STROBE_CCA_ON_MASK (0x00000004u) 01770 #define MAC_TX_STROBE_CCA_ON_BIT (2) 01771 #define MAC_TX_STROBE_CCA_ON_BITS (1) 01772 /* MAC_TX_RST field */ 01773 #define MAC_TX_STROBE_MAC_TX_RST (0x00000002u) 01774 #define MAC_TX_STROBE_MAC_TX_RST_MASK (0x00000002u) 01775 #define MAC_TX_STROBE_MAC_TX_RST_BIT (1) 01776 #define MAC_TX_STROBE_MAC_TX_RST_BITS (1) 01777 /* START_TX field */ 01778 #define MAC_TX_STROBE_START_TX (0x00000001u) 01779 #define MAC_TX_STROBE_START_TX_MASK (0x00000001u) 01780 #define MAC_TX_STROBE_START_TX_BIT (0) 01781 #define MAC_TX_STROBE_START_TX_BITS (1) 01782 01783 #define MAC_ACK_STROBE *((volatile int32u *)0x40002064u) 01784 #define MAC_ACK_STROBE_REG *((volatile int32u *)0x40002064u) 01785 #define MAC_ACK_STROBE_ADDR (0x40002064u) 01786 #define MAC_ACK_STROBE_RESET (0x00000000u) 01787 /* MANUAL_ACK field */ 01788 #define MAC_ACK_STROBE_MANUAL_ACK (0x00000002u) 01789 #define MAC_ACK_STROBE_MANUAL_ACK_MASK (0x00000002u) 01790 #define MAC_ACK_STROBE_MANUAL_ACK_BIT (1) 01791 #define MAC_ACK_STROBE_MANUAL_ACK_BITS (1) 01792 /* FRAME_PENDING field */ 01793 #define MAC_ACK_STROBE_FRAME_PENDING (0x00000001u) 01794 #define MAC_ACK_STROBE_FRAME_PENDING_MASK (0x00000001u) 01795 #define MAC_ACK_STROBE_FRAME_PENDING_BIT (0) 01796 #define MAC_ACK_STROBE_FRAME_PENDING_BITS (1) 01797 01798 #define MAC_STATUS *((volatile int32u *)0x40002068u) 01799 #define MAC_STATUS_REG *((volatile int32u *)0x40002068u) 01800 #define MAC_STATUS_ADDR (0x40002068u) 01801 #define MAC_STATUS_RESET (0x00000000u) 01802 /* RX_B_PEND_TX_ACK field */ 01803 #define MAC_STATUS_RX_B_PEND_TX_ACK (0x00000800u) 01804 #define MAC_STATUS_RX_B_PEND_TX_ACK_MASK (0x00000800u) 01805 #define MAC_STATUS_RX_B_PEND_TX_ACK_BIT (11) 01806 #define MAC_STATUS_RX_B_PEND_TX_ACK_BITS (1) 01807 /* RX_A_PEND_TX_ACK field */ 01808 #define MAC_STATUS_RX_A_PEND_TX_ACK (0x00000400u) 01809 #define MAC_STATUS_RX_A_PEND_TX_ACK_MASK (0x00000400u) 01810 #define MAC_STATUS_RX_A_PEND_TX_ACK_BIT (10) 01811 #define MAC_STATUS_RX_A_PEND_TX_ACK_BITS (1) 01812 /* RX_B_LAST_UNLOAD field */ 01813 #define MAC_STATUS_RX_B_LAST_UNLOAD (0x00000200u) 01814 #define MAC_STATUS_RX_B_LAST_UNLOAD_MASK (0x00000200u) 01815 #define MAC_STATUS_RX_B_LAST_UNLOAD_BIT (9) 01816 #define MAC_STATUS_RX_B_LAST_UNLOAD_BITS (1) 01817 /* RX_A_LAST_UNLOAD field */ 01818 #define MAC_STATUS_RX_A_LAST_UNLOAD (0x00000100u) 01819 #define MAC_STATUS_RX_A_LAST_UNLOAD_MASK (0x00000100u) 01820 #define MAC_STATUS_RX_A_LAST_UNLOAD_BIT (8) 01821 #define MAC_STATUS_RX_A_LAST_UNLOAD_BITS (1) 01822 /* WRONG_FORMAT field */ 01823 #define MAC_STATUS_WRONG_FORMAT (0x00000080u) 01824 #define MAC_STATUS_WRONG_FORMAT_MASK (0x00000080u) 01825 #define MAC_STATUS_WRONG_FORMAT_BIT (7) 01826 #define MAC_STATUS_WRONG_FORMAT_BITS (1) 01827 /* WRONG_ADDRESS field */ 01828 #define MAC_STATUS_WRONG_ADDRESS (0x00000040u) 01829 #define MAC_STATUS_WRONG_ADDRESS_MASK (0x00000040u) 01830 #define MAC_STATUS_WRONG_ADDRESS_BIT (6) 01831 #define MAC_STATUS_WRONG_ADDRESS_BITS (1) 01832 /* RX_ACK_REC field */ 01833 #define MAC_STATUS_RX_ACK_REC (0x00000020u) 01834 #define MAC_STATUS_RX_ACK_REC_MASK (0x00000020u) 01835 #define MAC_STATUS_RX_ACK_REC_BIT (5) 01836 #define MAC_STATUS_RX_ACK_REC_BITS (1) 01837 /* SENDING_ACK field */ 01838 #define MAC_STATUS_SENDING_ACK (0x00000010u) 01839 #define MAC_STATUS_SENDING_ACK_MASK (0x00000010u) 01840 #define MAC_STATUS_SENDING_ACK_BIT (4) 01841 #define MAC_STATUS_SENDING_ACK_BITS (1) 01842 /* RUN_BO field */ 01843 #define MAC_STATUS_RUN_BO (0x00000008u) 01844 #define MAC_STATUS_RUN_BO_MASK (0x00000008u) 01845 #define MAC_STATUS_RUN_BO_BIT (3) 01846 #define MAC_STATUS_RUN_BO_BITS (1) 01847 /* TX_FRAME field */ 01848 #define MAC_STATUS_TX_FRAME (0x00000004u) 01849 #define MAC_STATUS_TX_FRAME_MASK (0x00000004u) 01850 #define MAC_STATUS_TX_FRAME_BIT (2) 01851 #define MAC_STATUS_TX_FRAME_BITS (1) 01852 /* RX_FRAME field */ 01853 #define MAC_STATUS_RX_FRAME (0x00000002u) 01854 #define MAC_STATUS_RX_FRAME_MASK (0x00000002u) 01855 #define MAC_STATUS_RX_FRAME_BIT (1) 01856 #define MAC_STATUS_RX_FRAME_BITS (1) 01857 /* RX_CRC_PASS field */ 01858 #define MAC_STATUS_RX_CRC_PASS (0x00000001u) 01859 #define MAC_STATUS_RX_CRC_PASS_MASK (0x00000001u) 01860 #define MAC_STATUS_RX_CRC_PASS_BIT (0) 01861 #define MAC_STATUS_RX_CRC_PASS_BITS (1) 01862 01863 #define TX_CRC *((volatile int32u *)0x4000206Cu) 01864 #define TX_CRC_REG *((volatile int32u *)0x4000206Cu) 01865 #define TX_CRC_ADDR (0x4000206Cu) 01866 #define TX_CRC_RESET (0x00000000u) 01867 /* TX_CRC field */ 01868 #define TX_CRC_TX_CRC (0x0000FFFFu) 01869 #define TX_CRC_TX_CRC_MASK (0x0000FFFFu) 01870 #define TX_CRC_TX_CRC_BIT (0) 01871 #define TX_CRC_TX_CRC_BITS (16) 01872 01873 #define RX_CRC *((volatile int32u *)0x40002070u) 01874 #define RX_CRC_REG *((volatile int32u *)0x40002070u) 01875 #define RX_CRC_ADDR (0x40002070u) 01876 #define RX_CRC_RESET (0x00000000u) 01877 /* RX_CRC field */ 01878 #define RX_CRC_RX_CRC (0x0000FFFFu) 01879 #define RX_CRC_RX_CRC_MASK (0x0000FFFFu) 01880 #define RX_CRC_RX_CRC_BIT (0) 01881 #define RX_CRC_RX_CRC_BITS (16) 01882 01883 #define MAC_ACK_TO *((volatile int32u *)0x40002074u) 01884 #define MAC_ACK_TO_REG *((volatile int32u *)0x40002074u) 01885 #define MAC_ACK_TO_ADDR (0x40002074u) 01886 #define MAC_ACK_TO_RESET (0x00000300u) 01887 /* ACK_TO field */ 01888 #define MAC_ACK_TO_ACK_TO (0x00003FFFu) 01889 #define MAC_ACK_TO_ACK_TO_MASK (0x00003FFFu) 01890 #define MAC_ACK_TO_ACK_TO_BIT (0) 01891 #define MAC_ACK_TO_ACK_TO_BITS (14) 01892 01893 #define MAC_BOP_COMPARE *((volatile int32u *)0x40002078u) 01894 #define MAC_BOP_COMPARE_REG *((volatile int32u *)0x40002078u) 01895 #define MAC_BOP_COMPARE_ADDR (0x40002078u) 01896 #define MAC_BOP_COMPARE_RESET (0x00000014u) 01897 /* MAC_BOP_COMPARE field */ 01898 #define MAC_BOP_COMPARE_MAC_BOP_COMPARE (0x0000007Fu) 01899 #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_MASK (0x0000007Fu) 01900 #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT (0) 01901 #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS (7) 01902 01903 #define MAC_TX_ACK_FRAME *((volatile int32u *)0x4000207Cu) 01904 #define MAC_TX_ACK_FRAME_REG *((volatile int32u *)0x4000207Cu) 01905 #define MAC_TX_ACK_FRAME_ADDR (0x4000207Cu) 01906 #define MAC_TX_ACK_FRAME_RESET (0x00000002u) 01907 /* ACK_SRC_AM field */ 01908 #define MAC_TX_ACK_FRAME_ACK_SRC_AM (0x0000C000u) 01909 #define MAC_TX_ACK_FRAME_ACK_SRC_AM_MASK (0x0000C000u) 01910 #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BIT (14) 01911 #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BITS (2) 01912 /* RES1213 field */ 01913 #define MAC_TX_ACK_FRAME_RES1213 (0x00003000u) 01914 #define MAC_TX_ACK_FRAME_RES1213_MASK (0x00003000u) 01915 #define MAC_TX_ACK_FRAME_RES1213_BIT (12) 01916 #define MAC_TX_ACK_FRAME_RES1213_BITS (2) 01917 /* ACK_DST_AM field */ 01918 #define MAC_TX_ACK_FRAME_ACK_DST_AM (0x00000C00u) 01919 #define MAC_TX_ACK_FRAME_ACK_DST_AM_MASK (0x00000C00u) 01920 #define MAC_TX_ACK_FRAME_ACK_DST_AM_BIT (10) 01921 #define MAC_TX_ACK_FRAME_ACK_DST_AM_BITS (2) 01922 /* RES789 field */ 01923 #define MAC_TX_ACK_FRAME_RES789 (0x00000380u) 01924 #define MAC_TX_ACK_FRAME_RES789_MASK (0x00000380u) 01925 #define MAC_TX_ACK_FRAME_RES789_BIT (7) 01926 #define MAC_TX_ACK_FRAME_RES789_BITS (3) 01927 /* ACK_IP field */ 01928 #define MAC_TX_ACK_FRAME_ACK_IP (0x00000040u) 01929 #define MAC_TX_ACK_FRAME_ACK_IP_MASK (0x00000040u) 01930 #define MAC_TX_ACK_FRAME_ACK_IP_BIT (6) 01931 #define MAC_TX_ACK_FRAME_ACK_IP_BITS (1) 01932 /* ACK_ACK_REQ field */ 01933 #define MAC_TX_ACK_FRAME_ACK_ACK_REQ (0x00000020u) 01934 #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_MASK (0x00000020u) 01935 #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BIT (5) 01936 #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BITS (1) 01937 /* ACK_FRAME_P field */ 01938 #define MAC_TX_ACK_FRAME_ACK_FRAME_P (0x00000010u) 01939 #define MAC_TX_ACK_FRAME_ACK_FRAME_P_MASK (0x00000010u) 01940 #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BIT (4) 01941 #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BITS (1) 01942 /* ACK_SEC_EN field */ 01943 #define MAC_TX_ACK_FRAME_ACK_SEC_EN (0x00000008u) 01944 #define MAC_TX_ACK_FRAME_ACK_SEC_EN_MASK (0x00000008u) 01945 #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BIT (3) 01946 #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BITS (1) 01947 /* ACK_FRAME_T field */ 01948 #define MAC_TX_ACK_FRAME_ACK_FRAME_T (0x00000007u) 01949 #define MAC_TX_ACK_FRAME_ACK_FRAME_T_MASK (0x00000007u) 01950 #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT (0) 01951 #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS (3) 01952 01953 #define MAC_CONFIG *((volatile int32u *)0x40002080u) 01954 #define MAC_CONFIG_REG *((volatile int32u *)0x40002080u) 01955 #define MAC_CONFIG_ADDR (0x40002080u) 01956 #define MAC_CONFIG_RESET (0x00000000u) 01957 /* RSSI_INST_EN field */ 01958 #define MAC_CONFIG_RSSI_INST_EN (0x00000004u) 01959 #define MAC_CONFIG_RSSI_INST_EN_MASK (0x00000004u) 01960 #define MAC_CONFIG_RSSI_INST_EN_BIT (2) 01961 #define MAC_CONFIG_RSSI_INST_EN_BITS (1) 01962 /* SPI_SPY_EN field */ 01963 #define MAC_CONFIG_SPI_SPY_EN (0x00000002u) 01964 #define MAC_CONFIG_SPI_SPY_EN_MASK (0x00000002u) 01965 #define MAC_CONFIG_SPI_SPY_EN_BIT (1) 01966 #define MAC_CONFIG_SPI_SPY_EN_BITS (1) 01967 /* MAC_MODE field */ 01968 #define MAC_CONFIG_MAC_MODE (0x00000001u) 01969 #define MAC_CONFIG_MAC_MODE_MASK (0x00000001u) 01970 #define MAC_CONFIG_MAC_MODE_BIT (0) 01971 #define MAC_CONFIG_MAC_MODE_BITS (1) 01972 01973 #define MAC_RX_CONFIG *((volatile int32u *)0x40002084u) 01974 #define MAC_RX_CONFIG_REG *((volatile int32u *)0x40002084u) 01975 #define MAC_RX_CONFIG_ADDR (0x40002084u) 01976 #define MAC_RX_CONFIG_RESET (0x00000000u) 01977 /* AUTO_ACK field */ 01978 #define MAC_RX_CONFIG_AUTO_ACK (0x00000080u) 01979 #define MAC_RX_CONFIG_AUTO_ACK_MASK (0x00000080u) 01980 #define MAC_RX_CONFIG_AUTO_ACK_BIT (7) 01981 #define MAC_RX_CONFIG_AUTO_ACK_BITS (1) 01982 /* APPEND_INFO field */ 01983 #define MAC_RX_CONFIG_APPEND_INFO (0x00000040u) 01984 #define MAC_RX_CONFIG_APPEND_INFO_MASK (0x00000040u) 01985 #define MAC_RX_CONFIG_APPEND_INFO_BIT (6) 01986 #define MAC_RX_CONFIG_APPEND_INFO_BITS (1) 01987 /* COORDINATOR field */ 01988 #define MAC_RX_CONFIG_COORDINATOR (0x00000020u) 01989 #define MAC_RX_CONFIG_COORDINATOR_MASK (0x00000020u) 01990 #define MAC_RX_CONFIG_COORDINATOR_BIT (5) 01991 #define MAC_RX_CONFIG_COORDINATOR_BITS (1) 01992 /* FILT_ADDR_ON field */ 01993 #define MAC_RX_CONFIG_FILT_ADDR_ON (0x00000010u) 01994 #define MAC_RX_CONFIG_FILT_ADDR_ON_MASK (0x00000010u) 01995 #define MAC_RX_CONFIG_FILT_ADDR_ON_BIT (4) 01996 #define MAC_RX_CONFIG_FILT_ADDR_ON_BITS (1) 01997 /* RES_FILT_PASS_ADDR field */ 01998 #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR (0x00000008u) 01999 #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_MASK (0x00000008u) 02000 #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BIT (3) 02001 #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BITS (1) 02002 /* RES_FILT_PASS field */ 02003 #define MAC_RX_CONFIG_RES_FILT_PASS (0x00000004u) 02004 #define MAC_RX_CONFIG_RES_FILT_PASS_MASK (0x00000004u) 02005 #define MAC_RX_CONFIG_RES_FILT_PASS_BIT (2) 02006 #define MAC_RX_CONFIG_RES_FILT_PASS_BITS (1) 02007 /* FILT_FORMAT_ON field */ 02008 #define MAC_RX_CONFIG_FILT_FORMAT_ON (0x00000002u) 02009 #define MAC_RX_CONFIG_FILT_FORMAT_ON_MASK (0x00000002u) 02010 #define MAC_RX_CONFIG_FILT_FORMAT_ON_BIT (1) 02011 #define MAC_RX_CONFIG_FILT_FORMAT_ON_BITS (1) 02012 /* MAC_RX_RST field */ 02013 #define MAC_RX_CONFIG_MAC_RX_RST (0x00000001u) 02014 #define MAC_RX_CONFIG_MAC_RX_RST_MASK (0x00000001u) 02015 #define MAC_RX_CONFIG_MAC_RX_RST_BIT (0) 02016 #define MAC_RX_CONFIG_MAC_RX_RST_BITS (1) 02017 02018 #define MAC_TX_CONFIG *((volatile int32u *)0x40002088u) 02019 #define MAC_TX_CONFIG_REG *((volatile int32u *)0x40002088u) 02020 #define MAC_TX_CONFIG_ADDR (0x40002088u) 02021 #define MAC_TX_CONFIG_RESET (0x00000008u) 02022 /* SLOTTED field */ 02023 #define MAC_TX_CONFIG_SLOTTED (0x00000010u) 02024 #define MAC_TX_CONFIG_SLOTTED_MASK (0x00000010u) 02025 #define MAC_TX_CONFIG_SLOTTED_BIT (4) 02026 #define MAC_TX_CONFIG_SLOTTED_BITS (1) 02027 /* CCA_DELAY field */ 02028 #define MAC_TX_CONFIG_CCA_DELAY (0x00000008u) 02029 #define MAC_TX_CONFIG_CCA_DELAY_MASK (0x00000008u) 02030 #define MAC_TX_CONFIG_CCA_DELAY_BIT (3) 02031 #define MAC_TX_CONFIG_CCA_DELAY_BITS (1) 02032 /* SLOTTED_ACK field */ 02033 #define MAC_TX_CONFIG_SLOTTED_ACK (0x00000004u) 02034 #define MAC_TX_CONFIG_SLOTTED_ACK_MASK (0x00000004u) 02035 #define MAC_TX_CONFIG_SLOTTED_ACK_BIT (2) 02036 #define MAC_TX_CONFIG_SLOTTED_ACK_BITS (1) 02037 /* INFINITE_CRC field */ 02038 #define MAC_TX_CONFIG_INFINITE_CRC (0x00000002u) 02039 #define MAC_TX_CONFIG_INFINITE_CRC_MASK (0x00000002u) 02040 #define MAC_TX_CONFIG_INFINITE_CRC_BIT (1) 02041 #define MAC_TX_CONFIG_INFINITE_CRC_BITS (1) 02042 /* WAIT_ACK field */ 02043 #define MAC_TX_CONFIG_WAIT_ACK (0x00000001u) 02044 #define MAC_TX_CONFIG_WAIT_ACK_MASK (0x00000001u) 02045 #define MAC_TX_CONFIG_WAIT_ACK_BIT (0) 02046 #define MAC_TX_CONFIG_WAIT_ACK_BITS (1) 02047 02048 #define MAC_TIMER_CTRL *((volatile int32u *)0x4000208Cu) 02049 #define MAC_TIMER_CTRL_REG *((volatile int32u *)0x4000208Cu) 02050 #define MAC_TIMER_CTRL_ADDR (0x4000208Cu) 02051 #define MAC_TIMER_CTRL_RESET (0x00000000u) 02052 /* COMP_A_SYNC field */ 02053 #define MAC_TIMER_CTRL_COMP_A_SYNC (0x00000040u) 02054 #define MAC_TIMER_CTRL_COMP_A_SYNC_MASK (0x00000040u) 02055 #define MAC_TIMER_CTRL_COMP_A_SYNC_BIT (6) 02056 #define MAC_TIMER_CTRL_COMP_A_SYNC_BITS (1) 02057 /* BOP_TIMER_RST field */ 02058 #define MAC_TIMER_CTRL_BOP_TIMER_RST (0x00000020u) 02059 #define MAC_TIMER_CTRL_BOP_TIMER_RST_MASK (0x00000020u) 02060 #define MAC_TIMER_CTRL_BOP_TIMER_RST_BIT (5) 02061 #define MAC_TIMER_CTRL_BOP_TIMER_RST_BITS (1) 02062 /* BOP_TIMER_EN field */ 02063 #define MAC_TIMER_CTRL_BOP_TIMER_EN (0x00000010u) 02064 #define MAC_TIMER_CTRL_BOP_TIMER_EN_MASK (0x00000010u) 02065 #define MAC_TIMER_CTRL_BOP_TIMER_EN_BIT (4) 02066 #define MAC_TIMER_CTRL_BOP_TIMER_EN_BITS (1) 02067 /* BO_TIMER_RST field */ 02068 #define MAC_TIMER_CTRL_BO_TIMER_RST (0x00000008u) 02069 #define MAC_TIMER_CTRL_BO_TIMER_RST_MASK (0x00000008u) 02070 #define MAC_TIMER_CTRL_BO_TIMER_RST_BIT (3) 02071 #define MAC_TIMER_CTRL_BO_TIMER_RST_BITS (1) 02072 /* BO_TIMER_EN field */ 02073 #define MAC_TIMER_CTRL_BO_TIMER_EN (0x00000004u) 02074 #define MAC_TIMER_CTRL_BO_TIMER_EN_MASK (0x00000004u) 02075 #define MAC_TIMER_CTRL_BO_TIMER_EN_BIT (2) 02076 #define MAC_TIMER_CTRL_BO_TIMER_EN_BITS (1) 02077 /* MAC_TIMER_RST field */ 02078 #define MAC_TIMER_CTRL_MAC_TIMER_RST (0x00000002u) 02079 #define MAC_TIMER_CTRL_MAC_TIMER_RST_MASK (0x00000002u) 02080 #define MAC_TIMER_CTRL_MAC_TIMER_RST_BIT (1) 02081 #define MAC_TIMER_CTRL_MAC_TIMER_RST_BITS (1) 02082 /* MAC_TIMER_EN field */ 02083 #define MAC_TIMER_CTRL_MAC_TIMER_EN (0x00000001u) 02084 #define MAC_TIMER_CTRL_MAC_TIMER_EN_MASK (0x00000001u) 02085 #define MAC_TIMER_CTRL_MAC_TIMER_EN_BIT (0) 02086 #define MAC_TIMER_CTRL_MAC_TIMER_EN_BITS (1) 02087 02088 #define PAN_ID *((volatile int32u *)0x40002090u) 02089 #define PAN_ID_REG *((volatile int32u *)0x40002090u) 02090 #define PAN_ID_ADDR (0x40002090u) 02091 #define PAN_ID_RESET (0x00000000u) 02092 /* PAN_ID field */ 02093 #define PAN_ID_PAN_ID (0x0000FFFFu) 02094 #define PAN_ID_PAN_ID_MASK (0x0000FFFFu) 02095 #define PAN_ID_PAN_ID_BIT (0) 02096 #define PAN_ID_PAN_ID_BITS (16) 02097 02098 #define SHORT_ADDR *((volatile int32u *)0x40002094u) 02099 #define SHORT_ADDR_REG *((volatile int32u *)0x40002094u) 02100 #define SHORT_ADDR_ADDR (0x40002094u) 02101 #define SHORT_ADDR_RESET (0x00000000u) 02102 /* SHORT_ADDR field */ 02103 #define SHORT_ADDR_SHORT_ADDR (0x0000FFFFu) 02104 #define SHORT_ADDR_SHORT_ADDR_MASK (0x0000FFFFu) 02105 #define SHORT_ADDR_SHORT_ADDR_BIT (0) 02106 #define SHORT_ADDR_SHORT_ADDR_BITS (16) 02107 02108 #define EXT_ADDR_0 *((volatile int32u *)0x40002098u) 02109 #define EXT_ADDR_0_REG *((volatile int32u *)0x40002098u) 02110 #define EXT_ADDR_0_ADDR (0x40002098u) 02111 #define EXT_ADDR_0_RESET (0x00000000u) 02112 /* EXT_ADDR_0 field */ 02113 #define EXT_ADDR_0_EXT_ADDR_0 (0x0000FFFFu) 02114 #define EXT_ADDR_0_EXT_ADDR_0_MASK (0x0000FFFFu) 02115 #define EXT_ADDR_0_EXT_ADDR_0_BIT (0) 02116 #define EXT_ADDR_0_EXT_ADDR_0_BITS (16) 02117 02118 #define EXT_ADDR_1 *((volatile int32u *)0x4000209Cu) 02119 #define EXT_ADDR_1_REG *((volatile int32u *)0x4000209Cu) 02120 #define EXT_ADDR_1_ADDR (0x4000209Cu) 02121 #define EXT_ADDR_1_RESET (0x00000000u) 02122 /* EXT_ADDR_1 field */ 02123 #define EXT_ADDR_1_EXT_ADDR_1 (0x0000FFFFu) 02124 #define EXT_ADDR_1_EXT_ADDR_1_MASK (0x0000FFFFu) 02125 #define EXT_ADDR_1_EXT_ADDR_1_BIT (0) 02126 #define EXT_ADDR_1_EXT_ADDR_1_BITS (16) 02127 02128 #define EXT_ADDR_2 *((volatile int32u *)0x400020A0u) 02129 #define EXT_ADDR_2_REG *((volatile int32u *)0x400020A0u) 02130 #define EXT_ADDR_2_ADDR (0x400020A0u) 02131 #define EXT_ADDR_2_RESET (0x00000000u) 02132 /* EXT_ADDR_2 field */ 02133 #define EXT_ADDR_2_EXT_ADDR_2 (0x0000FFFFu) 02134 #define EXT_ADDR_2_EXT_ADDR_2_MASK (0x0000FFFFu) 02135 #define EXT_ADDR_2_EXT_ADDR_2_BIT (0) 02136 #define EXT_ADDR_2_EXT_ADDR_2_BITS (16) 02137 02138 #define EXT_ADDR_3 *((volatile int32u *)0x400020A4u) 02139 #define EXT_ADDR_3_REG *((volatile int32u *)0x400020A4u) 02140 #define EXT_ADDR_3_ADDR (0x400020A4u) 02141 #define EXT_ADDR_3_RESET (0x00000000u) 02142 /* EXT_ADDR_3 field */ 02143 #define EXT_ADDR_3_EXT_ADDR_3 (0x0000FFFFu) 02144 #define EXT_ADDR_3_EXT_ADDR_3_MASK (0x0000FFFFu) 02145 #define EXT_ADDR_3_EXT_ADDR_3_BIT (0) 02146 #define EXT_ADDR_3_EXT_ADDR_3_BITS (16) 02147 02148 #define MAC_STATE *((volatile int32u *)0x400020A8u) 02149 #define MAC_STATE_REG *((volatile int32u *)0x400020A8u) 02150 #define MAC_STATE_ADDR (0x400020A8u) 02151 #define MAC_STATE_RESET (0x00000000u) 02152 /* SPY_STATE field */ 02153 #define MAC_STATE_SPY_STATE (0x00000700u) 02154 #define MAC_STATE_SPY_STATE_MASK (0x00000700u) 02155 #define MAC_STATE_SPY_STATE_BIT (8) 02156 #define MAC_STATE_SPY_STATE_BITS (3) 02157 /* ACK_STATE field */ 02158 #define MAC_STATE_ACK_STATE (0x000000C0u) 02159 #define MAC_STATE_ACK_STATE_MASK (0x000000C0u) 02160 #define MAC_STATE_ACK_STATE_BIT (6) 02161 #define MAC_STATE_ACK_STATE_BITS (2) 02162 /* BO_STATE field */ 02163 #define MAC_STATE_BO_STATE (0x0000003Cu) 02164 #define MAC_STATE_BO_STATE_MASK (0x0000003Cu) 02165 #define MAC_STATE_BO_STATE_BIT (2) 02166 #define MAC_STATE_BO_STATE_BITS (4) 02167 /* TOP_STATE field */ 02168 #define MAC_STATE_TOP_STATE (0x00000003u) 02169 #define MAC_STATE_TOP_STATE_MASK (0x00000003u) 02170 #define MAC_STATE_TOP_STATE_BIT (0) 02171 #define MAC_STATE_TOP_STATE_BITS (2) 02172 02173 #define RX_STATE *((volatile int32u *)0x400020ACu) 02174 #define RX_STATE_REG *((volatile int32u *)0x400020ACu) 02175 #define RX_STATE_ADDR (0x400020ACu) 02176 #define RX_STATE_RESET (0x00000000u) 02177 /* RX_BUFFER_STATE field */ 02178 #define RX_STATE_RX_BUFFER_STATE (0x000001E0u) 02179 #define RX_STATE_RX_BUFFER_STATE_MASK (0x000001E0u) 02180 #define RX_STATE_RX_BUFFER_STATE_BIT (5) 02181 #define RX_STATE_RX_BUFFER_STATE_BITS (4) 02182 /* RX_TOP_STATE field */ 02183 #define RX_STATE_RX_TOP_STATE (0x0000001Fu) 02184 #define RX_STATE_RX_TOP_STATE_MASK (0x0000001Fu) 02185 #define RX_STATE_RX_TOP_STATE_BIT (0) 02186 #define RX_STATE_RX_TOP_STATE_BITS (5) 02187 02188 #define TX_STATE *((volatile int32u *)0x400020B0u) 02189 #define TX_STATE_REG *((volatile int32u *)0x400020B0u) 02190 #define TX_STATE_ADDR (0x400020B0u) 02191 #define TX_STATE_RESET (0x00000000u) 02192 /* TX_BUFFER_STATE field */ 02193 #define TX_STATE_TX_BUFFER_STATE (0x000000F0u) 02194 #define TX_STATE_TX_BUFFER_STATE_MASK (0x000000F0u) 02195 #define TX_STATE_TX_BUFFER_STATE_BIT (4) 02196 #define TX_STATE_TX_BUFFER_STATE_BITS (4) 02197 /* TX_TOP_STATE field */ 02198 #define TX_STATE_TX_TOP_STATE (0x0000000Fu) 02199 #define TX_STATE_TX_TOP_STATE_MASK (0x0000000Fu) 02200 #define TX_STATE_TX_TOP_STATE_BIT (0) 02201 #define TX_STATE_TX_TOP_STATE_BITS (4) 02202 02203 #define DMA_STATE *((volatile int32u *)0x400020B4u) 02204 #define DMA_STATE_REG *((volatile int32u *)0x400020B4u) 02205 #define DMA_STATE_ADDR (0x400020B4u) 02206 #define DMA_STATE_RESET (0x00000000u) 02207 /* DMA_RX_STATE field */ 02208 #define DMA_STATE_DMA_RX_STATE (0x00000038u) 02209 #define DMA_STATE_DMA_RX_STATE_MASK (0x00000038u) 02210 #define DMA_STATE_DMA_RX_STATE_BIT (3) 02211 #define DMA_STATE_DMA_RX_STATE_BITS (3) 02212 /* DMA_TX_STATE field */ 02213 #define DMA_STATE_DMA_TX_STATE (0x00000007u) 02214 #define DMA_STATE_DMA_TX_STATE_MASK (0x00000007u) 02215 #define DMA_STATE_DMA_TX_STATE_BIT (0) 02216 #define DMA_STATE_DMA_TX_STATE_BITS (3) 02217 02218 #define MAC_DEBUG *((volatile int32u *)0x400020B8u) 02219 #define MAC_DEBUG_REG *((volatile int32u *)0x400020B8u) 02220 #define MAC_DEBUG_ADDR (0x400020B8u) 02221 #define MAC_DEBUG_RESET (0x00000000u) 02222 /* SW_DEBUG_OUT field */ 02223 #define MAC_DEBUG_SW_DEBUG_OUT (0x00000060u) 02224 #define MAC_DEBUG_SW_DEBUG_OUT_MASK (0x00000060u) 02225 #define MAC_DEBUG_SW_DEBUG_OUT_BIT (5) 02226 #define MAC_DEBUG_SW_DEBUG_OUT_BITS (2) 02227 /* MAC_DEBUG_MUX field */ 02228 #define MAC_DEBUG_MAC_DEBUG_MUX (0x0000001Fu) 02229 #define MAC_DEBUG_MAC_DEBUG_MUX_MASK (0x0000001Fu) 02230 #define MAC_DEBUG_MAC_DEBUG_MUX_BIT (0) 02231 #define MAC_DEBUG_MAC_DEBUG_MUX_BITS (5) 02232 02233 #define MAC_DEBUG_VIEW *((volatile int32u *)0x400020BCu) 02234 #define MAC_DEBUG_VIEW_REG *((volatile int32u *)0x400020BCu) 02235 #define MAC_DEBUG_VIEW_ADDR (0x400020BCu) 02236 #define MAC_DEBUG_VIEW_RESET (0x00000010u) 02237 /* MAC_DEBUG_VIEW field */ 02238 #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW (0x0000FFFFu) 02239 #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_MASK (0x0000FFFFu) 02240 #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT (0) 02241 #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS (16) 02242 02243 #define MAC_RSSI_DELAY *((volatile int32u *)0x400020C0u) 02244 #define MAC_RSSI_DELAY_REG *((volatile int32u *)0x400020C0u) 02245 #define MAC_RSSI_DELAY_ADDR (0x400020C0u) 02246 #define MAC_RSSI_DELAY_RESET (0x00000000u) 02247 /* RSSI_INST_DELAY_OK field */ 02248 #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK (0x00000FC0u) 02249 #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_MASK (0x00000FC0u) 02250 #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BIT (6) 02251 #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BITS (6) 02252 /* RSSI_INST_DELAY field */ 02253 #define MAC_RSSI_DELAY_RSSI_INST_DELAY (0x0000003Fu) 02254 #define MAC_RSSI_DELAY_RSSI_INST_DELAY_MASK (0x0000003Fu) 02255 #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT (0) 02256 #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS (6) 02257 02258 #define PANID_COUNT *((volatile int32u *)0x400020C4u) 02259 #define PANID_COUNT_REG *((volatile int32u *)0x400020C4u) 02260 #define PANID_COUNT_ADDR (0x400020C4u) 02261 #define PANID_COUNT_RESET (0x00000000u) 02262 /* PANID_COUNT field */ 02263 #define PANID_COUNT_PANID_COUNT (0x0000FFFFu) 02264 #define PANID_COUNT_PANID_COUNT_MASK (0x0000FFFFu) 02265 #define PANID_COUNT_PANID_COUNT_BIT (0) 02266 #define PANID_COUNT_PANID_COUNT_BITS (16) 02267 02268 #define NONPAN_COUNT *((volatile int32u *)0x400020C8u) 02269 #define NONPAN_COUNT_REG *((volatile int32u *)0x400020C8u) 02270 #define NONPAN_COUNT_ADDR (0x400020C8u) 02271 #define NONPAN_COUNT_RESET (0x00000000u) 02272 /* NONPAN_COUNT field */ 02273 #define NONPAN_COUNT_NONPAN_COUNT (0x0000FFFFu) 02274 #define NONPAN_COUNT_NONPAN_COUNT_MASK (0x0000FFFFu) 02275 #define NONPAN_COUNT_NONPAN_COUNT_BIT (0) 02276 #define NONPAN_COUNT_NONPAN_COUNT_BITS (16) 02277 02278 /* SECURITY block */ 02279 #define DATA_SECURITY_BASE (0x40003000u) 02280 #define DATA_SECURITY_END (0x40003044u) 02281 #define DATA_SECURITY_SIZE (DATA_SECURITY_END - DATA_SECURITY_BASE + 1) 02282 02283 #define SECURITY_CONFIG *((volatile int32u *)0x40003000u) 02284 #define SECURITY_CONFIG_REG *((volatile int32u *)0x40003000u) 02285 #define SECURITY_CONFIG_ADDR (0x40003000u) 02286 #define SECURITY_CONFIG_RESET (0x00000000u) 02287 /* SEC_RST field */ 02288 #define SECURITY_CONFIG_SEC_RST (0x00000080u) 02289 #define SECURITY_CONFIG_SEC_RST_MASK (0x00000080u) 02290 #define SECURITY_CONFIG_SEC_RST_BIT (7) 02291 #define SECURITY_CONFIG_SEC_RST_BITS (1) 02292 /* CTR_IN field */ 02293 #define SECURITY_CONFIG_CTR_IN (0x00000040u) 02294 #define SECURITY_CONFIG_CTR_IN_MASK (0x00000040u) 02295 #define SECURITY_CONFIG_CTR_IN_BIT (6) 02296 #define SECURITY_CONFIG_CTR_IN_BITS (1) 02297 /* MIC_XOR_CT field */ 02298 #define SECURITY_CONFIG_MIC_XOR_CT (0x00000020u) 02299 #define SECURITY_CONFIG_MIC_XOR_CT_MASK (0x00000020u) 02300 #define SECURITY_CONFIG_MIC_XOR_CT_BIT (5) 02301 #define SECURITY_CONFIG_MIC_XOR_CT_BITS (1) 02302 /* CBC_XOR_PT field */ 02303 #define SECURITY_CONFIG_CBC_XOR_PT (0x00000010u) 02304 #define SECURITY_CONFIG_CBC_XOR_PT_MASK (0x00000010u) 02305 #define SECURITY_CONFIG_CBC_XOR_PT_BIT (4) 02306 #define SECURITY_CONFIG_CBC_XOR_PT_BITS (1) 02307 /* CT_TO_CBC_ST field */ 02308 #define SECURITY_CONFIG_CT_TO_CBC_ST (0x00000008u) 02309 #define SECURITY_CONFIG_CT_TO_CBC_ST_MASK (0x00000008u) 02310 #define SECURITY_CONFIG_CT_TO_CBC_ST_BIT (3) 02311 #define SECURITY_CONFIG_CT_TO_CBC_ST_BITS (1) 02312 /* WAIT_CT_READ field */ 02313 #define SECURITY_CONFIG_WAIT_CT_READ (0x00000004u) 02314 #define SECURITY_CONFIG_WAIT_CT_READ_MASK (0x00000004u) 02315 #define SECURITY_CONFIG_WAIT_CT_READ_BIT (2) 02316 #define SECURITY_CONFIG_WAIT_CT_READ_BITS (1) 02317 /* WAIT_PT_WRITE field */ 02318 #define SECURITY_CONFIG_WAIT_PT_WRITE (0x00000002u) 02319 #define SECURITY_CONFIG_WAIT_PT_WRITE_MASK (0x00000002u) 02320 #define SECURITY_CONFIG_WAIT_PT_WRITE_BIT (1) 02321 #define SECURITY_CONFIG_WAIT_PT_WRITE_BITS (1) 02322 /* START_AES field */ 02323 #define SECURITY_CONFIG_START_AES (0x00000001u) 02324 #define SECURITY_CONFIG_START_AES_MASK (0x00000001u) 02325 #define SECURITY_CONFIG_START_AES_BIT (0) 02326 #define SECURITY_CONFIG_START_AES_BITS (1) 02327 02328 #define SECURITY_STATUS *((volatile int32u *)0x40003004u) 02329 #define SECURITY_STATUS_REG *((volatile int32u *)0x40003004u) 02330 #define SECURITY_STATUS_ADDR (0x40003004u) 02331 #define SECURITY_STATUS_RESET (0x00000000u) 02332 /* SEC_BUSY field */ 02333 #define SECURITY_STATUS_SEC_BUSY (0x00000001u) 02334 #define SECURITY_STATUS_SEC_BUSY_MASK (0x00000001u) 02335 #define SECURITY_STATUS_SEC_BUSY_BIT (0) 02336 #define SECURITY_STATUS_SEC_BUSY_BITS (1) 02337 02338 #define CBC_STATE_0 *((volatile int32u *)0x40003008u) 02339 #define CBC_STATE_0_REG *((volatile int32u *)0x40003008u) 02340 #define CBC_STATE_0_ADDR (0x40003008u) 02341 #define CBC_STATE_0_RESET (0x00000000u) 02342 /* CBC_STATE field */ 02343 #define CBC_STATE_0_CBC_STATE (0xFFFFFFFFu) 02344 #define CBC_STATE_0_CBC_STATE_MASK (0xFFFFFFFFu) 02345 #define CBC_STATE_0_CBC_STATE_BIT (0) 02346 #define CBC_STATE_0_CBC_STATE_BITS (32) 02347 02348 #define CBC_STATE_1 *((volatile int32u *)0x4000300Cu) 02349 #define CBC_STATE_1_REG *((volatile int32u *)0x4000300Cu) 02350 #define CBC_STATE_1_ADDR (0x4000300Cu) 02351 #define CBC_STATE_1_RESET (0x00000000u) 02352 /* CBC_STATE_1 field */ 02353 #define CBC_STATE_1_CBC_STATE_1 (0xFFFFFFFFu) 02354 #define CBC_STATE_1_CBC_STATE_1_MASK (0xFFFFFFFFu) 02355 #define CBC_STATE_1_CBC_STATE_1_BIT (0) 02356 #define CBC_STATE_1_CBC_STATE_1_BITS (32) 02357 02358 #define CBC_STATE_2 *((volatile int32u *)0x40003010u) 02359 #define CBC_STATE_2_REG *((volatile int32u *)0x40003010u) 02360 #define CBC_STATE_2_ADDR (0x40003010u) 02361 #define CBC_STATE_2_RESET (0x00000000u) 02362 /* CBC_STATE_2 field */ 02363 #define CBC_STATE_2_CBC_STATE_2 (0xFFFFFFFFu) 02364 #define CBC_STATE_2_CBC_STATE_2_MASK (0xFFFFFFFFu) 02365 #define CBC_STATE_2_CBC_STATE_2_BIT (0) 02366 #define CBC_STATE_2_CBC_STATE_2_BITS (32) 02367 02368 #define CBC_STATE_3 *((volatile int32u *)0x40003014u) 02369 #define CBC_STATE_3_REG *((volatile int32u *)0x40003014u) 02370 #define CBC_STATE_3_ADDR (0x40003014u) 02371 #define CBC_STATE_3_RESET (0x00000000u) 02372 /* CBC_STATE_3 field */ 02373 #define CBC_STATE_3_CBC_STATE_3 (0xFFFFFFFFu) 02374 #define CBC_STATE_3_CBC_STATE_3_MASK (0xFFFFFFFFu) 02375 #define CBC_STATE_3_CBC_STATE_3_BIT (0) 02376 #define CBC_STATE_3_CBC_STATE_3_BITS (32) 02377 02378 #define PT *((volatile int32u *)0x40003028u) 02379 #define PT_REG *((volatile int32u *)0x40003028u) 02380 #define PT_ADDR (0x40003028u) 02381 #define PT_RESET (0x00000000u) 02382 /* PT field */ 02383 #define PT_PT (0xFFFFFFFFu) 02384 #define PT_PT_MASK (0xFFFFFFFFu) 02385 #define PT_PT_BIT (0) 02386 #define PT_PT_BITS (32) 02387 02388 #define CT *((volatile int32u *)0x40003030u) 02389 #define CT_REG *((volatile int32u *)0x40003030u) 02390 #define CT_ADDR (0x40003030u) 02391 #define CT_RESET (0x00000000u) 02392 /* CT field */ 02393 #define CT_CT (0xFFFFFFFFu) 02394 #define CT_CT_MASK (0xFFFFFFFFu) 02395 #define CT_CT_BIT (0) 02396 #define CT_CT_BITS (32) 02397 02398 #define KEY_0 *((volatile int32u *)0x40003038u) 02399 #define KEY_0_REG *((volatile int32u *)0x40003038u) 02400 #define KEY_0_ADDR (0x40003038u) 02401 #define KEY_0_RESET (0x00000000u) 02402 /* KEY_O field */ 02403 #define KEY_0_KEY_O (0xFFFFFFFFu) 02404 #define KEY_0_KEY_O_MASK (0xFFFFFFFFu) 02405 #define KEY_0_KEY_O_BIT (0) 02406 #define KEY_0_KEY_O_BITS (32) 02407 02408 #define KEY_1 *((volatile int32u *)0x4000303Cu) 02409 #define KEY_1_REG *((volatile int32u *)0x4000303Cu) 02410 #define KEY_1_ADDR (0x4000303Cu) 02411 #define KEY_1_RESET (0x00000000u) 02412 /* KEY_1 field */ 02413 #define KEY_1_KEY_1 (0xFFFFFFFFu) 02414 #define KEY_1_KEY_1_MASK (0xFFFFFFFFu) 02415 #define KEY_1_KEY_1_BIT (0) 02416 #define KEY_1_KEY_1_BITS (32) 02417 02418 #define KEY_2 *((volatile int32u *)0x40003040u) 02419 #define KEY_2_REG *((volatile int32u *)0x40003040u) 02420 #define KEY_2_ADDR (0x40003040u) 02421 #define KEY_2_RESET (0x00000000u) 02422 /* KEY_2 field */ 02423 #define KEY_2_KEY_2 (0xFFFFFFFFu) 02424 #define KEY_2_KEY_2_MASK (0xFFFFFFFFu) 02425 #define KEY_2_KEY_2_BIT (0) 02426 #define KEY_2_KEY_2_BITS (32) 02427 02428 #define KEY_3 *((volatile int32u *)0x40003044u) 02429 #define KEY_3_REG *((volatile int32u *)0x40003044u) 02430 #define KEY_3_ADDR (0x40003044u) 02431 #define KEY_3_RESET (0x00000000u) 02432 /* KEY_3 field */ 02433 #define KEY_3_KEY_3 (0xFFFFFFFFu) 02434 #define KEY_3_KEY_3_MASK (0xFFFFFFFFu) 02435 #define KEY_3_KEY_3_BIT (0) 02436 #define KEY_3_KEY_3_BITS (32) 02437 02438 /* CM_LV block */ 02439 #define BLOCK_CM_LV_BASE (0x40004000u) 02440 #define BLOCK_CM_LV_END (0x40004034u) 02441 #define BLOCK_CM_LV_SIZE (BLOCK_CM_LV_END - BLOCK_CM_LV_BASE + 1) 02442 02443 #define SILICON_ID *((volatile int32u *)0x40004000u) 02444 #define SILICON_ID_REG *((volatile int32u *)0x40004000u) 02445 #define SILICON_ID_ADDR (0x40004000u) 02446 #define SILICON_ID_RESET (0x069A862Bu) 02447 /* HW_VERSION field */ 02448 #define SILICON_ID_HW_VERSION (0xF0000000u) 02449 #define SILICON_ID_HW_VERSION_MASK (0xF0000000u) 02450 #define SILICON_ID_HW_VERSION_BIT (28) 02451 #define SILICON_ID_HW_VERSION_BITS (4) 02452 /* ST_DIVISION field */ 02453 #define SILICON_ID_ST_DIVISION (0x0F000000u) 02454 #define SILICON_ID_ST_DIVISION_MASK (0x0F000000u) 02455 #define SILICON_ID_ST_DIVISION_BIT (24) 02456 #define SILICON_ID_ST_DIVISION_BITS (4) 02457 /* CHIP_TYPE field */ 02458 #define SILICON_ID_CHIP_TYPE (0x00FF8000u) 02459 #define SILICON_ID_CHIP_TYPE_MASK (0x00FF8000u) 02460 #define SILICON_ID_CHIP_TYPE_BIT (15) 02461 #define SILICON_ID_CHIP_TYPE_BITS (9) 02462 /* SUB_TYPE field */ 02463 #define SILICON_ID_SUB_TYPE (0x00007000u) 02464 #define SILICON_ID_SUB_TYPE_MASK (0x00007000u) 02465 #define SILICON_ID_SUB_TYPE_BIT (12) 02466 #define SILICON_ID_SUB_TYPE_BITS (3) 02467 /* JEDEC_MAN_ID field */ 02468 #define SILICON_ID_JEDEC_MAN_ID (0x00000FFEu) 02469 #define SILICON_ID_JEDEC_MAN_ID_MASK (0x00000FFEu) 02470 #define SILICON_ID_JEDEC_MAN_ID_BIT (1) 02471 #define SILICON_ID_JEDEC_MAN_ID_BITS (11) 02472 /* ONE field */ 02473 #define SILICON_ID_ONE (0x00000001u) 02474 #define SILICON_ID_ONE_MASK (0x00000001u) 02475 #define SILICON_ID_ONE_BIT (0) 02476 #define SILICON_ID_ONE_BITS (1) 02477 02478 #define OSC24M_BIASTRIM *((volatile int32u *)0x40004004u) 02479 #define OSC24M_BIASTRIM_REG *((volatile int32u *)0x40004004u) 02480 #define OSC24M_BIASTRIM_ADDR (0x40004004u) 02481 #define OSC24M_BIASTRIM_RESET (0x0000000Fu) 02482 /* OSC24M_BIAS_TRIM field */ 02483 #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM (0x0000000Fu) 02484 #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK (0x0000000Fu) 02485 #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT (0) 02486 #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS (4) 02487 02488 #define OSCHF_TUNE *((volatile int32u *)0x40004008u) 02489 #define OSCHF_TUNE_REG *((volatile int32u *)0x40004008u) 02490 #define OSCHF_TUNE_ADDR (0x40004008u) 02491 #define OSCHF_TUNE_RESET (0x00000017u) 02492 /* OSCHF_TUNE_FIELD field */ 02493 #define OSCHF_TUNE_FIELD (0x0000001Fu) 02494 #define OSCHF_TUNE_FIELD_MASK (0x0000001Fu) 02495 #define OSCHF_TUNE_FIELD_BIT (0) 02496 #define OSCHF_TUNE_FIELD_BITS (5) 02497 02498 #define OSC24M_COMP *((volatile int32u *)0x4000400Cu) 02499 #define OSC24M_COMP_REG *((volatile int32u *)0x4000400Cu) 02500 #define OSC24M_COMP_ADDR (0x4000400Cu) 02501 #define OSC24M_COMP_RESET (0x00000000u) 02502 /* OSC24M_HI field */ 02503 #define OSC24M_HI (0x00000002u) 02504 #define OSC24M_HI_MASK (0x00000002u) 02505 #define OSC24M_HI_BIT (1) 02506 #define OSC24M_HI_BITS (1) 02507 /* OSC24M_LO field */ 02508 #define OSC24M_LO (0x00000001u) 02509 #define OSC24M_LO_MASK (0x00000001u) 02510 #define OSC24M_LO_BIT (0) 02511 #define OSC24M_LO_BITS (1) 02512 02513 #define CLK_PERIODMODE *((volatile int32u *)0x40004010u) 02514 #define CLK_PERIODMODE_REG *((volatile int32u *)0x40004010u) 02515 #define CLK_PERIODMODE_ADDR (0x40004010u) 02516 #define CLK_PERIODMODE_RESET (0x00000000u) 02517 /* CLK_PERIODMODE_FIELD field */ 02518 #define CLK_PERIODMODE_FIELD (0x00000003u) 02519 #define CLK_PERIODMODE_FIELD_MASK (0x00000003u) 02520 #define CLK_PERIODMODE_FIELD_BIT (0) 02521 #define CLK_PERIODMODE_FIELD_BITS (2) 02522 02523 #define CLK_PERIOD *((volatile int32u *)0x40004014u) 02524 #define CLK_PERIOD_REG *((volatile int32u *)0x40004014u) 02525 #define CLK_PERIOD_ADDR (0x40004014u) 02526 #define CLK_PERIOD_RESET (0x00000000u) 02527 /* CLK_PERIOD_FIELD field */ 02528 #define CLK_PERIOD_FIELD (0x0000FFFFu) 02529 #define CLK_PERIOD_FIELD_MASK (0x0000FFFFu) 02530 #define CLK_PERIOD_FIELD_BIT (0) 02531 #define CLK_PERIOD_FIELD_BITS (16) 02532 02533 #define DITHER_DIS *((volatile int32u *)0x40004018u) 02534 #define DITHER_DIS_REG *((volatile int32u *)0x40004018u) 02535 #define DITHER_DIS_ADDR (0x40004018u) 02536 #define DITHER_DIS_RESET (0x00000000u) 02537 /* DITHER_DIS field */ 02538 #define DITHER_DIS_DITHER_DIS (0x00000001u) 02539 #define DITHER_DIS_DITHER_DIS_MASK (0x00000001u) 02540 #define DITHER_DIS_DITHER_DIS_BIT (0) 02541 #define DITHER_DIS_DITHER_DIS_BITS (1) 02542 02543 #define OSC24M_CTRL *((volatile int32u *)0x4000401Cu) 02544 #define OSC24M_CTRL_REG *((volatile int32u *)0x4000401Cu) 02545 #define OSC24M_CTRL_ADDR (0x4000401Cu) 02546 #define OSC24M_CTRL_RESET (0x00000000u) 02547 /* OSC24M_EN field */ 02548 #define OSC24M_CTRL_OSC24M_EN (0x00000002u) 02549 #define OSC24M_CTRL_OSC24M_EN_MASK (0x00000002u) 02550 #define OSC24M_CTRL_OSC24M_EN_BIT (1) 02551 #define OSC24M_CTRL_OSC24M_EN_BITS (1) 02552 /* OSC24M_SEL field */ 02553 #define OSC24M_CTRL_OSC24M_SEL (0x00000001u) 02554 #define OSC24M_CTRL_OSC24M_SEL_MASK (0x00000001u) 02555 #define OSC24M_CTRL_OSC24M_SEL_BIT (0) 02556 #define OSC24M_CTRL_OSC24M_SEL_BITS (1) 02557 02558 #define CPU_CLKSEL *((volatile int32u *)0x40004020u) 02559 #define CPU_CLKSEL_REG *((volatile int32u *)0x40004020u) 02560 #define CPU_CLKSEL_ADDR (0x40004020u) 02561 #define CPU_CLKSEL_RESET (0x00000000u) 02562 /* CPU_CLKSEL_FIELD field */ 02563 #define CPU_CLKSEL_FIELD (0x00000001u) 02564 #define CPU_CLKSEL_FIELD_MASK (0x00000001u) 02565 #define CPU_CLKSEL_FIELD_BIT (0) 02566 #define CPU_CLKSEL_FIELD_BITS (1) 02567 02568 #define BUS_FAULT *((volatile int32u *)0x40004024u) 02569 #define BUS_FAULT_REG *((volatile int32u *)0x40004024u) 02570 #define BUS_FAULT_ADDR (0x40004024u) 02571 #define BUS_FAULT_RESET (0x00000000u) 02572 /* WRONGSIZE field */ 02573 #define BUS_FAULT_WRONGSIZE (0x00000008u) 02574 #define BUS_FAULT_WRONGSIZE_MASK (0x00000008u) 02575 #define BUS_FAULT_WRONGSIZE_BIT (3) 02576 #define BUS_FAULT_WRONGSIZE_BITS (1) 02577 /* PROTECTED field */ 02578 #define BUS_FAULT_PROTECTED (0x00000004u) 02579 #define BUS_FAULT_PROTECTED_MASK (0x00000004u) 02580 #define BUS_FAULT_PROTECTED_BIT (2) 02581 #define BUS_FAULT_PROTECTED_BITS (1) 02582 /* RESERVED field */ 02583 #define BUS_FAULT_RESERVED (0x00000002u) 02584 #define BUS_FAULT_RESERVED_MASK (0x00000002u) 02585 #define BUS_FAULT_RESERVED_BIT (1) 02586 #define BUS_FAULT_RESERVED_BITS (1) 02587 /* MISSED field */ 02588 #define BUS_FAULT_MISSED (0x00000001u) 02589 #define BUS_FAULT_MISSED_MASK (0x00000001u) 02590 #define BUS_FAULT_MISSED_BIT (0) 02591 #define BUS_FAULT_MISSED_BITS (1) 02592 02593 #define PCTRACE_SEL *((volatile int32u *)0x40004028u) 02594 #define PCTRACE_SEL_REG *((volatile int32u *)0x40004028u) 02595 #define PCTRACE_SEL_ADDR (0x40004028u) 02596 #define PCTRACE_SEL_RESET (0x00000000u) 02597 /* PCTRACE_SEL_FIELD field */ 02598 #define PCTRACE_SEL_FIELD (0x00000001u) 02599 #define PCTRACE_SEL_FIELD_MASK (0x00000001u) 02600 #define PCTRACE_SEL_FIELD_BIT (0) 02601 #define PCTRACE_SEL_FIELD_BITS (1) 02602 02603 #define FPEC_CLKREQ *((volatile int32u *)0x4000402Cu) 02604 #define FPEC_CLKREQ_REG *((volatile int32u *)0x4000402Cu) 02605 #define FPEC_CLKREQ_ADDR (0x4000402Cu) 02606 #define FPEC_CLKREQ_RESET (0x00000000u) 02607 /* FPEC_CLKREQ_FIELD field */ 02608 #define FPEC_CLKREQ_FIELD (0x00000001u) 02609 #define FPEC_CLKREQ_FIELD_MASK (0x00000001u) 02610 #define FPEC_CLKREQ_FIELD_BIT (0) 02611 #define FPEC_CLKREQ_FIELD_BITS (1) 02612 02613 #define FPEC_CLKSTAT *((volatile int32u *)0x40004030u) 02614 #define FPEC_CLKSTAT_REG *((volatile int32u *)0x40004030u) 02615 #define FPEC_CLKSTAT_ADDR (0x40004030u) 02616 #define FPEC_CLKSTAT_RESET (0x00000000u) 02617 /* FPEC_CLKBSY field */ 02618 #define FPEC_CLKBSY (0x00000002u) 02619 #define FPEC_CLKBSY_MASK (0x00000002u) 02620 #define FPEC_CLKBSY_BIT (1) 02621 #define FPEC_CLKBSY_BITS (1) 02622 /* FPEC_CLKACK field */ 02623 #define FPEC_CLKACK (0x00000001u) 02624 #define FPEC_CLKACK_MASK (0x00000001u) 02625 #define FPEC_CLKACK_BIT (0) 02626 #define FPEC_CLKACK_BITS (1) 02627 02628 #define LV_SPARE *((volatile int32u *)0x40004034u) 02629 #define LV_SPARE_REG *((volatile int32u *)0x40004034u) 02630 #define LV_SPARE_ADDR (0x40004034u) 02631 #define LV_SPARE_RESET (0x00000000u) 02632 /* LV_SPARE field */ 02633 #define LV_SPARE_LV_SPARE (0x000000FFu) 02634 #define LV_SPARE_LV_SPARE_MASK (0x000000FFu) 02635 #define LV_SPARE_LV_SPARE_BIT (0) 02636 #define LV_SPARE_LV_SPARE_BITS (8) 02637 02638 /* RAM_CTRL block */ 02639 #define DATA_RAM_CTRL_BASE (0x40005000u) 02640 #define DATA_RAM_CTRL_END (0x40005028u) 02641 #define DATA_RAM_CTRL_SIZE (DATA_RAM_CTRL_END - DATA_RAM_CTRL_BASE + 1) 02642 02643 #define MEM_PROT_0 *((volatile int32u *)0x40005000u) 02644 #define MEM_PROT_0_REG *((volatile int32u *)0x40005000u) 02645 #define MEM_PROT_0_ADDR (0x40005000u) 02646 #define MEM_PROT_0_RESET (0x00000000u) 02647 /* MEM_PROT_0 field */ 02648 #define MEM_PROT_0_MEM_PROT_0 (0xFFFFFFFFu) 02649 #define MEM_PROT_0_MEM_PROT_0_MASK (0xFFFFFFFFu) 02650 #define MEM_PROT_0_MEM_PROT_0_BIT (0) 02651 #define MEM_PROT_0_MEM_PROT_0_BITS (32) 02652 02653 #define MEM_PROT_1 *((volatile int32u *)0x40005004u) 02654 #define MEM_PROT_1_REG *((volatile int32u *)0x40005004u) 02655 #define MEM_PROT_1_ADDR (0x40005004u) 02656 #define MEM_PROT_1_RESET (0x00000000u) 02657 /* MEM_PROT_1 field */ 02658 #define MEM_PROT_1_MEM_PROT_1 (0xFFFFFFFFu) 02659 #define MEM_PROT_1_MEM_PROT_1_MASK (0xFFFFFFFFu) 02660 #define MEM_PROT_1_MEM_PROT_1_BIT (0) 02661 #define MEM_PROT_1_MEM_PROT_1_BITS (32) 02662 02663 #define MEM_PROT_2 *((volatile int32u *)0x40005008u) 02664 #define MEM_PROT_2_REG *((volatile int32u *)0x40005008u) 02665 #define MEM_PROT_2_ADDR (0x40005008u) 02666 #define MEM_PROT_2_RESET (0x00000000u) 02667 /* MEM_PROT_2 field */ 02668 #define MEM_PROT_2_MEM_PROT_2 (0xFFFFFFFFu) 02669 #define MEM_PROT_2_MEM_PROT_2_MASK (0xFFFFFFFFu) 02670 #define MEM_PROT_2_MEM_PROT_2_BIT (0) 02671 #define MEM_PROT_2_MEM_PROT_2_BITS (32) 02672 02673 #define MEM_PROT_3 *((volatile int32u *)0x4000500Cu) 02674 #define MEM_PROT_3_REG *((volatile int32u *)0x4000500Cu) 02675 #define MEM_PROT_3_ADDR (0x4000500Cu) 02676 #define MEM_PROT_3_RESET (0x00000000u) 02677 /* MEM_PROT_3 field */ 02678 #define MEM_PROT_3_MEM_PROT_3 (0xFFFFFFFFu) 02679 #define MEM_PROT_3_MEM_PROT_3_MASK (0xFFFFFFFFu) 02680 #define MEM_PROT_3_MEM_PROT_3_BIT (0) 02681 #define MEM_PROT_3_MEM_PROT_3_BITS (32) 02682 02683 #define MEM_PROT_4 *((volatile int32u *)0x40005010u) 02684 #define MEM_PROT_4_REG *((volatile int32u *)0x40005010u) 02685 #define MEM_PROT_4_ADDR (0x40005010u) 02686 #define MEM_PROT_4_RESET (0x00000000u) 02687 /* MEM_PROT_4 field */ 02688 #define MEM_PROT_4_MEM_PROT_4 (0xFFFFFFFFu) 02689 #define MEM_PROT_4_MEM_PROT_4_MASK (0xFFFFFFFFu) 02690 #define MEM_PROT_4_MEM_PROT_4_BIT (0) 02691 #define MEM_PROT_4_MEM_PROT_4_BITS (32) 02692 02693 #define MEM_PROT_5 *((volatile int32u *)0x40005014u) 02694 #define MEM_PROT_5_REG *((volatile int32u *)0x40005014u) 02695 #define MEM_PROT_5_ADDR (0x40005014u) 02696 #define MEM_PROT_5_RESET (0x00000000u) 02697 /* MEM_PROT_5 field */ 02698 #define MEM_PROT_5_MEM_PROT_5 (0xFFFFFFFFu) 02699 #define MEM_PROT_5_MEM_PROT_5_MASK (0xFFFFFFFFu) 02700 #define MEM_PROT_5_MEM_PROT_5_BIT (0) 02701 #define MEM_PROT_5_MEM_PROT_5_BITS (32) 02702 02703 #define MEM_PROT_6 *((volatile int32u *)0x40005018u) 02704 #define MEM_PROT_6_REG *((volatile int32u *)0x40005018u) 02705 #define MEM_PROT_6_ADDR (0x40005018u) 02706 #define MEM_PROT_6_RESET (0x00000000u) 02707 /* MEM_PROT_6 field */ 02708 #define MEM_PROT_6_MEM_PROT_6 (0xFFFFFFFFu) 02709 #define MEM_PROT_6_MEM_PROT_6_MASK (0xFFFFFFFFu) 02710 #define MEM_PROT_6_MEM_PROT_6_BIT (0) 02711 #define MEM_PROT_6_MEM_PROT_6_BITS (32) 02712 02713 #define MEM_PROT_7 *((volatile int32u *)0x4000501Cu) 02714 #define MEM_PROT_7_REG *((volatile int32u *)0x4000501Cu) 02715 #define MEM_PROT_7_ADDR (0x4000501Cu) 02716 #define MEM_PROT_7_RESET (0x00000000u) 02717 /* MEM_PROT_7 field */ 02718 #define MEM_PROT_7_MEM_PROT_7 (0xFFFFFFFFu) 02719 #define MEM_PROT_7_MEM_PROT_7_MASK (0xFFFFFFFFu) 02720 #define MEM_PROT_7_MEM_PROT_7_BIT (0) 02721 #define MEM_PROT_7_MEM_PROT_7_BITS (32) 02722 02723 #define DMA_PROT_ADDR *((volatile int32u *)0x40005020u) 02724 #define DMA_PROT_ADDR_REG *((volatile int32u *)0x40005020u) 02725 #define DMA_PROT_ADDR_ADDR (0x40005020u) 02726 #define DMA_PROT_ADDR_RESET (0x20000000u) 02727 /* DMA_PROT_OFFS field */ 02728 #define DMA_PROT_ADDR_DMA_PROT_OFFS (0xFFFFE000u) 02729 #define DMA_PROT_ADDR_DMA_PROT_OFFS_MASK (0xFFFFE000u) 02730 #define DMA_PROT_ADDR_DMA_PROT_OFFS_BIT (13) 02731 #define DMA_PROT_ADDR_DMA_PROT_OFFS_BITS (19) 02732 /* DMA_PROT_ADDR field */ 02733 #define DMA_PROT_ADDR_DMA_PROT_ADDR (0x00001FFFu) 02734 #define DMA_PROT_ADDR_DMA_PROT_ADDR_MASK (0x00001FFFu) 02735 #define DMA_PROT_ADDR_DMA_PROT_ADDR_BIT (0) 02736 #define DMA_PROT_ADDR_DMA_PROT_ADDR_BITS (13) 02737 02738 #define DMA_PROT_CH *((volatile int32u *)0x40005024u) 02739 #define DMA_PROT_CH_REG *((volatile int32u *)0x40005024u) 02740 #define DMA_PROT_CH_ADDR (0x40005024u) 02741 #define DMA_PROT_CH_RESET (0x00000000u) 02742 /* DMA_PROT_CH field */ 02743 #define DMA_PROT_CH_DMA_PROT_CH (0x00000007u) 02744 #define DMA_PROT_CH_DMA_PROT_CH_MASK (0x00000007u) 02745 #define DMA_PROT_CH_DMA_PROT_CH_BIT (0) 02746 #define DMA_PROT_CH_DMA_PROT_CH_BITS (3) 02747 02748 #define MEM_PROT_EN *((volatile int32u *)0x40005028u) 02749 #define MEM_PROT_EN_REG *((volatile int32u *)0x40005028u) 02750 #define MEM_PROT_EN_ADDR (0x40005028u) 02751 #define MEM_PROT_EN_RESET (0x00000000u) 02752 /* FORCE_PROT field */ 02753 #define MEM_PROT_EN_FORCE_PROT (0x00000004u) 02754 #define MEM_PROT_EN_FORCE_PROT_MASK (0x00000004u) 02755 #define MEM_PROT_EN_FORCE_PROT_BIT (2) 02756 #define MEM_PROT_EN_FORCE_PROT_BITS (1) 02757 /* DMA_PROT_EN_MAC field */ 02758 #define MEM_PROT_EN_DMA_PROT_EN_MAC (0x00000002u) 02759 #define MEM_PROT_EN_DMA_PROT_EN_MAC_MASK (0x00000002u) 02760 #define MEM_PROT_EN_DMA_PROT_EN_MAC_BIT (1) 02761 #define MEM_PROT_EN_DMA_PROT_EN_MAC_BITS (1) 02762 /* DMA_PROT_EN_OTHER field */ 02763 #define MEM_PROT_EN_DMA_PROT_EN_OTHER (0x00000001u) 02764 #define MEM_PROT_EN_DMA_PROT_EN_OTHER_MASK (0x00000001u) 02765 #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BIT (0) 02766 #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BITS (1) 02767 02768 /* SLOW_TIMERS block */ 02769 #define DATA_SLOW_TIMERS_BASE (0x40006000u) 02770 #define DATA_SLOW_TIMERS_END (0x40006024u) 02771 #define DATA_SLOW_TIMERS_SIZE (DATA_SLOW_TIMERS_END - DATA_SLOW_TIMERS_BASE + 1) 02772 02773 #define WDOG_CFG *((volatile int32u *)0x40006000u) 02774 #define WDOG_CFG_REG *((volatile int32u *)0x40006000u) 02775 #define WDOG_CFG_ADDR (0x40006000u) 02776 #define WDOG_CFG_RESET (0x00000002u) 02777 /* WDOG_DISABLE field */ 02778 #define WDOG_DISABLE (0x00000002u) 02779 #define WDOG_DISABLE_MASK (0x00000002u) 02780 #define WDOG_DISABLE_BIT (1) 02781 #define WDOG_DISABLE_BITS (1) 02782 /* WDOG_ENABLE field */ 02783 #define WDOG_ENABLE (0x00000001u) 02784 #define WDOG_ENABLE_MASK (0x00000001u) 02785 #define WDOG_ENABLE_BIT (0) 02786 #define WDOG_ENABLE_BITS (1) 02787 02788 #define WDOG_KEY *((volatile int32u *)0x40006004u) 02789 #define WDOG_KEY_REG *((volatile int32u *)0x40006004u) 02790 #define WDOG_KEY_ADDR (0x40006004u) 02791 #define WDOG_KEY_RESET (0x00000000u) 02792 /* WDOG_KEY_FIELD field */ 02793 #define WDOG_KEY_FIELD (0x0000FFFFu) 02794 #define WDOG_KEY_FIELD_MASK (0x0000FFFFu) 02795 #define WDOG_KEY_FIELD_BIT (0) 02796 #define WDOG_KEY_FIELD_BITS (16) 02797 02798 #define WDOG_RESET *((volatile int32u *)0x40006008u) 02799 #define WDOG_RESET_REG *((volatile int32u *)0x40006008u) 02800 #define WDOG_RESET_ADDR (0x40006008u) 02801 #define WDOG_RESET_RESET (0x00000000u) 02802 02803 #define SLEEPTMR_CFG *((volatile int32u *)0x4000600Cu) 02804 #define SLEEPTMR_CFG_REG *((volatile int32u *)0x4000600Cu) 02805 #define SLEEPTMR_CFG_ADDR (0x4000600Cu) 02806 #define SLEEPTMR_CFG_RESET (0x00000400u) 02807 /* SLEEPTMR_REVERSE field */ 02808 #define SLEEPTMR_REVERSE (0x00001000u) 02809 #define SLEEPTMR_REVERSE_MASK (0x00001000u) 02810 #define SLEEPTMR_REVERSE_BIT (12) 02811 #define SLEEPTMR_REVERSE_BITS (1) 02812 /* SLEEPTMR_ENABLE field */ 02813 #define SLEEPTMR_ENABLE (0x00000800u) 02814 #define SLEEPTMR_ENABLE_MASK (0x00000800u) 02815 #define SLEEPTMR_ENABLE_BIT (11) 02816 #define SLEEPTMR_ENABLE_BITS (1) 02817 /* SLEEPTMR_DBGPAUSE field */ 02818 #define SLEEPTMR_DBGPAUSE (0x00000400u) 02819 #define SLEEPTMR_DBGPAUSE_MASK (0x00000400u) 02820 #define SLEEPTMR_DBGPAUSE_BIT (10) 02821 #define SLEEPTMR_DBGPAUSE_BITS (1) 02822 /* SLEEPTMR_CLKDIV field */ 02823 #define SLEEPTMR_CLKDIV (0x000000F0u) 02824 #define SLEEPTMR_CLKDIV_MASK (0x000000F0u) 02825 #define SLEEPTMR_CLKDIV_BIT (4) 02826 #define SLEEPTMR_CLKDIV_BITS (4) 02827 /* SLEEPTMR_CLKSEL field */ 02828 #define SLEEPTMR_CLKSEL (0x00000001u) 02829 #define SLEEPTMR_CLKSEL_MASK (0x00000001u) 02830 #define SLEEPTMR_CLKSEL_BIT (0) 02831 #define SLEEPTMR_CLKSEL_BITS (1) 02832 02833 #define SLEEPTMR_CNTH *((volatile int32u *)0x40006010u) 02834 #define SLEEPTMR_CNTH_REG *((volatile int32u *)0x40006010u) 02835 #define SLEEPTMR_CNTH_ADDR (0x40006010u) 02836 #define SLEEPTMR_CNTH_RESET (0x00000000u) 02837 /* SLEEPTMR_CNTH_FIELD field */ 02838 #define SLEEPTMR_CNTH_FIELD (0x0000FFFFu) 02839 #define SLEEPTMR_CNTH_FIELD_MASK (0x0000FFFFu) 02840 #define SLEEPTMR_CNTH_FIELD_BIT (0) 02841 #define SLEEPTMR_CNTH_FIELD_BITS (16) 02842 02843 #define SLEEPTMR_CNTL *((volatile int32u *)0x40006014u) 02844 #define SLEEPTMR_CNTL_REG *((volatile int32u *)0x40006014u) 02845 #define SLEEPTMR_CNTL_ADDR (0x40006014u) 02846 #define SLEEPTMR_CNTL_RESET (0x00000000u) 02847 /* SLEEPTMR_CNTL_FIELD field */ 02848 #define SLEEPTMR_CNTL_FIELD (0x0000FFFFu) 02849 #define SLEEPTMR_CNTL_FIELD_MASK (0x0000FFFFu) 02850 #define SLEEPTMR_CNTL_FIELD_BIT (0) 02851 #define SLEEPTMR_CNTL_FIELD_BITS (16) 02852 02853 #define SLEEPTMR_CMPAH *((volatile int32u *)0x40006018u) 02854 #define SLEEPTMR_CMPAH_REG *((volatile int32u *)0x40006018u) 02855 #define SLEEPTMR_CMPAH_ADDR (0x40006018u) 02856 #define SLEEPTMR_CMPAH_RESET (0x0000FFFFu) 02857 /* SLEEPTMR_CMPAH_FIELD field */ 02858 #define SLEEPTMR_CMPAH_FIELD (0x0000FFFFu) 02859 #define SLEEPTMR_CMPAH_FIELD_MASK (0x0000FFFFu) 02860 #define SLEEPTMR_CMPAH_FIELD_BIT (0) 02861 #define SLEEPTMR_CMPAH_FIELD_BITS (16) 02862 02863 #define SLEEPTMR_CMPAL *((volatile int32u *)0x4000601Cu) 02864 #define SLEEPTMR_CMPAL_REG *((volatile int32u *)0x4000601Cu) 02865 #define SLEEPTMR_CMPAL_ADDR (0x4000601Cu) 02866 #define SLEEPTMR_CMPAL_RESET (0x0000FFFFu) 02867 /* SLEEPTMR_CMPAL_FIELD field */ 02868 #define SLEEPTMR_CMPAL_FIELD (0x0000FFFFu) 02869 #define SLEEPTMR_CMPAL_FIELD_MASK (0x0000FFFFu) 02870 #define SLEEPTMR_CMPAL_FIELD_BIT (0) 02871 #define SLEEPTMR_CMPAL_FIELD_BITS (16) 02872 02873 #define SLEEPTMR_CMPBH *((volatile int32u *)0x40006020u) 02874 #define SLEEPTMR_CMPBH_REG *((volatile int32u *)0x40006020u) 02875 #define SLEEPTMR_CMPBH_ADDR (0x40006020u) 02876 #define SLEEPTMR_CMPBH_RESET (0x0000FFFFu) 02877 /* SLEEPTMR_CMPBH_FIELD field */ 02878 #define SLEEPTMR_CMPBH_FIELD (0x0000FFFFu) 02879 #define SLEEPTMR_CMPBH_FIELD_MASK (0x0000FFFFu) 02880 #define SLEEPTMR_CMPBH_FIELD_BIT (0) 02881 #define SLEEPTMR_CMPBH_FIELD_BITS (16) 02882 02883 #define SLEEPTMR_CMPBL *((volatile int32u *)0x40006024u) 02884 #define SLEEPTMR_CMPBL_REG *((volatile int32u *)0x40006024u) 02885 #define SLEEPTMR_CMPBL_ADDR (0x40006024u) 02886 #define SLEEPTMR_CMPBL_RESET (0x0000FFFFu) 02887 /* SLEEPTMR_CMPBL_FIELD field */ 02888 #define SLEEPTMR_CMPBL_FIELD (0x0000FFFFu) 02889 #define SLEEPTMR_CMPBL_FIELD_MASK (0x0000FFFFu) 02890 #define SLEEPTMR_CMPBL_FIELD_BIT (0) 02891 #define SLEEPTMR_CMPBL_FIELD_BITS (16) 02892 02893 /* CAL_ADC block */ 02894 #define DATA_CAL_ADC_BASE (0x40007000u) 02895 #define DATA_CAL_ADC_END (0x40007004u) 02896 #define DATA_CAL_ADC_SIZE (DATA_CAL_ADC_END - DATA_CAL_ADC_BASE + 1) 02897 02898 #define CAL_ADC_DATA *((volatile int32u *)0x40007000u) 02899 #define CAL_ADC_DATA_REG *((volatile int32u *)0x40007000u) 02900 #define CAL_ADC_DATA_ADDR (0x40007000u) 02901 #define CAL_ADC_DATA_RESET (0x00000000u) 02902 /* CAL_ADC_DATA field */ 02903 #define CAL_ADC_DATA_CAL_ADC_DATA (0x0000FFFFu) 02904 #define CAL_ADC_DATA_CAL_ADC_DATA_MASK (0x0000FFFFu) 02905 #define CAL_ADC_DATA_CAL_ADC_DATA_BIT (0) 02906 #define CAL_ADC_DATA_CAL_ADC_DATA_BITS (16) 02907 02908 #define CAL_ADC_CONFIG *((volatile int32u *)0x40007004u) 02909 #define CAL_ADC_CONFIG_REG *((volatile int32u *)0x40007004u) 02910 #define CAL_ADC_CONFIG_ADDR (0x40007004u) 02911 #define CAL_ADC_CONFIG_RESET (0x00000000u) 02912 /* CAL_ADC_RATE field */ 02913 #define CAL_ADC_CONFIG_CAL_ADC_RATE (0x00007000u) 02914 #define CAL_ADC_CONFIG_CAL_ADC_RATE_MASK (0x00007000u) 02915 #define CAL_ADC_CONFIG_CAL_ADC_RATE_BIT (12) 02916 #define CAL_ADC_CONFIG_CAL_ADC_RATE_BITS (3) 02917 /* CAL_ADC_MUX field */ 02918 #define CAL_ADC_CONFIG_CAL_ADC_MUX (0x00000F80u) 02919 #define CAL_ADC_CONFIG_CAL_ADC_MUX_MASK (0x00000F80u) 02920 #define CAL_ADC_CONFIG_CAL_ADC_MUX_BIT (7) 02921 #define CAL_ADC_CONFIG_CAL_ADC_MUX_BITS (5) 02922 /* CAL_ADC_CLKSEL field */ 02923 #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL (0x00000004u) 02924 #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_MASK (0x00000004u) 02925 #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT (2) 02926 #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BITS (1) 02927 /* CAL_ADC_DITHER_DIS field */ 02928 #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS (0x00000002u) 02929 #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_MASK (0x00000002u) 02930 #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BIT (1) 02931 #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BITS (1) 02932 /* CAL_ADC_EN field */ 02933 #define CAL_ADC_CONFIG_CAL_ADC_EN (0x00000001u) 02934 #define CAL_ADC_CONFIG_CAL_ADC_EN_MASK (0x00000001u) 02935 #define CAL_ADC_CONFIG_CAL_ADC_EN_BIT (0) 02936 #define CAL_ADC_CONFIG_CAL_ADC_EN_BITS (1) 02937 02938 /* FLASH_CONTROL block */ 02939 #define DATA_FLASH_CONTROL_BASE (0x40008000u) 02940 #define DATA_FLASH_CONTROL_END (0x40008084u) 02941 #define DATA_FLASH_CONTROL_SIZE (DATA_FLASH_CONTROL_END - DATA_FLASH_CONTROL_BASE + 1) 02942 02943 #define FLASH_ACCESS *((volatile int32u *)0x40008000u) 02944 #define FLASH_ACCESS_REG *((volatile int32u *)0x40008000u) 02945 #define FLASH_ACCESS_ADDR (0x40008000u) 02946 #define FLASH_ACCESS_RESET (0x00000031u) 02947 /* PREFETCH_STATUS field */ 02948 #define FLASH_ACCESS_PREFETCH_STATUS (0x00000020u) 02949 #define FLASH_ACCESS_PREFETCH_STATUS_MASK (0x00000020u) 02950 #define FLASH_ACCESS_PREFETCH_STATUS_BIT (5) 02951 #define FLASH_ACCESS_PREFETCH_STATUS_BITS (1) 02952 /* PREFETCH_EN field */ 02953 #define FLASH_ACCESS_PREFETCH_EN (0x00000010u) 02954 #define FLASH_ACCESS_PREFETCH_EN_MASK (0x00000010u) 02955 #define FLASH_ACCESS_PREFETCH_EN_BIT (4) 02956 #define FLASH_ACCESS_PREFETCH_EN_BITS (1) 02957 /* HALFCYCLE_ACCESS field */ 02958 #define FLASH_ACCESS_HALFCYCLE_ACCESS (0x00000008u) 02959 #define FLASH_ACCESS_HALFCYCLE_ACCESS_MASK (0x00000008u) 02960 #define FLASH_ACCESS_HALFCYCLE_ACCESS_BIT (3) 02961 #define FLASH_ACCESS_HALFCYCLE_ACCESS_BITS (1) 02962 /* CODE_LATENCY field */ 02963 #define FLASH_ACCESS_CODE_LATENCY (0x00000007u) 02964 #define FLASH_ACCESS_CODE_LATENCY_MASK (0x00000007u) 02965 #define FLASH_ACCESS_CODE_LATENCY_BIT (0) 02966 #define FLASH_ACCESS_CODE_LATENCY_BITS (3) 02967 02968 #define FPEC_KEY *((volatile int32u *)0x40008004u) 02969 #define FPEC_KEY_REG *((volatile int32u *)0x40008004u) 02970 #define FPEC_KEY_ADDR (0x40008004u) 02971 #define FPEC_KEY_RESET (0x00000000u) 02972 /* FKEYR field */ 02973 #define FPEC_KEY_FKEYR (0xFFFFFFFFu) 02974 #define FPEC_KEY_FKEYR_MASK (0xFFFFFFFFu) 02975 #define FPEC_KEY_FKEYR_BIT (0) 02976 #define FPEC_KEY_FKEYR_BITS (32) 02977 02978 #define OPT_KEY *((volatile int32u *)0x40008008u) 02979 #define OPT_KEY_REG *((volatile int32u *)0x40008008u) 02980 #define OPT_KEY_ADDR (0x40008008u) 02981 #define OPT_KEY_RESET (0x00000000u) 02982 /* OPTKEYR field */ 02983 #define OPT_KEY_OPTKEYR (0xFFFFFFFFu) 02984 #define OPT_KEY_OPTKEYR_MASK (0xFFFFFFFFu) 02985 #define OPT_KEY_OPTKEYR_BIT (0) 02986 #define OPT_KEY_OPTKEYR_BITS (32) 02987 02988 #define FLASH_STATUS *((volatile int32u *)0x4000800Cu) 02989 #define FLASH_STATUS_REG *((volatile int32u *)0x4000800Cu) 02990 #define FLASH_STATUS_ADDR (0x4000800Cu) 02991 #define FLASH_STATUS_RESET (0x00000000u) 02992 /* EOP field */ 02993 #define FLASH_STATUS_EOP (0x00000020u) 02994 #define FLASH_STATUS_EOP_MASK (0x00000020u) 02995 #define FLASH_STATUS_EOP_BIT (5) 02996 #define FLASH_STATUS_EOP_BITS (1) 02997 /* WRP_ERR field */ 02998 #define FLASH_STATUS_WRP_ERR (0x00000010u) 02999 #define FLASH_STATUS_WRP_ERR_MASK (0x00000010u) 03000 #define FLASH_STATUS_WRP_ERR_BIT (4) 03001 #define FLASH_STATUS_WRP_ERR_BITS (1) 03002 /* PAGE_PROG_ERR field */ 03003 #define FLASH_STATUS_PAGE_PROG_ERR (0x00000008u) 03004 #define FLASH_STATUS_PAGE_PROG_ERR_MASK (0x00000008u) 03005 #define FLASH_STATUS_PAGE_PROG_ERR_BIT (3) 03006 #define FLASH_STATUS_PAGE_PROG_ERR_BITS (1) 03007 /* PROG_ERR field */ 03008 #define FLASH_STATUS_PROG_ERR (0x00000004u) 03009 #define FLASH_STATUS_PROG_ERR_MASK (0x00000004u) 03010 #define FLASH_STATUS_PROG_ERR_BIT (2) 03011 #define FLASH_STATUS_PROG_ERR_BITS (1) 03012 /* EARLY_BSY field */ 03013 #define FLASH_STATUS_EARLY_BSY (0x00000002u) 03014 #define FLASH_STATUS_EARLY_BSY_MASK (0x00000002u) 03015 #define FLASH_STATUS_EARLY_BSY_BIT (1) 03016 #define FLASH_STATUS_EARLY_BSY_BITS (1) 03017 /* FLA_BSY field */ 03018 #define FLASH_STATUS_FLA_BSY (0x00000001u) 03019 #define FLASH_STATUS_FLA_BSY_MASK (0x00000001u) 03020 #define FLASH_STATUS_FLA_BSY_BIT (0) 03021 #define FLASH_STATUS_FLA_BSY_BITS (1) 03022 03023 #define FLASH_CTRL *((volatile int32u *)0x40008010u) 03024 #define FLASH_CTRL_REG *((volatile int32u *)0x40008010u) 03025 #define FLASH_CTRL_ADDR (0x40008010u) 03026 #define FLASH_CTRL_RESET (0x00000080u) 03027 /* EOPIE field */ 03028 #define FLASH_CTRL_EOPIE (0x00001000u) 03029 #define FLASH_CTRL_EOPIE_MASK (0x00001000u) 03030 #define FLASH_CTRL_EOPIE_BIT (12) 03031 #define FLASH_CTRL_EOPIE_BITS (1) 03032 /* EARLYBSYIE field */ 03033 #define FLASH_CTRL_EARLYBSYIE (0x00000800u) 03034 #define FLASH_CTRL_EARLYBSYIE_MASK (0x00000800u) 03035 #define FLASH_CTRL_EARLYBSYIE_BIT (11) 03036 #define FLASH_CTRL_EARLYBSYIE_BITS (1) 03037 /* ERRIE field */ 03038 #define FLASH_CTRL_ERRIE (0x00000400u) 03039 #define FLASH_CTRL_ERRIE_MASK (0x00000400u) 03040 #define FLASH_CTRL_ERRIE_BIT (10) 03041 #define FLASH_CTRL_ERRIE_BITS (1) 03042 /* OPTWREN field */ 03043 #define FLASH_CTRL_OPTWREN (0x00000200u) 03044 #define FLASH_CTRL_OPTWREN_MASK (0x00000200u) 03045 #define FLASH_CTRL_OPTWREN_BIT (9) 03046 #define FLASH_CTRL_OPTWREN_BITS (1) 03047 /* FSTPROG field */ 03048 #define FLASH_CTRL_FSTPROG (0x00000100u) 03049 #define FLASH_CTRL_FSTPROG_MASK (0x00000100u) 03050 #define FLASH_CTRL_FSTPROG_BIT (8) 03051 #define FLASH_CTRL_FSTPROG_BITS (1) 03052 /* LOCK field */ 03053 #define FLASH_CTRL_LOCK (0x00000080u) 03054 #define FLASH_CTRL_LOCK_MASK (0x00000080u) 03055 #define FLASH_CTRL_LOCK_BIT (7) 03056 #define FLASH_CTRL_LOCK_BITS (1) 03057 /* FLA_START field */ 03058 #define FLASH_CTRL_FLA_START (0x00000040u) 03059 #define FLASH_CTRL_FLA_START_MASK (0x00000040u) 03060 #define FLASH_CTRL_FLA_START_BIT (6) 03061 #define FLASH_CTRL_FLA_START_BITS (1) 03062 /* OPTERASE field */ 03063 #define FLASH_CTRL_OPTERASE (0x00000020u) 03064 #define FLASH_CTRL_OPTERASE_MASK (0x00000020u) 03065 #define FLASH_CTRL_OPTERASE_BIT (5) 03066 #define FLASH_CTRL_OPTERASE_BITS (1) 03067 /* OPTPROG field */ 03068 #define FLASH_CTRL_OPTPROG (0x00000010u) 03069 #define FLASH_CTRL_OPTPROG_MASK (0x00000010u) 03070 #define FLASH_CTRL_OPTPROG_BIT (4) 03071 #define FLASH_CTRL_OPTPROG_BITS (1) 03072 /* GLOBALERASE field */ 03073 #define FLASH_CTRL_GLOBALERASE (0x00000008u) 03074 #define FLASH_CTRL_GLOBALERASE_MASK (0x00000008u) 03075 #define FLASH_CTRL_GLOBALERASE_BIT (3) 03076 #define FLASH_CTRL_GLOBALERASE_BITS (1) 03077 /* MASSERASE field */ 03078 #define FLASH_CTRL_MASSERASE (0x00000004u) 03079 #define FLASH_CTRL_MASSERASE_MASK (0x00000004u) 03080 #define FLASH_CTRL_MASSERASE_BIT (2) 03081 #define FLASH_CTRL_MASSERASE_BITS (1) 03082 /* PAGEERASE field */ 03083 #define FLASH_CTRL_PAGEERASE (0x00000002u) 03084 #define FLASH_CTRL_PAGEERASE_MASK (0x00000002u) 03085 #define FLASH_CTRL_PAGEERASE_BIT (1) 03086 #define FLASH_CTRL_PAGEERASE_BITS (1) 03087 /* PROG field */ 03088 #define FLASH_CTRL_PROG (0x00000001u) 03089 #define FLASH_CTRL_PROG_MASK (0x00000001u) 03090 #define FLASH_CTRL_PROG_BIT (0) 03091 #define FLASH_CTRL_PROG_BITS (1) 03092 03093 #define FLASH_ADDR *((volatile int32u *)0x40008014u) 03094 #define FLASH_ADDR_REG *((volatile int32u *)0x40008014u) 03095 #define FLASH_ADDR_ADDR (0x40008014u) 03096 #define FLASH_ADDR_RESET (0x00000000u) 03097 /* FAR field */ 03098 #define FLASH_ADDR_FAR (0xFFFFFFFFu) 03099 #define FLASH_ADDR_FAR_MASK (0xFFFFFFFFu) 03100 #define FLASH_ADDR_FAR_BIT (0) 03101 #define FLASH_ADDR_FAR_BITS (32) 03102 03103 #define OPT_BYTE *((volatile int32u *)0x4000801Cu) 03104 #define OPT_BYTE_REG *((volatile int32u *)0x4000801Cu) 03105 #define OPT_BYTE_ADDR (0x4000801Cu) 03106 #define OPT_BYTE_RESET (0xFBFFFFFEu) 03107 /* RSVD field */ 03108 #define OPT_BYTE_RSVD (0xF8000000u) 03109 #define OPT_BYTE_RSVD_MASK (0xF8000000u) 03110 #define OPT_BYTE_RSVD_BIT (27) 03111 #define OPT_BYTE_RSVD_BITS (5) 03112 /* OBR field */ 03113 #define OPT_BYTE_OBR (0x07FFFFFCu) 03114 #define OPT_BYTE_OBR_MASK (0x07FFFFFCu) 03115 #define OPT_BYTE_OBR_BIT (2) 03116 #define OPT_BYTE_OBR_BITS (25) 03117 /* RDPROT field */ 03118 #define OPT_BYTE_RDPROT (0x00000002u) 03119 #define OPT_BYTE_RDPROT_MASK (0x00000002u) 03120 #define OPT_BYTE_RDPROT_BIT (1) 03121 #define OPT_BYTE_RDPROT_BITS (1) 03122 /* OPT_ERR field */ 03123 #define OPT_BYTE_OPT_ERR (0x00000001u) 03124 #define OPT_BYTE_OPT_ERR_MASK (0x00000001u) 03125 #define OPT_BYTE_OPT_ERR_BIT (0) 03126 #define OPT_BYTE_OPT_ERR_BITS (1) 03127 03128 #define WRPROT *((volatile int32u *)0x40008020u) 03129 #define WRPROT_REG *((volatile int32u *)0x40008020u) 03130 #define WRPROT_ADDR (0x40008020u) 03131 #define WRPROT_RESET (0xFFFFFFFFu) 03132 /* WRP field */ 03133 #define WRPROT_WRP (0xFFFFFFFFu) 03134 #define WRPROT_WRP_MASK (0xFFFFFFFFu) 03135 #define WRPROT_WRP_BIT (0) 03136 #define WRPROT_WRP_BITS (32) 03137 03138 #define FLASH_TEST_CTRL *((volatile int32u *)0x40008080u) 03139 #define FLASH_TEST_CTRL_REG *((volatile int32u *)0x40008080u) 03140 #define FLASH_TEST_CTRL_ADDR (0x40008080u) 03141 #define FLASH_TEST_CTRL_RESET (0x00000000u) 03142 /* TMR field */ 03143 #define FLASH_TEST_CTRL_TMR (0x00001000u) 03144 #define FLASH_TEST_CTRL_TMR_MASK (0x00001000u) 03145 #define FLASH_TEST_CTRL_TMR_BIT (12) 03146 #define FLASH_TEST_CTRL_TMR_BITS (1) 03147 /* ERASE field */ 03148 #define FLASH_TEST_CTRL_ERASE (0x00000800u) 03149 #define FLASH_TEST_CTRL_ERASE_MASK (0x00000800u) 03150 #define FLASH_TEST_CTRL_ERASE_BIT (11) 03151 #define FLASH_TEST_CTRL_ERASE_BITS (1) 03152 /* MAS1 field */ 03153 #define FLASH_TEST_CTRL_MAS1 (0x00000400u) 03154 #define FLASH_TEST_CTRL_MAS1_MASK (0x00000400u) 03155 #define FLASH_TEST_CTRL_MAS1_BIT (10) 03156 #define FLASH_TEST_CTRL_MAS1_BITS (1) 03157 /* TEST_PROG field */ 03158 #define FLASH_TEST_CTRL_TEST_PROG (0x00000200u) 03159 #define FLASH_TEST_CTRL_TEST_PROG_MASK (0x00000200u) 03160 #define FLASH_TEST_CTRL_TEST_PROG_BIT (9) 03161 #define FLASH_TEST_CTRL_TEST_PROG_BITS (1) 03162 /* NVSTR field */ 03163 #define FLASH_TEST_CTRL_NVSTR (0x00000100u) 03164 #define FLASH_TEST_CTRL_NVSTR_MASK (0x00000100u) 03165 #define FLASH_TEST_CTRL_NVSTR_BIT (8) 03166 #define FLASH_TEST_CTRL_NVSTR_BITS (1) 03167 /* SE field */ 03168 #define FLASH_TEST_CTRL_SE (0x00000080u) 03169 #define FLASH_TEST_CTRL_SE_MASK (0x00000080u) 03170 #define FLASH_TEST_CTRL_SE_BIT (7) 03171 #define FLASH_TEST_CTRL_SE_BITS (1) 03172 /* IFREN field */ 03173 #define FLASH_TEST_CTRL_IFREN (0x00000040u) 03174 #define FLASH_TEST_CTRL_IFREN_MASK (0x00000040u) 03175 #define FLASH_TEST_CTRL_IFREN_BIT (6) 03176 #define FLASH_TEST_CTRL_IFREN_BITS (1) 03177 /* YE field */ 03178 #define FLASH_TEST_CTRL_YE (0x00000020u) 03179 #define FLASH_TEST_CTRL_YE_MASK (0x00000020u) 03180 #define FLASH_TEST_CTRL_YE_BIT (5) 03181 #define FLASH_TEST_CTRL_YE_BITS (1) 03182 /* XE field */ 03183 #define FLASH_TEST_CTRL_XE (0x00000010u) 03184 #define FLASH_TEST_CTRL_XE_MASK (0x00000010u) 03185 #define FLASH_TEST_CTRL_XE_BIT (4) 03186 #define FLASH_TEST_CTRL_XE_BITS (1) 03187 /* SW_CTRL field */ 03188 #define FLASH_TEST_CTRL_SW_CTRL (0x00000008u) 03189 #define FLASH_TEST_CTRL_SW_CTRL_MASK (0x00000008u) 03190 #define FLASH_TEST_CTRL_SW_CTRL_BIT (3) 03191 #define FLASH_TEST_CTRL_SW_CTRL_BITS (1) 03192 /* SW field */ 03193 #define FLASH_TEST_CTRL_SW (0x00000006u) 03194 #define FLASH_TEST_CTRL_SW_MASK (0x00000006u) 03195 #define FLASH_TEST_CTRL_SW_BIT (1) 03196 #define FLASH_TEST_CTRL_SW_BITS (2) 03197 /* SW_EN field */ 03198 #define FLASH_TEST_CTRL_SW_EN (0x00000001u) 03199 #define FLASH_TEST_CTRL_SW_EN_MASK (0x00000001u) 03200 #define FLASH_TEST_CTRL_SW_EN_BIT (0) 03201 #define FLASH_TEST_CTRL_SW_EN_BITS (1) 03202 03203 #define FLASH_DATA0 *((volatile int32u *)0x40008084u) 03204 #define FLASH_DATA0_REG *((volatile int32u *)0x40008084u) 03205 #define FLASH_DATA0_ADDR (0x40008084u) 03206 #define FLASH_DATA0_RESET (0xFFFFFFFFu) 03207 /* FDR0 field */ 03208 #define FLASH_DATA0_FDR0 (0xFFFFFFFFu) 03209 #define FLASH_DATA0_FDR0_MASK (0xFFFFFFFFu) 03210 #define FLASH_DATA0_FDR0_BIT (0) 03211 #define FLASH_DATA0_FDR0_BITS (32) 03212 03213 /* EMU_REGS block */ 03214 #define DATA_EMU_REGS_BASE (0x40009000u) 03215 #define DATA_EMU_REGS_END (0x40009000u) 03216 #define DATA_EMU_REGS_SIZE (DATA_EMU_REGS_END - DATA_EMU_REGS_BASE + 1) 03217 03218 #define I_AM_AN_EMULATOR *((volatile int32u *)0x40009000u) 03219 #define I_AM_AN_EMULATOR_REG *((volatile int32u *)0x40009000u) 03220 #define I_AM_AN_EMULATOR_ADDR (0x40009000u) 03221 #define I_AM_AN_EMULATOR_RESET (0x00000000u) 03222 /* I_AM_AN_EMULATOR field */ 03223 #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR (0x00000001u) 03224 #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK (0x00000001u) 03225 #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT (0) 03226 #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS (1) 03227 03228 /* INTERRUPTS block */ 03229 #define BLOCK_INTERRUPTS_BASE (0x4000A000u) 03230 #define BLOCK_INTERRUPTS_END (0x4000A86Cu) 03231 #define BLOCK_INTERRUPTS_SIZE (BLOCK_INTERRUPTS_END - BLOCK_INTERRUPTS_BASE + 1) 03232 03233 #define MAC_RX_INT_SRC *((volatile int32u *)0x4000A000u) 03234 #define MAC_RX_INT_SRC_REG *((volatile int32u *)0x4000A000u) 03235 #define MAC_RX_INT_SRC_ADDR (0x4000A000u) 03236 #define MAC_RX_INT_SRC_RESET (0x00000000u) 03237 /* TX_B_ACK_ERR_SRC field */ 03238 #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC (0x00008000u) 03239 #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_MASK (0x00008000u) 03240 #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BIT (15) 03241 #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BITS (1) 03242 /* TX_A_ACK_ERR_SRC field */ 03243 #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC (0x00004000u) 03244 #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_MASK (0x00004000u) 03245 #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BIT (14) 03246 #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BITS (1) 03247 /* RX_OVFLW_SRC field */ 03248 #define MAC_RX_INT_SRC_RX_OVFLW_SRC (0x00002000u) 03249 #define MAC_RX_INT_SRC_RX_OVFLW_SRC_MASK (0x00002000u) 03250 #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BIT (13) 03251 #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BITS (1) 03252 /* RX_ERROR_SRC field */ 03253 #define MAC_RX_INT_SRC_RX_ERROR_SRC (0x00001000u) 03254 #define MAC_RX_INT_SRC_RX_ERROR_SRC_MASK (0x00001000u) 03255 #define MAC_RX_INT_SRC_RX_ERROR_SRC_BIT (12) 03256 #define MAC_RX_INT_SRC_RX_ERROR_SRC_BITS (1) 03257 /* BB_RX_LEN_ERR_SRC field */ 03258 #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC (0x00000800u) 03259 #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_MASK (0x00000800u) 03260 #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BIT (11) 03261 #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BITS (1) 03262 /* TX_COLL_RX_SRC field */ 03263 #define MAC_RX_INT_SRC_TX_COLL_RX_SRC (0x00000400u) 03264 #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_MASK (0x00000400u) 03265 #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BIT (10) 03266 #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BITS (1) 03267 /* RSSI_INST_MEAS_SRC field */ 03268 #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC (0x00000200u) 03269 #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_MASK (0x00000200u) 03270 #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BIT (9) 03271 #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BITS (1) 03272 /* TX_B_ACK_SRC field */ 03273 #define MAC_RX_INT_SRC_TX_B_ACK_SRC (0x00000100u) 03274 #define MAC_RX_INT_SRC_TX_B_ACK_SRC_MASK (0x00000100u) 03275 #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BIT (8) 03276 #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BITS (1) 03277 /* TX_A_ACK_SRC field */ 03278 #define MAC_RX_INT_SRC_TX_A_ACK_SRC (0x00000080u) 03279 #define MAC_RX_INT_SRC_TX_A_ACK_SRC_MASK (0x00000080u) 03280 #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BIT (7) 03281 #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BITS (1) 03282 /* RX_B_UNLOAD_COMP_SRC field */ 03283 #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC (0x00000040u) 03284 #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_MASK (0x00000040u) 03285 #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BIT (6) 03286 #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BITS (1) 03287 /* RX_A_UNLOAD_COMP_SRC field */ 03288 #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC (0x00000020u) 03289 #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_MASK (0x00000020u) 03290 #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BIT (5) 03291 #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BITS (1) 03292 /* RX_B_ADDR_REC_SRC field */ 03293 #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC (0x00000010u) 03294 #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_MASK (0x00000010u) 03295 #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BIT (4) 03296 #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BITS (1) 03297 /* RX_A_ADDR_REC_SRC field */ 03298 #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC (0x00000008u) 03299 #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_MASK (0x00000008u) 03300 #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BIT (3) 03301 #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BITS (1) 03302 /* RX_B_FILT_COMP_SRC field */ 03303 #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC (0x00000004u) 03304 #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_MASK (0x00000004u) 03305 #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BIT (2) 03306 #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BITS (1) 03307 /* RX_A_FILT_COMP_SRC field */ 03308 #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC (0x00000002u) 03309 #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_MASK (0x00000002u) 03310 #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BIT (1) 03311 #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BITS (1) 03312 /* RX_FRAME_SRC field */ 03313 #define MAC_RX_INT_SRC_RX_FRAME_SRC (0x00000001u) 03314 #define MAC_RX_INT_SRC_RX_FRAME_SRC_MASK (0x00000001u) 03315 #define MAC_RX_INT_SRC_RX_FRAME_SRC_BIT (0) 03316 #define MAC_RX_INT_SRC_RX_FRAME_SRC_BITS (1) 03317 03318 #define MAC_TX_INT_SRC *((volatile int32u *)0x4000A004u) 03319 #define MAC_TX_INT_SRC_REG *((volatile int32u *)0x4000A004u) 03320 #define MAC_TX_INT_SRC_ADDR (0x4000A004u) 03321 #define MAC_TX_INT_SRC_RESET (0x00000000u) 03322 /* RX_B_ACK_SRC field */ 03323 #define MAC_TX_INT_SRC_RX_B_ACK_SRC (0x00000800u) 03324 #define MAC_TX_INT_SRC_RX_B_ACK_SRC_MASK (0x00000800u) 03325 #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BIT (11) 03326 #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BITS (1) 03327 /* RX_A_ACK_SRC field */ 03328 #define MAC_TX_INT_SRC_RX_A_ACK_SRC (0x00000400u) 03329 #define MAC_TX_INT_SRC_RX_A_ACK_SRC_MASK (0x00000400u) 03330 #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BIT (10) 03331 #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BITS (1) 03332 /* TX_B_UNLOAD_SRC field */ 03333 #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC (0x00000200u) 03334 #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_MASK (0x00000200u) 03335 #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BIT (9) 03336 #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BITS (1) 03337 /* TX_A_UNLOAD_SRC field */ 03338 #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC (0x00000100u) 03339 #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_MASK (0x00000100u) 03340 #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BIT (8) 03341 #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BITS (1) 03342 /* ACK_EXPIRED_SRC field */ 03343 #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC (0x00000080u) 03344 #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_MASK (0x00000080u) 03345 #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BIT (7) 03346 #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BITS (1) 03347 /* TX_LOCK_FAIL_SRC field */ 03348 #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC (0x00000040u) 03349 #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_MASK (0x00000040u) 03350 #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BIT (6) 03351 #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BITS (1) 03352 /* TX_UNDERFLOW_SRC field */ 03353 #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC (0x00000020u) 03354 #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_MASK (0x00000020u) 03355 #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BIT (5) 03356 #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BITS (1) 03357 /* CCA_FAIL_SRC field */ 03358 #define MAC_TX_INT_SRC_CCA_FAIL_SRC (0x00000010u) 03359 #define MAC_TX_INT_SRC_CCA_FAIL_SRC_MASK (0x00000010u) 03360 #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BIT (4) 03361 #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BITS (1) 03362 /* SFD_SENT_SRC field */ 03363 #define MAC_TX_INT_SRC_SFD_SENT_SRC (0x00000008u) 03364 #define MAC_TX_INT_SRC_SFD_SENT_SRC_MASK (0x00000008u) 03365 #define MAC_TX_INT_SRC_SFD_SENT_SRC_BIT (3) 03366 #define MAC_TX_INT_SRC_SFD_SENT_SRC_BITS (1) 03367 /* BO_COMPLETE_SRC field */ 03368 #define MAC_TX_INT_SRC_BO_COMPLETE_SRC (0x00000004u) 03369 #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_MASK (0x00000004u) 03370 #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BIT (2) 03371 #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BITS (1) 03372 /* RX_ACK_SRC field */ 03373 #define MAC_TX_INT_SRC_RX_ACK_SRC (0x00000002u) 03374 #define MAC_TX_INT_SRC_RX_ACK_SRC_MASK (0x00000002u) 03375 #define MAC_TX_INT_SRC_RX_ACK_SRC_BIT (1) 03376 #define MAC_TX_INT_SRC_RX_ACK_SRC_BITS (1) 03377 /* TX_COMPLETE_SRC field */ 03378 #define MAC_TX_INT_SRC_TX_COMPLETE_SRC (0x00000001u) 03379 #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_MASK (0x00000001u) 03380 #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT (0) 03381 #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS (1) 03382 03383 #define MAC_TIMER_INT_SRC *((volatile int32u *)0x4000A008u) 03384 #define MAC_TIMER_INT_SRC_REG *((volatile int32u *)0x4000A008u) 03385 #define MAC_TIMER_INT_SRC_ADDR (0x4000A008u) 03386 #define MAC_TIMER_INT_SRC_RESET (0x00000000u) 03387 /* TIMER_COMP_B_SRC field */ 03388 #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC (0x00000004u) 03389 #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_MASK (0x00000004u) 03390 #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BIT (2) 03391 #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BITS (1) 03392 /* TIMER_COMP_A_SRC field */ 03393 #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC (0x00000002u) 03394 #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_MASK (0x00000002u) 03395 #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BIT (1) 03396 #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BITS (1) 03397 /* TIMER_WRAP_SRC field */ 03398 #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC (0x00000001u) 03399 #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_MASK (0x00000001u) 03400 #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT (0) 03401 #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS (1) 03402 03403 #define BB_INT_SRC *((volatile int32u *)0x4000A00Cu) 03404 #define BB_INT_SRC_REG *((volatile int32u *)0x4000A00Cu) 03405 #define BB_INT_SRC_ADDR (0x4000A00Cu) 03406 #define BB_INT_SRC_RESET (0x00000000u) 03407 /* RSSI_INT_SRC field */ 03408 #define BB_INT_SRC_RSSI_INT_SRC (0x00000002u) 03409 #define BB_INT_SRC_RSSI_INT_SRC_MASK (0x00000002u) 03410 #define BB_INT_SRC_RSSI_INT_SRC_BIT (1) 03411 #define BB_INT_SRC_RSSI_INT_SRC_BITS (1) 03412 /* BASEBAND_INT_SRC field */ 03413 #define BB_INT_SRC_BASEBAND_INT_SRC (0x00000001u) 03414 #define BB_INT_SRC_BASEBAND_INT_SRC_MASK (0x00000001u) 03415 #define BB_INT_SRC_BASEBAND_INT_SRC_BIT (0) 03416 #define BB_INT_SRC_BASEBAND_INT_SRC_BITS (1) 03417 03418 #define SEC_INT_SRC *((volatile int32u *)0x4000A010u) 03419 #define SEC_INT_SRC_REG *((volatile int32u *)0x4000A010u) 03420 #define SEC_INT_SRC_ADDR (0x4000A010u) 03421 #define SEC_INT_SRC_RESET (0x00000000u) 03422 /* CT_WORD_VALID_SRC field */ 03423 #define SEC_INT_SRC_CT_WORD_VALID_SRC (0x00000004u) 03424 #define SEC_INT_SRC_CT_WORD_VALID_SRC_MASK (0x00000004u) 03425 #define SEC_INT_SRC_CT_WORD_VALID_SRC_BIT (2) 03426 #define SEC_INT_SRC_CT_WORD_VALID_SRC_BITS (1) 03427 /* PT_WORD_REQ_SRC field */ 03428 #define SEC_INT_SRC_PT_WORD_REQ_SRC (0x00000002u) 03429 #define SEC_INT_SRC_PT_WORD_REQ_SRC_MASK (0x00000002u) 03430 #define SEC_INT_SRC_PT_WORD_REQ_SRC_BIT (1) 03431 #define SEC_INT_SRC_PT_WORD_REQ_SRC_BITS (1) 03432 /* ENC_COMPLETE_SRC field */ 03433 #define SEC_INT_SRC_ENC_COMPLETE_SRC (0x00000001u) 03434 #define SEC_INT_SRC_ENC_COMPLETE_SRC_MASK (0x00000001u) 03435 #define SEC_INT_SRC_ENC_COMPLETE_SRC_BIT (0) 03436 #define SEC_INT_SRC_ENC_COMPLETE_SRC_BITS (1) 03437 03438 #define INT_SLEEPTMRFLAG *((volatile int32u *)0x4000A014u) 03439 #define INT_SLEEPTMRFLAG_REG *((volatile int32u *)0x4000A014u) 03440 #define INT_SLEEPTMRFLAG_ADDR (0x4000A014u) 03441 #define INT_SLEEPTMRFLAG_RESET (0x00000000u) 03442 /* INT_SLEEPTMRCMPB field */ 03443 #define INT_SLEEPTMRCMPB (0x00000004u) 03444 #define INT_SLEEPTMRCMPB_MASK (0x00000004u) 03445 #define INT_SLEEPTMRCMPB_BIT (2) 03446 #define INT_SLEEPTMRCMPB_BITS (1) 03447 /* INT_SLEEPTMRCMPA field */ 03448 #define INT_SLEEPTMRCMPA (0x00000002u) 03449 #define INT_SLEEPTMRCMPA_MASK (0x00000002u) 03450 #define INT_SLEEPTMRCMPA_BIT (1) 03451 #define INT_SLEEPTMRCMPA_BITS (1) 03452 /* INT_SLEEPTMRWRAP field */ 03453 #define INT_SLEEPTMRWRAP (0x00000001u) 03454 #define INT_SLEEPTMRWRAP_MASK (0x00000001u) 03455 #define INT_SLEEPTMRWRAP_BIT (0) 03456 #define INT_SLEEPTMRWRAP_BITS (1) 03457 03458 #define INT_MGMTFLAG *((volatile int32u *)0x4000A018u) 03459 #define INT_MGMTFLAG_REG *((volatile int32u *)0x4000A018u) 03460 #define INT_MGMTFLAG_ADDR (0x4000A018u) 03461 #define INT_MGMTFLAG_RESET (0x00000000u) 03462 /* INT_MGMTDMAPROT field */ 03463 #define INT_MGMTDMAPROT (0x00000010u) 03464 #define INT_MGMTDMAPROT_MASK (0x00000010u) 03465 #define INT_MGMTDMAPROT_BIT (4) 03466 #define INT_MGMTDMAPROT_BITS (1) 03467 /* INT_MGMTCALADC field */ 03468 #define INT_MGMTCALADC (0x00000008u) 03469 #define INT_MGMTCALADC_MASK (0x00000008u) 03470 #define INT_MGMTCALADC_BIT (3) 03471 #define INT_MGMTCALADC_BITS (1) 03472 /* INT_MGMTFPEC field */ 03473 #define INT_MGMTFPEC (0x00000004u) 03474 #define INT_MGMTFPEC_MASK (0x00000004u) 03475 #define INT_MGMTFPEC_BIT (2) 03476 #define INT_MGMTFPEC_BITS (1) 03477 /* INT_MGMTOSC24MHI field */ 03478 #define INT_MGMTOSC24MHI (0x00000002u) 03479 #define INT_MGMTOSC24MHI_MASK (0x00000002u) 03480 #define INT_MGMTOSC24MHI_BIT (1) 03481 #define INT_MGMTOSC24MHI_BITS (1) 03482 /* INT_MGMTOSC24MLO field */ 03483 #define INT_MGMTOSC24MLO (0x00000001u) 03484 #define INT_MGMTOSC24MLO_MASK (0x00000001u) 03485 #define INT_MGMTOSC24MLO_BIT (0) 03486 #define INT_MGMTOSC24MLO_BITS (1) 03487 03488 #define INT_NMIFLAG *((volatile int32u *)0x4000A01Cu) 03489 #define INT_NMIFLAG_REG *((volatile int32u *)0x4000A01Cu) 03490 #define INT_NMIFLAG_ADDR (0x4000A01Cu) 03491 #define INT_NMIFLAG_RESET (0x00000000u) 03492 /* INT_NMICLK24M field */ 03493 #define INT_NMICLK24M (0x00000002u) 03494 #define INT_NMICLK24M_MASK (0x00000002u) 03495 #define INT_NMICLK24M_BIT (1) 03496 #define INT_NMICLK24M_BITS (1) 03497 /* INT_NMIWDOG field */ 03498 #define INT_NMIWDOG (0x00000001u) 03499 #define INT_NMIWDOG_MASK (0x00000001u) 03500 #define INT_NMIWDOG_BIT (0) 03501 #define INT_NMIWDOG_BITS (1) 03502 03503 #define INT_SLEEPTMRFORCE *((volatile int32u *)0x4000A020u) 03504 #define INT_SLEEPTMRFORCE_REG *((volatile int32u *)0x4000A020u) 03505 #define INT_SLEEPTMRFORCE_ADDR (0x4000A020u) 03506 #define INT_SLEEPTMRFORCE_RESET (0x00000000u) 03507 /* INT_SLEEPTMRCMPB field */ 03508 #define INT_SLEEPTMRCMPB (0x00000004u) 03509 #define INT_SLEEPTMRCMPB_MASK (0x00000004u) 03510 #define INT_SLEEPTMRCMPB_BIT (2) 03511 #define INT_SLEEPTMRCMPB_BITS (1) 03512 /* INT_SLEEPTMRCMPA field */ 03513 #define INT_SLEEPTMRCMPA (0x00000002u) 03514 #define INT_SLEEPTMRCMPA_MASK (0x00000002u) 03515 #define INT_SLEEPTMRCMPA_BIT (1) 03516 #define INT_SLEEPTMRCMPA_BITS (1) 03517 /* INT_SLEEPTMRWRAP field */ 03518 #define INT_SLEEPTMRWRAP (0x00000001u) 03519 #define INT_SLEEPTMRWRAP_MASK (0x00000001u) 03520 #define INT_SLEEPTMRWRAP_BIT (0) 03521 #define INT_SLEEPTMRWRAP_BITS (1) 03522 03523 #define TEST_FORCE_ALL_INT *((volatile int32u *)0x4000A024u) 03524 #define TEST_FORCE_ALL_INT_REG *((volatile int32u *)0x4000A024u) 03525 #define TEST_FORCE_ALL_INT_ADDR (0x4000A024u) 03526 #define TEST_FORCE_ALL_INT_RESET (0x00000000u) 03527 /* FORCE_ALL_INT field */ 03528 #define TEST_FORCE_ALL_INT_FORCE_ALL_INT (0x00000001u) 03529 #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_MASK (0x00000001u) 03530 #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT (0) 03531 #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS (1) 03532 03533 #define MAC_RX_INT_MASK *((volatile int32u *)0x4000A040u) 03534 #define MAC_RX_INT_MASK_REG *((volatile int32u *)0x4000A040u) 03535 #define MAC_RX_INT_MASK_ADDR (0x4000A040u) 03536 #define MAC_RX_INT_MASK_RESET (0x00000000u) 03537 /* TX_B_ACK_ERR_MSK field */ 03538 #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK (0x00008000u) 03539 #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_MASK (0x00008000u) 03540 #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BIT (15) 03541 #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BITS (1) 03542 /* TX_A_ACK_ERR_MSK field */ 03543 #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK (0x00004000u) 03544 #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_MASK (0x00004000u) 03545 #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BIT (14) 03546 #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BITS (1) 03547 /* RX_OVFLW_MSK field */ 03548 #define MAC_RX_INT_MASK_RX_OVFLW_MSK (0x00002000u) 03549 #define MAC_RX_INT_MASK_RX_OVFLW_MSK_MASK (0x00002000u) 03550 #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BIT (13) 03551 #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BITS (1) 03552 /* RX_ERROR_MSK field */ 03553 #define MAC_RX_INT_MASK_RX_ERROR_MSK (0x00001000u) 03554 #define MAC_RX_INT_MASK_RX_ERROR_MSK_MASK (0x00001000u) 03555 #define MAC_RX_INT_MASK_RX_ERROR_MSK_BIT (12) 03556 #define MAC_RX_INT_MASK_RX_ERROR_MSK_BITS (1) 03557 /* BB_RX_LEN_ERR_MSK field */ 03558 #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK (0x00000800u) 03559 #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_MASK (0x00000800u) 03560 #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BIT (11) 03561 #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BITS (1) 03562 /* TX_COLL_RX_MSK field */ 03563 #define MAC_RX_INT_MASK_TX_COLL_RX_MSK (0x00000400u) 03564 #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_MASK (0x00000400u) 03565 #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BIT (10) 03566 #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BITS (1) 03567 /* RSSI_INST_MEAS_MSK field */ 03568 #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK (0x00000200u) 03569 #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_MASK (0x00000200u) 03570 #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BIT (9) 03571 #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BITS (1) 03572 /* TX_B_ACK_MSK field */ 03573 #define MAC_RX_INT_MASK_TX_B_ACK_MSK (0x00000100u) 03574 #define MAC_RX_INT_MASK_TX_B_ACK_MSK_MASK (0x00000100u) 03575 #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BIT (8) 03576 #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BITS (1) 03577 /* TX_A_ACK_MSK field */ 03578 #define MAC_RX_INT_MASK_TX_A_ACK_MSK (0x00000080u) 03579 #define MAC_RX_INT_MASK_TX_A_ACK_MSK_MASK (0x00000080u) 03580 #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BIT (7) 03581 #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BITS (1) 03582 /* RX_B_UNLOAD_COMP_MSK field */ 03583 #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK (0x00000040u) 03584 #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_MASK (0x00000040u) 03585 #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BIT (6) 03586 #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BITS (1) 03587 /* RX_A_UNLOAD_COMP_MSK field */ 03588 #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK (0x00000020u) 03589 #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_MASK (0x00000020u) 03590 #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BIT (5) 03591 #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BITS (1) 03592 /* RX_B_ADDR_REC_MSK field */ 03593 #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK (0x00000010u) 03594 #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_MASK (0x00000010u) 03595 #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BIT (4) 03596 #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BITS (1) 03597 /* RX_A_ADDR_REC_MSK field */ 03598 #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK (0x00000008u) 03599 #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_MASK (0x00000008u) 03600 #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BIT (3) 03601 #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BITS (1) 03602 /* RX_B_FILT_COMP_MSK field */ 03603 #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK (0x00000004u) 03604 #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_MASK (0x00000004u) 03605 #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BIT (2) 03606 #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BITS (1) 03607 /* RX_A_FILT_COMP_MSK field */ 03608 #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK (0x00000002u) 03609 #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_MASK (0x00000002u) 03610 #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BIT (1) 03611 #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BITS (1) 03612 /* RX_FRAME_MSK field */ 03613 #define MAC_RX_INT_MASK_RX_FRAME_MSK (0x00000001u) 03614 #define MAC_RX_INT_MASK_RX_FRAME_MSK_MASK (0x00000001u) 03615 #define MAC_RX_INT_MASK_RX_FRAME_MSK_BIT (0) 03616 #define MAC_RX_INT_MASK_RX_FRAME_MSK_BITS (1) 03617 03618 #define MAC_TX_INT_MASK *((volatile int32u *)0x4000A044u) 03619 #define MAC_TX_INT_MASK_REG *((volatile int32u *)0x4000A044u) 03620 #define MAC_TX_INT_MASK_ADDR (0x4000A044u) 03621 #define MAC_TX_INT_MASK_RESET (0x00000000u) 03622 /* RX_B_ACK_MSK field */ 03623 #define MAC_TX_INT_MASK_RX_B_ACK_MSK (0x00000800u) 03624 #define MAC_TX_INT_MASK_RX_B_ACK_MSK_MASK (0x00000800u) 03625 #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BIT (11) 03626 #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BITS (1) 03627 /* RX_A_ACK_MSK field */ 03628 #define MAC_TX_INT_MASK_RX_A_ACK_MSK (0x00000400u) 03629 #define MAC_TX_INT_MASK_RX_A_ACK_MSK_MASK (0x00000400u) 03630 #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BIT (10) 03631 #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BITS (1) 03632 /* TX_B_UNLOAD_MSK field */ 03633 #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK (0x00000200u) 03634 #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_MASK (0x00000200u) 03635 #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BIT (9) 03636 #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BITS (1) 03637 /* TX_A_UNLOAD_MSK field */ 03638 #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK (0x00000100u) 03639 #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_MASK (0x00000100u) 03640 #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BIT (8) 03641 #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BITS (1) 03642 /* ACK_EXPIRED_MSK field */ 03643 #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK (0x00000080u) 03644 #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_MASK (0x00000080u) 03645 #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BIT (7) 03646 #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BITS (1) 03647 /* TX_LOCK_FAIL_MSK field */ 03648 #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK (0x00000040u) 03649 #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_MASK (0x00000040u) 03650 #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BIT (6) 03651 #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BITS (1) 03652 /* TX_UNDERFLOW_MSK field */ 03653 #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK (0x00000020u) 03654 #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_MASK (0x00000020u) 03655 #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BIT (5) 03656 #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BITS (1) 03657 /* CCA_FAIL_MSK field */ 03658 #define MAC_TX_INT_MASK_CCA_FAIL_MSK (0x00000010u) 03659 #define MAC_TX_INT_MASK_CCA_FAIL_MSK_MASK (0x00000010u) 03660 #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BIT (4) 03661 #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BITS (1) 03662 /* SFD_SENT_MSK field */ 03663 #define MAC_TX_INT_MASK_SFD_SENT_MSK (0x00000008u) 03664 #define MAC_TX_INT_MASK_SFD_SENT_MSK_MASK (0x00000008u) 03665 #define MAC_TX_INT_MASK_SFD_SENT_MSK_BIT (3) 03666 #define MAC_TX_INT_MASK_SFD_SENT_MSK_BITS (1) 03667 /* BO_COMPLETE_MSK field */ 03668 #define MAC_TX_INT_MASK_BO_COMPLETE_MSK (0x00000004u) 03669 #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_MASK (0x00000004u) 03670 #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BIT (2) 03671 #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BITS (1) 03672 /* RX_ACK_MSK field */ 03673 #define MAC_TX_INT_MASK_RX_ACK_MSK (0x00000002u) 03674 #define MAC_TX_INT_MASK_RX_ACK_MSK_MASK (0x00000002u) 03675 #define MAC_TX_INT_MASK_RX_ACK_MSK_BIT (1) 03676 #define MAC_TX_INT_MASK_RX_ACK_MSK_BITS (1) 03677 /* TX_COMPLETE_MSK field */ 03678 #define MAC_TX_INT_MASK_TX_COMPLETE_MSK (0x00000001u) 03679 #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_MASK (0x00000001u) 03680 #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT (0) 03681 #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS (1) 03682 03683 #define MAC_TIMER_INT_MASK *((volatile int32u *)0x4000A048u) 03684 #define MAC_TIMER_INT_MASK_REG *((volatile int32u *)0x4000A048u) 03685 #define MAC_TIMER_INT_MASK_ADDR (0x4000A048u) 03686 #define MAC_TIMER_INT_MASK_RESET (0x00000000u) 03687 /* TIMER_COMP_B_MSK field */ 03688 #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK (0x00000004u) 03689 #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_MASK (0x00000004u) 03690 #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BIT (2) 03691 #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BITS (1) 03692 /* TIMER_COMP_A_MSK field */ 03693 #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK (0x00000002u) 03694 #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_MASK (0x00000002u) 03695 #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BIT (1) 03696 #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BITS (1) 03697 /* TIMER_WRAP_MSK field */ 03698 #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK (0x00000001u) 03699 #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_MASK (0x00000001u) 03700 #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT (0) 03701 #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS (1) 03702 03703 #define BB_INT_MASK *((volatile int32u *)0x4000A04Cu) 03704 #define BB_INT_MASK_REG *((volatile int32u *)0x4000A04Cu) 03705 #define BB_INT_MASK_ADDR (0x4000A04Cu) 03706 #define BB_INT_MASK_RESET (0x00000000u) 03707 /* RSSI_INT_MSK field */ 03708 #define BB_INT_MASK_RSSI_INT_MSK (0x00000002u) 03709 #define BB_INT_MASK_RSSI_INT_MSK_MASK (0x00000002u) 03710 #define BB_INT_MASK_RSSI_INT_MSK_BIT (1) 03711 #define BB_INT_MASK_RSSI_INT_MSK_BITS (1) 03712 /* BASEBAND_INT_MSK field */ 03713 #define BB_INT_MASK_BASEBAND_INT_MSK (0x00000001u) 03714 #define BB_INT_MASK_BASEBAND_INT_MSK_MASK (0x00000001u) 03715 #define BB_INT_MASK_BASEBAND_INT_MSK_BIT (0) 03716 #define BB_INT_MASK_BASEBAND_INT_MSK_BITS (1) 03717 03718 #define SEC_INT_MASK *((volatile int32u *)0x4000A050u) 03719 #define SEC_INT_MASK_REG *((volatile int32u *)0x4000A050u) 03720 #define SEC_INT_MASK_ADDR (0x4000A050u) 03721 #define SEC_INT_MASK_RESET (0x00000000u) 03722 /* CT_WORD_VALID_MSK field */ 03723 #define SEC_INT_MASK_CT_WORD_VALID_MSK (0x00000004u) 03724 #define SEC_INT_MASK_CT_WORD_VALID_MSK_MASK (0x00000004u) 03725 #define SEC_INT_MASK_CT_WORD_VALID_MSK_BIT (2) 03726 #define SEC_INT_MASK_CT_WORD_VALID_MSK_BITS (1) 03727 /* PT_WORD_REQ_MSK field */ 03728 #define SEC_INT_MASK_PT_WORD_REQ_MSK (0x00000002u) 03729 #define SEC_INT_MASK_PT_WORD_REQ_MSK_MASK (0x00000002u) 03730 #define SEC_INT_MASK_PT_WORD_REQ_MSK_BIT (1) 03731 #define SEC_INT_MASK_PT_WORD_REQ_MSK_BITS (1) 03732 /* ENC_COMPLETE_MSK field */ 03733 #define SEC_INT_MASK_ENC_COMPLETE_MSK (0x00000001u) 03734 #define SEC_INT_MASK_ENC_COMPLETE_MSK_MASK (0x00000001u) 03735 #define SEC_INT_MASK_ENC_COMPLETE_MSK_BIT (0) 03736 #define SEC_INT_MASK_ENC_COMPLETE_MSK_BITS (1) 03737 03738 #define INT_SLEEPTMRCFG *((volatile int32u *)0x4000A054u) 03739 #define INT_SLEEPTMRCFG_REG *((volatile int32u *)0x4000A054u) 03740 #define INT_SLEEPTMRCFG_ADDR (0x4000A054u) 03741 #define INT_SLEEPTMRCFG_RESET (0x00000000u) 03742 /* INT_SLEEPTMRCMPB field */ 03743 #define INT_SLEEPTMRCMPB (0x00000004u) 03744 #define INT_SLEEPTMRCMPB_MASK (0x00000004u) 03745 #define INT_SLEEPTMRCMPB_BIT (2) 03746 #define INT_SLEEPTMRCMPB_BITS (1) 03747 /* INT_SLEEPTMRCMPA field */ 03748 #define INT_SLEEPTMRCMPA (0x00000002u) 03749 #define INT_SLEEPTMRCMPA_MASK (0x00000002u) 03750 #define INT_SLEEPTMRCMPA_BIT (1) 03751 #define INT_SLEEPTMRCMPA_BITS (1) 03752 /* INT_SLEEPTMRWRAP field */ 03753 #define INT_SLEEPTMRWRAP (0x00000001u) 03754 #define INT_SLEEPTMRWRAP_MASK (0x00000001u) 03755 #define INT_SLEEPTMRWRAP_BIT (0) 03756 #define INT_SLEEPTMRWRAP_BITS (1) 03757 03758 #define INT_MGMTCFG *((volatile int32u *)0x4000A058u) 03759 #define INT_MGMTCFG_REG *((volatile int32u *)0x4000A058u) 03760 #define INT_MGMTCFG_ADDR (0x4000A058u) 03761 #define INT_MGMTCFG_RESET (0x00000000u) 03762 /* INT_MGMTDMAPROT field */ 03763 #define INT_MGMTDMAPROT (0x00000010u) 03764 #define INT_MGMTDMAPROT_MASK (0x00000010u) 03765 #define INT_MGMTDMAPROT_BIT (4) 03766 #define INT_MGMTDMAPROT_BITS (1) 03767 /* INT_MGMTCALADC field */ 03768 #define INT_MGMTCALADC (0x00000008u) 03769 #define INT_MGMTCALADC_MASK (0x00000008u) 03770 #define INT_MGMTCALADC_BIT (3) 03771 #define INT_MGMTCALADC_BITS (1) 03772 /* INT_MGMTFPEC field */ 03773 #define INT_MGMTFPEC (0x00000004u) 03774 #define INT_MGMTFPEC_MASK (0x00000004u) 03775 #define INT_MGMTFPEC_BIT (2) 03776 #define INT_MGMTFPEC_BITS (1) 03777 /* INT_MGMTOSC24MHI field */ 03778 #define INT_MGMTOSC24MHI (0x00000002u) 03779 #define INT_MGMTOSC24MHI_MASK (0x00000002u) 03780 #define INT_MGMTOSC24MHI_BIT (1) 03781 #define INT_MGMTOSC24MHI_BITS (1) 03782 /* INT_MGMTOSC24MLO field */ 03783 #define INT_MGMTOSC24MLO (0x00000001u) 03784 #define INT_MGMTOSC24MLO_MASK (0x00000001u) 03785 #define INT_MGMTOSC24MLO_BIT (0) 03786 #define INT_MGMTOSC24MLO_BITS (1) 03787 03788 #define INT_TIM1FLAG *((volatile int32u *)0x4000A800u) 03789 #define INT_TIM1FLAG_REG *((volatile int32u *)0x4000A800u) 03790 #define INT_TIM1FLAG_ADDR (0x4000A800u) 03791 #define INT_TIM1FLAG_RESET (0x00000000u) 03792 /* INT_TIMRSVD field */ 03793 #define INT_TIMRSVD (0x00001E00u) 03794 #define INT_TIMRSVD_MASK (0x00001E00u) 03795 #define INT_TIMRSVD_BIT (9) 03796 #define INT_TIMRSVD_BITS (4) 03797 /* INT_TIMTIF field */ 03798 #define INT_TIMTIF (0x00000040u) 03799 #define INT_TIMTIF_MASK (0x00000040u) 03800 #define INT_TIMTIF_BIT (6) 03801 #define INT_TIMTIF_BITS (1) 03802 /* INT_TIMCC4IF field */ 03803 #define INT_TIMCC4IF (0x00000010u) 03804 #define INT_TIMCC4IF_MASK (0x00000010u) 03805 #define INT_TIMCC4IF_BIT (4) 03806 #define INT_TIMCC4IF_BITS (1) 03807 /* INT_TIMCC3IF field */ 03808 #define INT_TIMCC3IF (0x00000008u) 03809 #define INT_TIMCC3IF_MASK (0x00000008u) 03810 #define INT_TIMCC3IF_BIT (3) 03811 #define INT_TIMCC3IF_BITS (1) 03812 /* INT_TIMCC2IF field */ 03813 #define INT_TIMCC2IF (0x00000004u) 03814 #define INT_TIMCC2IF_MASK (0x00000004u) 03815 #define INT_TIMCC2IF_BIT (2) 03816 #define INT_TIMCC2IF_BITS (1) 03817 /* INT_TIMCC1IF field */ 03818 #define INT_TIMCC1IF (0x00000002u) 03819 #define INT_TIMCC1IF_MASK (0x00000002u) 03820 #define INT_TIMCC1IF_BIT (1) 03821 #define INT_TIMCC1IF_BITS (1) 03822 /* INT_TIMUIF field */ 03823 #define INT_TIMUIF (0x00000001u) 03824 #define INT_TIMUIF_MASK (0x00000001u) 03825 #define INT_TIMUIF_BIT (0) 03826 #define INT_TIMUIF_BITS (1) 03827 03828 #define INT_TIM2FLAG *((volatile int32u *)0x4000A804u) 03829 #define INT_TIM2FLAG_REG *((volatile int32u *)0x4000A804u) 03830 #define INT_TIM2FLAG_ADDR (0x4000A804u) 03831 #define INT_TIM2FLAG_RESET (0x00000000u) 03832 /* INT_TIMRSVD field */ 03833 #define INT_TIMRSVD (0x00001E00u) 03834 #define INT_TIMRSVD_MASK (0x00001E00u) 03835 #define INT_TIMRSVD_BIT (9) 03836 #define INT_TIMRSVD_BITS (4) 03837 /* INT_TIMTIF field */ 03838 #define INT_TIMTIF (0x00000040u) 03839 #define INT_TIMTIF_MASK (0x00000040u) 03840 #define INT_TIMTIF_BIT (6) 03841 #define INT_TIMTIF_BITS (1) 03842 /* INT_TIMCC4IF field */ 03843 #define INT_TIMCC4IF (0x00000010u) 03844 #define INT_TIMCC4IF_MASK (0x00000010u) 03845 #define INT_TIMCC4IF_BIT (4) 03846 #define INT_TIMCC4IF_BITS (1) 03847 /* INT_TIMCC3IF field */ 03848 #define INT_TIMCC3IF (0x00000008u) 03849 #define INT_TIMCC3IF_MASK (0x00000008u) 03850 #define INT_TIMCC3IF_BIT (3) 03851 #define INT_TIMCC3IF_BITS (1) 03852 /* INT_TIMCC2IF field */ 03853 #define INT_TIMCC2IF (0x00000004u) 03854 #define INT_TIMCC2IF_MASK (0x00000004u) 03855 #define INT_TIMCC2IF_BIT (2) 03856 #define INT_TIMCC2IF_BITS (1) 03857 /* INT_TIMCC1IF field */ 03858 #define INT_TIMCC1IF (0x00000002u) 03859 #define INT_TIMCC1IF_MASK (0x00000002u) 03860 #define INT_TIMCC1IF_BIT (1) 03861 #define INT_TIMCC1IF_BITS (1) 03862 /* INT_TIMUIF field */ 03863 #define INT_TIMUIF (0x00000001u) 03864 #define INT_TIMUIF_MASK (0x00000001u) 03865 #define INT_TIMUIF_BIT (0) 03866 #define INT_TIMUIF_BITS (1) 03867 03868 #define INT_SC1FLAG *((volatile int32u *)0x4000A808u) 03869 #define INT_SC1FLAG_REG *((volatile int32u *)0x4000A808u) 03870 #define INT_SC1FLAG_ADDR (0x4000A808u) 03871 #define INT_SC1FLAG_RESET (0x00000000u) 03872 /* INT_SC1PARERR field */ 03873 #define INT_SC1PARERR (0x00004000u) 03874 #define INT_SC1PARERR_MASK (0x00004000u) 03875 #define INT_SC1PARERR_BIT (14) 03876 #define INT_SC1PARERR_BITS (1) 03877 /* INT_SC1FRMERR field */ 03878 #define INT_SC1FRMERR (0x00002000u) 03879 #define INT_SC1FRMERR_MASK (0x00002000u) 03880 #define INT_SC1FRMERR_BIT (13) 03881 #define INT_SC1FRMERR_BITS (1) 03882 /* INT_SCTXULDB field */ 03883 #define INT_SCTXULDB (0x00001000u) 03884 #define INT_SCTXULDB_MASK (0x00001000u) 03885 #define INT_SCTXULDB_BIT (12) 03886 #define INT_SCTXULDB_BITS (1) 03887 /* INT_SCTXULDA field */ 03888 #define INT_SCTXULDA (0x00000800u) 03889 #define INT_SCTXULDA_MASK (0x00000800u) 03890 #define INT_SCTXULDA_BIT (11) 03891 #define INT_SCTXULDA_BITS (1) 03892 /* INT_SCRXULDB field */ 03893 #define INT_SCRXULDB (0x00000400u) 03894 #define INT_SCRXULDB_MASK (0x00000400u) 03895 #define INT_SCRXULDB_BIT (10) 03896 #define INT_SCRXULDB_BITS (1) 03897 /* INT_SCRXULDA field */ 03898 #define INT_SCRXULDA (0x00000200u) 03899 #define INT_SCRXULDA_MASK (0x00000200u) 03900 #define INT_SCRXULDA_BIT (9) 03901 #define INT_SCRXULDA_BITS (1) 03902 /* INT_SCNAK field */ 03903 #define INT_SCNAK (0x00000100u) 03904 #define INT_SCNAK_MASK (0x00000100u) 03905 #define INT_SCNAK_BIT (8) 03906 #define INT_SCNAK_BITS (1) 03907 /* INT_SCCMDFIN field */ 03908 #define INT_SCCMDFIN (0x00000080u) 03909 #define INT_SCCMDFIN_MASK (0x00000080u) 03910 #define INT_SCCMDFIN_BIT (7) 03911 #define INT_SCCMDFIN_BITS (1) 03912 /* INT_SCTXFIN field */ 03913 #define INT_SCTXFIN (0x00000040u) 03914 #define INT_SCTXFIN_MASK (0x00000040u) 03915 #define INT_SCTXFIN_BIT (6) 03916 #define INT_SCTXFIN_BITS (1) 03917 /* INT_SCRXFIN field */ 03918 #define INT_SCRXFIN (0x00000020u) 03919 #define INT_SCRXFIN_MASK (0x00000020u) 03920 #define INT_SCRXFIN_BIT (5) 03921 #define INT_SCRXFIN_BITS (1) 03922 /* INT_SCTXUND field */ 03923 #define INT_SCTXUND (0x00000010u) 03924 #define INT_SCTXUND_MASK (0x00000010u) 03925 #define INT_SCTXUND_BIT (4) 03926 #define INT_SCTXUND_BITS (1) 03927 /* INT_SCRXOVF field */ 03928 #define INT_SCRXOVF (0x00000008u) 03929 #define INT_SCRXOVF_MASK (0x00000008u) 03930 #define INT_SCRXOVF_BIT (3) 03931 #define INT_SCRXOVF_BITS (1) 03932 /* INT_SCTXIDLE field */ 03933 #define INT_SCTXIDLE (0x00000004u) 03934 #define INT_SCTXIDLE_MASK (0x00000004u) 03935 #define INT_SCTXIDLE_BIT (2) 03936 #define INT_SCTXIDLE_BITS (1) 03937 /* INT_SCTXFREE field */ 03938 #define INT_SCTXFREE (0x00000002u) 03939 #define INT_SCTXFREE_MASK (0x00000002u) 03940 #define INT_SCTXFREE_BIT (1) 03941 #define INT_SCTXFREE_BITS (1) 03942 /* INT_SCRXVAL field */ 03943 #define INT_SCRXVAL (0x00000001u) 03944 #define INT_SCRXVAL_MASK (0x00000001u) 03945 #define INT_SCRXVAL_BIT (0) 03946 #define INT_SCRXVAL_BITS (1) 03947 03948 #define INT_SC2FLAG *((volatile int32u *)0x4000A80Cu) 03949 #define INT_SC2FLAG_REG *((volatile int32u *)0x4000A80Cu) 03950 #define INT_SC2FLAG_ADDR (0x4000A80Cu) 03951 #define INT_SC2FLAG_RESET (0x00000000u) 03952 /* INT_SCTXULDB field */ 03953 #define INT_SCTXULDB (0x00001000u) 03954 #define INT_SCTXULDB_MASK (0x00001000u) 03955 #define INT_SCTXULDB_BIT (12) 03956 #define INT_SCTXULDB_BITS (1) 03957 /* INT_SCTXULDA field */ 03958 #define INT_SCTXULDA (0x00000800u) 03959 #define INT_SCTXULDA_MASK (0x00000800u) 03960 #define INT_SCTXULDA_BIT (11) 03961 #define INT_SCTXULDA_BITS (1) 03962 /* INT_SCRXULDB field */ 03963 #define INT_SCRXULDB (0x00000400u) 03964 #define INT_SCRXULDB_MASK (0x00000400u) 03965 #define INT_SCRXULDB_BIT (10) 03966 #define INT_SCRXULDB_BITS (1) 03967 /* INT_SCRXULDA field */ 03968 #define INT_SCRXULDA (0x00000200u) 03969 #define INT_SCRXULDA_MASK (0x00000200u) 03970 #define INT_SCRXULDA_BIT (9) 03971 #define INT_SCRXULDA_BITS (1) 03972 /* INT_SCNAK field */ 03973 #define INT_SCNAK (0x00000100u) 03974 #define INT_SCNAK_MASK (0x00000100u) 03975 #define INT_SCNAK_BIT (8) 03976 #define INT_SCNAK_BITS (1) 03977 /* INT_SCCMDFIN field */ 03978 #define INT_SCCMDFIN (0x00000080u) 03979 #define INT_SCCMDFIN_MASK (0x00000080u) 03980 #define INT_SCCMDFIN_BIT (7) 03981 #define INT_SCCMDFIN_BITS (1) 03982 /* INT_SCTXFIN field */ 03983 #define INT_SCTXFIN (0x00000040u) 03984 #define INT_SCTXFIN_MASK (0x00000040u) 03985 #define INT_SCTXFIN_BIT (6) 03986 #define INT_SCTXFIN_BITS (1) 03987 /* INT_SCRXFIN field */ 03988 #define INT_SCRXFIN (0x00000020u) 03989 #define INT_SCRXFIN_MASK (0x00000020u) 03990 #define INT_SCRXFIN_BIT (5) 03991 #define INT_SCRXFIN_BITS (1) 03992 /* INT_SCTXUND field */ 03993 #define INT_SCTXUND (0x00000010u) 03994 #define INT_SCTXUND_MASK (0x00000010u) 03995 #define INT_SCTXUND_BIT (4) 03996 #define INT_SCTXUND_BITS (1) 03997 /* INT_SCRXOVF field */ 03998 #define INT_SCRXOVF (0x00000008u) 03999 #define INT_SCRXOVF_MASK (0x00000008u) 04000 #define INT_SCRXOVF_BIT (3) 04001 #define INT_SCRXOVF_BITS (1) 04002 /* INT_SCTXIDLE field */ 04003 #define INT_SCTXIDLE (0x00000004u) 04004 #define INT_SCTXIDLE_MASK (0x00000004u) 04005 #define INT_SCTXIDLE_BIT (2) 04006 #define INT_SCTXIDLE_BITS (1) 04007 /* INT_SCTXFREE field */ 04008 #define INT_SCTXFREE (0x00000002u) 04009 #define INT_SCTXFREE_MASK (0x00000002u) 04010 #define INT_SCTXFREE_BIT (1) 04011 #define INT_SCTXFREE_BITS (1) 04012 /* INT_SCRXVAL field */ 04013 #define INT_SCRXVAL (0x00000001u) 04014 #define INT_SCRXVAL_MASK (0x00000001u) 04015 #define INT_SCRXVAL_BIT (0) 04016 #define INT_SCRXVAL_BITS (1) 04017 04018 #define INT_ADCFLAG *((volatile int32u *)0x4000A810u) 04019 #define INT_ADCFLAG_REG *((volatile int32u *)0x4000A810u) 04020 #define INT_ADCFLAG_ADDR (0x4000A810u) 04021 #define INT_ADCFLAG_RESET (0x00000000u) 04022 /* INT_ADCOVF field */ 04023 #define INT_ADCOVF (0x00000010u) 04024 #define INT_ADCOVF_MASK (0x00000010u) 04025 #define INT_ADCOVF_BIT (4) 04026 #define INT_ADCOVF_BITS (1) 04027 /* INT_ADCSAT field */ 04028 #define INT_ADCSAT (0x00000008u) 04029 #define INT_ADCSAT_MASK (0x00000008u) 04030 #define INT_ADCSAT_BIT (3) 04031 #define INT_ADCSAT_BITS (1) 04032 /* INT_ADCULDFULL field */ 04033 #define INT_ADCULDFULL (0x00000004u) 04034 #define INT_ADCULDFULL_MASK (0x00000004u) 04035 #define INT_ADCULDFULL_BIT (2) 04036 #define INT_ADCULDFULL_BITS (1) 04037 /* INT_ADCULDHALF field */ 04038 #define INT_ADCULDHALF (0x00000002u) 04039 #define INT_ADCULDHALF_MASK (0x00000002u) 04040 #define INT_ADCULDHALF_BIT (1) 04041 #define INT_ADCULDHALF_BITS (1) 04042 /* INT_ADCFLAGRSVD field */ 04043 #define INT_ADCFLAGRSVD (0x00000001u) 04044 #define INT_ADCFLAGRSVD_MASK (0x00000001u) 04045 #define INT_ADCFLAGRSVD_BIT (0) 04046 #define INT_ADCFLAGRSVD_BITS (1) 04047 04048 #define INT_GPIOFLAG *((volatile int32u *)0x4000A814u) 04049 #define INT_GPIOFLAG_REG *((volatile int32u *)0x4000A814u) 04050 #define INT_GPIOFLAG_ADDR (0x4000A814u) 04051 #define INT_GPIOFLAG_RESET (0x00000000u) 04052 /* INT_IRQDFLAG field */ 04053 #define INT_IRQDFLAG (0x00000008u) 04054 #define INT_IRQDFLAG_MASK (0x00000008u) 04055 #define INT_IRQDFLAG_BIT (3) 04056 #define INT_IRQDFLAG_BITS (1) 04057 /* INT_IRQCFLAG field */ 04058 #define INT_IRQCFLAG (0x00000004u) 04059 #define INT_IRQCFLAG_MASK (0x00000004u) 04060 #define INT_IRQCFLAG_BIT (2) 04061 #define INT_IRQCFLAG_BITS (1) 04062 /* INT_IRQBFLAG field */ 04063 #define INT_IRQBFLAG (0x00000002u) 04064 #define INT_IRQBFLAG_MASK (0x00000002u) 04065 #define INT_IRQBFLAG_BIT (1) 04066 #define INT_IRQBFLAG_BITS (1) 04067 /* INT_IRQAFLAG field */ 04068 #define INT_IRQAFLAG (0x00000001u) 04069 #define INT_IRQAFLAG_MASK (0x00000001u) 04070 #define INT_IRQAFLAG_BIT (0) 04071 #define INT_IRQAFLAG_BITS (1) 04072 04073 #define INT_TIM1MISS *((volatile int32u *)0x4000A818u) 04074 #define INT_TIM1MISS_REG *((volatile int32u *)0x4000A818u) 04075 #define INT_TIM1MISS_ADDR (0x4000A818u) 04076 #define INT_TIM1MISS_RESET (0x00000000u) 04077 /* INT_TIMMISSCC4IF field */ 04078 #define INT_TIMMISSCC4IF (0x00001000u) 04079 #define INT_TIMMISSCC4IF_MASK (0x00001000u) 04080 #define INT_TIMMISSCC4IF_BIT (12) 04081 #define INT_TIMMISSCC4IF_BITS (1) 04082 /* INT_TIMMISSCC3IF field */ 04083 #define INT_TIMMISSCC3IF (0x00000800u) 04084 #define INT_TIMMISSCC3IF_MASK (0x00000800u) 04085 #define INT_TIMMISSCC3IF_BIT (11) 04086 #define INT_TIMMISSCC3IF_BITS (1) 04087 /* INT_TIMMISSCC2IF field */ 04088 #define INT_TIMMISSCC2IF (0x00000400u) 04089 #define INT_TIMMISSCC2IF_MASK (0x00000400u) 04090 #define INT_TIMMISSCC2IF_BIT (10) 04091 #define INT_TIMMISSCC2IF_BITS (1) 04092 /* INT_TIMMISSCC1IF field */ 04093 #define INT_TIMMISSCC1IF (0x00000200u) 04094 #define INT_TIMMISSCC1IF_MASK (0x00000200u) 04095 #define INT_TIMMISSCC1IF_BIT (9) 04096 #define INT_TIMMISSCC1IF_BITS (1) 04097 /* INT_TIMMISSRSVD field */ 04098 #define INT_TIMMISSRSVD (0x0000007Fu) 04099 #define INT_TIMMISSRSVD_MASK (0x0000007Fu) 04100 #define INT_TIMMISSRSVD_BIT (0) 04101 #define INT_TIMMISSRSVD_BITS (7) 04102 04103 #define INT_TIM2MISS *((volatile int32u *)0x4000A81Cu) 04104 #define INT_TIM2MISS_REG *((volatile int32u *)0x4000A81Cu) 04105 #define INT_TIM2MISS_ADDR (0x4000A81Cu) 04106 #define INT_TIM2MISS_RESET (0x00000000u) 04107 /* INT_TIMMISSCC4IF field */ 04108 #define INT_TIMMISSCC4IF (0x00001000u) 04109 #define INT_TIMMISSCC4IF_MASK (0x00001000u) 04110 #define INT_TIMMISSCC4IF_BIT (12) 04111 #define INT_TIMMISSCC4IF_BITS (1) 04112 /* INT_TIMMISSCC3IF field */ 04113 #define INT_TIMMISSCC3IF (0x00000800u) 04114 #define INT_TIMMISSCC3IF_MASK (0x00000800u) 04115 #define INT_TIMMISSCC3IF_BIT (11) 04116 #define INT_TIMMISSCC3IF_BITS (1) 04117 /* INT_TIMMISSCC2IF field */ 04118 #define INT_TIMMISSCC2IF (0x00000400u) 04119 #define INT_TIMMISSCC2IF_MASK (0x00000400u) 04120 #define INT_TIMMISSCC2IF_BIT (10) 04121 #define INT_TIMMISSCC2IF_BITS (1) 04122 /* INT_TIMMISSCC1IF field */ 04123 #define INT_TIMMISSCC1IF (0x00000200u) 04124 #define INT_TIMMISSCC1IF_MASK (0x00000200u) 04125 #define INT_TIMMISSCC1IF_BIT (9) 04126 #define INT_TIMMISSCC1IF_BITS (1) 04127 /* INT_TIMMISSRSVD field */ 04128 #define INT_TIMMISSRSVD (0x0000007Fu) 04129 #define INT_TIMMISSRSVD_MASK (0x0000007Fu) 04130 #define INT_TIMMISSRSVD_BIT (0) 04131 #define INT_TIMMISSRSVD_BITS (7) 04132 04133 #define INT_MISS *((volatile int32u *)0x4000A820u) 04134 #define INT_MISS_REG *((volatile int32u *)0x4000A820u) 04135 #define INT_MISS_ADDR (0x4000A820u) 04136 #define INT_MISS_RESET (0x00000000u) 04137 /* INT_MISSIRQD field */ 04138 #define INT_MISSIRQD (0x00008000u) 04139 #define INT_MISSIRQD_MASK (0x00008000u) 04140 #define INT_MISSIRQD_BIT (15) 04141 #define INT_MISSIRQD_BITS (1) 04142 /* INT_MISSIRQC field */ 04143 #define INT_MISSIRQC (0x00004000u) 04144 #define INT_MISSIRQC_MASK (0x00004000u) 04145 #define INT_MISSIRQC_BIT (14) 04146 #define INT_MISSIRQC_BITS (1) 04147 /* INT_MISSIRQB field */ 04148 #define INT_MISSIRQB (0x00002000u) 04149 #define INT_MISSIRQB_MASK (0x00002000u) 04150 #define INT_MISSIRQB_BIT (13) 04151 #define INT_MISSIRQB_BITS (1) 04152 /* INT_MISSIRQA field */ 04153 #define INT_MISSIRQA (0x00001000u) 04154 #define INT_MISSIRQA_MASK (0x00001000u) 04155 #define INT_MISSIRQA_BIT (12) 04156 #define INT_MISSIRQA_BITS (1) 04157 /* INT_MISSADC field */ 04158 #define INT_MISSADC (0x00000800u) 04159 #define INT_MISSADC_MASK (0x00000800u) 04160 #define INT_MISSADC_BIT (11) 04161 #define INT_MISSADC_BITS (1) 04162 /* INT_MISSMACRX field */ 04163 #define INT_MISSMACRX (0x00000400u) 04164 #define INT_MISSMACRX_MASK (0x00000400u) 04165 #define INT_MISSMACRX_BIT (10) 04166 #define INT_MISSMACRX_BITS (1) 04167 /* INT_MISSMACTX field */ 04168 #define INT_MISSMACTX (0x00000200u) 04169 #define INT_MISSMACTX_MASK (0x00000200u) 04170 #define INT_MISSMACTX_BIT (9) 04171 #define INT_MISSMACTX_BITS (1) 04172 /* INT_MISSMACTMR field */ 04173 #define INT_MISSMACTMR (0x00000100u) 04174 #define INT_MISSMACTMR_MASK (0x00000100u) 04175 #define INT_MISSMACTMR_BIT (8) 04176 #define INT_MISSMACTMR_BITS (1) 04177 /* INT_MISSSEC field */ 04178 #define INT_MISSSEC (0x00000080u) 04179 #define INT_MISSSEC_MASK (0x00000080u) 04180 #define INT_MISSSEC_BIT (7) 04181 #define INT_MISSSEC_BITS (1) 04182 /* INT_MISSSC2 field */ 04183 #define INT_MISSSC2 (0x00000040u) 04184 #define INT_MISSSC2_MASK (0x00000040u) 04185 #define INT_MISSSC2_BIT (6) 04186 #define INT_MISSSC2_BITS (1) 04187 /* INT_MISSSC1 field */ 04188 #define INT_MISSSC1 (0x00000020u) 04189 #define INT_MISSSC1_MASK (0x00000020u) 04190 #define INT_MISSSC1_BIT (5) 04191 #define INT_MISSSC1_BITS (1) 04192 /* INT_MISSSLEEP field */ 04193 #define INT_MISSSLEEP (0x00000010u) 04194 #define INT_MISSSLEEP_MASK (0x00000010u) 04195 #define INT_MISSSLEEP_BIT (4) 04196 #define INT_MISSSLEEP_BITS (1) 04197 /* INT_MISSBB field */ 04198 #define INT_MISSBB (0x00000008u) 04199 #define INT_MISSBB_MASK (0x00000008u) 04200 #define INT_MISSBB_BIT (3) 04201 #define INT_MISSBB_BITS (1) 04202 /* INT_MISSMGMT field */ 04203 #define INT_MISSMGMT (0x00000004u) 04204 #define INT_MISSMGMT_MASK (0x00000004u) 04205 #define INT_MISSMGMT_BIT (2) 04206 #define INT_MISSMGMT_BITS (1) 04207 04208 #define INT_TIM1CFG *((volatile int32u *)0x4000A840u) 04209 #define INT_TIM1CFG_REG *((volatile int32u *)0x4000A840u) 04210 #define INT_TIM1CFG_ADDR (0x4000A840u) 04211 #define INT_TIM1CFG_RESET (0x00000000u) 04212 /* INT_TIMTIF field */ 04213 #define INT_TIMTIF (0x00000040u) 04214 #define INT_TIMTIF_MASK (0x00000040u) 04215 #define INT_TIMTIF_BIT (6) 04216 #define INT_TIMTIF_BITS (1) 04217 /* INT_TIMCC4IF field */ 04218 #define INT_TIMCC4IF (0x00000010u) 04219 #define INT_TIMCC4IF_MASK (0x00000010u) 04220 #define INT_TIMCC4IF_BIT (4) 04221 #define INT_TIMCC4IF_BITS (1) 04222 /* INT_TIMCC3IF field */ 04223 #define INT_TIMCC3IF (0x00000008u) 04224 #define INT_TIMCC3IF_MASK (0x00000008u) 04225 #define INT_TIMCC3IF_BIT (3) 04226 #define INT_TIMCC3IF_BITS (1) 04227 /* INT_TIMCC2IF field */ 04228 #define INT_TIMCC2IF (0x00000004u) 04229 #define INT_TIMCC2IF_MASK (0x00000004u) 04230 #define INT_TIMCC2IF_BIT (2) 04231 #define INT_TIMCC2IF_BITS (1) 04232 /* INT_TIMCC1IF field */ 04233 #define INT_TIMCC1IF (0x00000002u) 04234 #define INT_TIMCC1IF_MASK (0x00000002u) 04235 #define INT_TIMCC1IF_BIT (1) 04236 #define INT_TIMCC1IF_BITS (1) 04237 /* INT_TIMUIF field */ 04238 #define INT_TIMUIF (0x00000001u) 04239 #define INT_TIMUIF_MASK (0x00000001u) 04240 #define INT_TIMUIF_BIT (0) 04241 #define INT_TIMUIF_BITS (1) 04242 04243 #define INT_TIM2CFG *((volatile int32u *)0x4000A844u) 04244 #define INT_TIM2CFG_REG *((volatile int32u *)0x4000A844u) 04245 #define INT_TIM2CFG_ADDR (0x4000A844u) 04246 #define INT_TIM2CFG_RESET (0x00000000u) 04247 /* INT_TIMTIF field */ 04248 #define INT_TIMTIF (0x00000040u) 04249 #define INT_TIMTIF_MASK (0x00000040u) 04250 #define INT_TIMTIF_BIT (6) 04251 #define INT_TIMTIF_BITS (1) 04252 /* INT_TIMCC4IF field */ 04253 #define INT_TIMCC4IF (0x00000010u) 04254 #define INT_TIMCC4IF_MASK (0x00000010u) 04255 #define INT_TIMCC4IF_BIT (4) 04256 #define INT_TIMCC4IF_BITS (1) 04257 /* INT_TIMCC3IF field */ 04258 #define INT_TIMCC3IF (0x00000008u) 04259 #define INT_TIMCC3IF_MASK (0x00000008u) 04260 #define INT_TIMCC3IF_BIT (3) 04261 #define INT_TIMCC3IF_BITS (1) 04262 /* INT_TIMCC2IF field */ 04263 #define INT_TIMCC2IF (0x00000004u) 04264 #define INT_TIMCC2IF_MASK (0x00000004u) 04265 #define INT_TIMCC2IF_BIT (2) 04266 #define INT_TIMCC2IF_BITS (1) 04267 /* INT_TIMCC1IF field */ 04268 #define INT_TIMCC1IF (0x00000002u) 04269 #define INT_TIMCC1IF_MASK (0x00000002u) 04270 #define INT_TIMCC1IF_BIT (1) 04271 #define INT_TIMCC1IF_BITS (1) 04272 /* INT_TIMUIF field */ 04273 #define INT_TIMUIF (0x00000001u) 04274 #define INT_TIMUIF_MASK (0x00000001u) 04275 #define INT_TIMUIF_BIT (0) 04276 #define INT_TIMUIF_BITS (1) 04277 04278 #define INT_SC1CFG *((volatile int32u *)0x4000A848u) 04279 #define INT_SC1CFG_REG *((volatile int32u *)0x4000A848u) 04280 #define INT_SC1CFG_ADDR (0x4000A848u) 04281 #define INT_SC1CFG_RESET (0x00000000u) 04282 /* INT_SC1PARERR field */ 04283 #define INT_SC1PARERR (0x00004000u) 04284 #define INT_SC1PARERR_MASK (0x00004000u) 04285 #define INT_SC1PARERR_BIT (14) 04286 #define INT_SC1PARERR_BITS (1) 04287 /* INT_SC1FRMERR field */ 04288 #define INT_SC1FRMERR (0x00002000u) 04289 #define INT_SC1FRMERR_MASK (0x00002000u) 04290 #define INT_SC1FRMERR_BIT (13) 04291 #define INT_SC1FRMERR_BITS (1) 04292 /* INT_SCTXULDB field */ 04293 #define INT_SCTXULDB (0x00001000u) 04294 #define INT_SCTXULDB_MASK (0x00001000u) 04295 #define INT_SCTXULDB_BIT (12) 04296 #define INT_SCTXULDB_BITS (1) 04297 /* INT_SCTXULDA field */ 04298 #define INT_SCTXULDA (0x00000800u) 04299 #define INT_SCTXULDA_MASK (0x00000800u) 04300 #define INT_SCTXULDA_BIT (11) 04301 #define INT_SCTXULDA_BITS (1) 04302 /* INT_SCRXULDB field */ 04303 #define INT_SCRXULDB (0x00000400u) 04304 #define INT_SCRXULDB_MASK (0x00000400u) 04305 #define INT_SCRXULDB_BIT (10) 04306 #define INT_SCRXULDB_BITS (1) 04307 /* INT_SCRXULDA field */ 04308 #define INT_SCRXULDA (0x00000200u) 04309 #define INT_SCRXULDA_MASK (0x00000200u) 04310 #define INT_SCRXULDA_BIT (9) 04311 #define INT_SCRXULDA_BITS (1) 04312 /* INT_SCNAK field */ 04313 #define INT_SCNAK (0x00000100u) 04314 #define INT_SCNAK_MASK (0x00000100u) 04315 #define INT_SCNAK_BIT (8) 04316 #define INT_SCNAK_BITS (1) 04317 /* INT_SCCMDFIN field */ 04318 #define INT_SCCMDFIN (0x00000080u) 04319 #define INT_SCCMDFIN_MASK (0x00000080u) 04320 #define INT_SCCMDFIN_BIT (7) 04321 #define INT_SCCMDFIN_BITS (1) 04322 /* INT_SCTXFIN field */ 04323 #define INT_SCTXFIN (0x00000040u) 04324 #define INT_SCTXFIN_MASK (0x00000040u) 04325 #define INT_SCTXFIN_BIT (6) 04326 #define INT_SCTXFIN_BITS (1) 04327 /* INT_SCRXFIN field */ 04328 #define INT_SCRXFIN (0x00000020u) 04329 #define INT_SCRXFIN_MASK (0x00000020u) 04330 #define INT_SCRXFIN_BIT (5) 04331 #define INT_SCRXFIN_BITS (1) 04332 /* INT_SCTXUND field */ 04333 #define INT_SCTXUND (0x00000010u) 04334 #define INT_SCTXUND_MASK (0x00000010u) 04335 #define INT_SCTXUND_BIT (4) 04336 #define INT_SCTXUND_BITS (1) 04337 /* INT_SCRXOVF field */ 04338 #define INT_SCRXOVF (0x00000008u) 04339 #define INT_SCRXOVF_MASK (0x00000008u) 04340 #define INT_SCRXOVF_BIT (3) 04341 #define INT_SCRXOVF_BITS (1) 04342 /* INT_SCTXIDLE field */ 04343 #define INT_SCTXIDLE (0x00000004u) 04344 #define INT_SCTXIDLE_MASK (0x00000004u) 04345 #define INT_SCTXIDLE_BIT (2) 04346 #define INT_SCTXIDLE_BITS (1) 04347 /* INT_SCTXFREE field */ 04348 #define INT_SCTXFREE (0x00000002u) 04349 #define INT_SCTXFREE_MASK (0x00000002u) 04350 #define INT_SCTXFREE_BIT (1) 04351 #define INT_SCTXFREE_BITS (1) 04352 /* INT_SCRXVAL field */ 04353 #define INT_SCRXVAL (0x00000001u) 04354 #define INT_SCRXVAL_MASK (0x00000001u) 04355 #define INT_SCRXVAL_BIT (0) 04356 #define INT_SCRXVAL_BITS (1) 04357 04358 #define INT_SC2CFG *((volatile int32u *)0x4000A84Cu) 04359 #define INT_SC2CFG_REG *((volatile int32u *)0x4000A84Cu) 04360 #define INT_SC2CFG_ADDR (0x4000A84Cu) 04361 #define INT_SC2CFG_RESET (0x00000000u) 04362 /* INT_SCTXULDB field */ 04363 #define INT_SCTXULDB (0x00001000u) 04364 #define INT_SCTXULDB_MASK (0x00001000u) 04365 #define INT_SCTXULDB_BIT (12) 04366 #define INT_SCTXULDB_BITS (1) 04367 /* INT_SCTXULDA field */ 04368 #define INT_SCTXULDA (0x00000800u) 04369 #define INT_SCTXULDA_MASK (0x00000800u) 04370 #define INT_SCTXULDA_BIT (11) 04371 #define INT_SCTXULDA_BITS (1) 04372 /* INT_SCRXULDB field */ 04373 #define INT_SCRXULDB (0x00000400u) 04374 #define INT_SCRXULDB_MASK (0x00000400u) 04375 #define INT_SCRXULDB_BIT (10) 04376 #define INT_SCRXULDB_BITS (1) 04377 /* INT_SCRXULDA field */ 04378 #define INT_SCRXULDA (0x00000200u) 04379 #define INT_SCRXULDA_MASK (0x00000200u) 04380 #define INT_SCRXULDA_BIT (9) 04381 #define INT_SCRXULDA_BITS (1) 04382 /* INT_SCNAK field */ 04383 #define INT_SCNAK (0x00000100u) 04384 #define INT_SCNAK_MASK (0x00000100u) 04385 #define INT_SCNAK_BIT (8) 04386 #define INT_SCNAK_BITS (1) 04387 /* INT_SCCMDFIN field */ 04388 #define INT_SCCMDFIN (0x00000080u) 04389 #define INT_SCCMDFIN_MASK (0x00000080u) 04390 #define INT_SCCMDFIN_BIT (7) 04391 #define INT_SCCMDFIN_BITS (1) 04392 /* INT_SCTXFIN field */ 04393 #define INT_SCTXFIN (0x00000040u) 04394 #define INT_SCTXFIN_MASK (0x00000040u) 04395 #define INT_SCTXFIN_BIT (6) 04396 #define INT_SCTXFIN_BITS (1) 04397 /* INT_SCRXFIN field */ 04398 #define INT_SCRXFIN (0x00000020u) 04399 #define INT_SCRXFIN_MASK (0x00000020u) 04400 #define INT_SCRXFIN_BIT (5) 04401 #define INT_SCRXFIN_BITS (1) 04402 /* INT_SCTXUND field */ 04403 #define INT_SCTXUND (0x00000010u) 04404 #define INT_SCTXUND_MASK (0x00000010u) 04405 #define INT_SCTXUND_BIT (4) 04406 #define INT_SCTXUND_BITS (1) 04407 /* INT_SCRXOVF field */ 04408 #define INT_SCRXOVF (0x00000008u) 04409 #define INT_SCRXOVF_MASK (0x00000008u) 04410 #define INT_SCRXOVF_BIT (3) 04411 #define INT_SCRXOVF_BITS (1) 04412 /* INT_SCTXIDLE field */ 04413 #define INT_SCTXIDLE (0x00000004u) 04414 #define INT_SCTXIDLE_MASK (0x00000004u) 04415 #define INT_SCTXIDLE_BIT (2) 04416 #define INT_SCTXIDLE_BITS (1) 04417 /* INT_SCTXFREE field */ 04418 #define INT_SCTXFREE (0x00000002u) 04419 #define INT_SCTXFREE_MASK (0x00000002u) 04420 #define INT_SCTXFREE_BIT (1) 04421 #define INT_SCTXFREE_BITS (1) 04422 /* INT_SCRXVAL field */ 04423 #define INT_SCRXVAL (0x00000001u) 04424 #define INT_SCRXVAL_MASK (0x00000001u) 04425 #define INT_SCRXVAL_BIT (0) 04426 #define INT_SCRXVAL_BITS (1) 04427 04428 #define INT_ADCCFG *((volatile int32u *)0x4000A850u) 04429 #define INT_ADCCFG_REG *((volatile int32u *)0x4000A850u) 04430 #define INT_ADCCFG_ADDR (0x4000A850u) 04431 #define INT_ADCCFG_RESET (0x00000000u) 04432 /* INT_ADCOVF field */ 04433 #define INT_ADCOVF (0x00000010u) 04434 #define INT_ADCOVF_MASK (0x00000010u) 04435 #define INT_ADCOVF_BIT (4) 04436 #define INT_ADCOVF_BITS (1) 04437 /* INT_ADCSAT field */ 04438 #define INT_ADCSAT (0x00000008u) 04439 #define INT_ADCSAT_MASK (0x00000008u) 04440 #define INT_ADCSAT_BIT (3) 04441 #define INT_ADCSAT_BITS (1) 04442 /* INT_ADCULDFULL field */ 04443 #define INT_ADCULDFULL (0x00000004u) 04444 #define INT_ADCULDFULL_MASK (0x00000004u) 04445 #define INT_ADCULDFULL_BIT (2) 04446 #define INT_ADCULDFULL_BITS (1) 04447 /* INT_ADCULDHALF field */ 04448 #define INT_ADCULDHALF (0x00000002u) 04449 #define INT_ADCULDHALF_MASK (0x00000002u) 04450 #define INT_ADCULDHALF_BIT (1) 04451 #define INT_ADCULDHALF_BITS (1) 04452 /* INT_ADCCFGRSVD field */ 04453 #define INT_ADCCFGRSVD (0x00000001u) 04454 #define INT_ADCCFGRSVD_MASK (0x00000001u) 04455 #define INT_ADCCFGRSVD_BIT (0) 04456 #define INT_ADCCFGRSVD_BITS (1) 04457 04458 #define SC1_INTMODE *((volatile int32u *)0x4000A854u) 04459 #define SC1_INTMODE_REG *((volatile int32u *)0x4000A854u) 04460 #define SC1_INTMODE_ADDR (0x4000A854u) 04461 #define SC1_INTMODE_RESET (0x00000000u) 04462 /* SC_TXIDLELEVEL field */ 04463 #define SC_TXIDLELEVEL (0x00000004u) 04464 #define SC_TXIDLELEVEL_MASK (0x00000004u) 04465 #define SC_TXIDLELEVEL_BIT (2) 04466 #define SC_TXIDLELEVEL_BITS (1) 04467 /* SC_TXFREELEVEL field */ 04468 #define SC_TXFREELEVEL (0x00000002u) 04469 #define SC_TXFREELEVEL_MASK (0x00000002u) 04470 #define SC_TXFREELEVEL_BIT (1) 04471 #define SC_TXFREELEVEL_BITS (1) 04472 /* SC_RXVALLEVEL field */ 04473 #define SC_RXVALLEVEL (0x00000001u) 04474 #define SC_RXVALLEVEL_MASK (0x00000001u) 04475 #define SC_RXVALLEVEL_BIT (0) 04476 #define SC_RXVALLEVEL_BITS (1) 04477 04478 #define SC2_INTMODE *((volatile int32u *)0x4000A858u) 04479 #define SC2_INTMODE_REG *((volatile int32u *)0x4000A858u) 04480 #define SC2_INTMODE_ADDR (0x4000A858u) 04481 #define SC2_INTMODE_RESET (0x00000000u) 04482 /* SC_TXIDLELEVEL field */ 04483 #define SC_TXIDLELEVEL (0x00000004u) 04484 #define SC_TXIDLELEVEL_MASK (0x00000004u) 04485 #define SC_TXIDLELEVEL_BIT (2) 04486 #define SC_TXIDLELEVEL_BITS (1) 04487 /* SC_TXFREELEVEL field */ 04488 #define SC_TXFREELEVEL (0x00000002u) 04489 #define SC_TXFREELEVEL_MASK (0x00000002u) 04490 #define SC_TXFREELEVEL_BIT (1) 04491 #define SC_TXFREELEVEL_BITS (1) 04492 /* SC_RXVALLEVEL field */ 04493 #define SC_RXVALLEVEL (0x00000001u) 04494 #define SC_RXVALLEVEL_MASK (0x00000001u) 04495 #define SC_RXVALLEVEL_BIT (0) 04496 #define SC_RXVALLEVEL_BITS (1) 04497 04498 #define GPIO_INTCFGA *((volatile int32u *)0x4000A860u) 04499 #define GPIO_INTCFGA_REG *((volatile int32u *)0x4000A860u) 04500 #define GPIO_INTCFGA_ADDR (0x4000A860u) 04501 #define GPIO_INTCFGA_RESET (0x00000000u) 04502 /* GPIO_INTFILT field */ 04503 #define GPIO_INTFILT (0x00000100u) 04504 #define GPIO_INTFILT_MASK (0x00000100u) 04505 #define GPIO_INTFILT_BIT (8) 04506 #define GPIO_INTFILT_BITS (1) 04507 /* GPIO_INTMOD field */ 04508 #define GPIO_INTMOD (0x000000E0u) 04509 #define GPIO_INTMOD_MASK (0x000000E0u) 04510 #define GPIO_INTMOD_BIT (5) 04511 #define GPIO_INTMOD_BITS (3) 04512 04513 #define GPIO_INTCFGB *((volatile int32u *)0x4000A864u) 04514 #define GPIO_INTCFGB_REG *((volatile int32u *)0x4000A864u) 04515 #define GPIO_INTCFGB_ADDR (0x4000A864u) 04516 #define GPIO_INTCFGB_RESET (0x00000000u) 04517 /* GPIO_INTFILT field */ 04518 #define GPIO_INTFILT (0x00000100u) 04519 #define GPIO_INTFILT_MASK (0x00000100u) 04520 #define GPIO_INTFILT_BIT (8) 04521 #define GPIO_INTFILT_BITS (1) 04522 /* GPIO_INTMOD field */ 04523 #define GPIO_INTMOD (0x000000E0u) 04524 #define GPIO_INTMOD_MASK (0x000000E0u) 04525 #define GPIO_INTMOD_BIT (5) 04526 #define GPIO_INTMOD_BITS (3) 04527 04528 #define GPIO_INTCFGC *((volatile int32u *)0x4000A868u) 04529 #define GPIO_INTCFGC_REG *((volatile int32u *)0x4000A868u) 04530 #define GPIO_INTCFGC_ADDR (0x4000A868u) 04531 #define GPIO_INTCFGC_RESET (0x00000000u) 04532 /* GPIO_INTFILT field */ 04533 #define GPIO_INTFILT (0x00000100u) 04534 #define GPIO_INTFILT_MASK (0x00000100u) 04535 #define GPIO_INTFILT_BIT (8) 04536 #define GPIO_INTFILT_BITS (1) 04537 /* GPIO_INTMOD field */ 04538 #define GPIO_INTMOD (0x000000E0u) 04539 #define GPIO_INTMOD_MASK (0x000000E0u) 04540 #define GPIO_INTMOD_BIT (5) 04541 #define GPIO_INTMOD_BITS (3) 04542 04543 #define GPIO_INTCFGD *((volatile int32u *)0x4000A86Cu) 04544 #define GPIO_INTCFGD_REG *((volatile int32u *)0x4000A86Cu) 04545 #define GPIO_INTCFGD_ADDR (0x4000A86Cu) 04546 #define GPIO_INTCFGD_RESET (0x00000000u) 04547 /* GPIO_INTFILT field */ 04548 #define GPIO_INTFILT (0x00000100u) 04549 #define GPIO_INTFILT_MASK (0x00000100u) 04550 #define GPIO_INTFILT_BIT (8) 04551 #define GPIO_INTFILT_BITS (1) 04552 /* GPIO_INTMOD field */ 04553 #define GPIO_INTMOD (0x000000E0u) 04554 #define GPIO_INTMOD_MASK (0x000000E0u) 04555 #define GPIO_INTMOD_BIT (5) 04556 #define GPIO_INTMOD_BITS (3) 04557 04558 /* GPIO block */ 04559 #define BLOCK_GPIO_BASE (0x4000B000u) 04560 #define BLOCK_GPIO_END (0x4000BC1Cu) 04561 #define BLOCK_GPIO_SIZE (BLOCK_GPIO_END - BLOCK_GPIO_BASE + 1) 04562 04563 #define GPIO_PACFGL *((volatile int32u *)0x4000B000u) 04564 #define GPIO_PACFGL_REG *((volatile int32u *)0x4000B000u) 04565 #define GPIO_PACFGL_ADDR (0x4000B000u) 04566 #define GPIO_PACFGL_RESET (0x00004444u) 04567 /* PA3_CFG field */ 04568 #define PA3_CFG (0x0000F000u) 04569 #define PA3_CFG_MASK (0x0000F000u) 04570 #define PA3_CFG_BIT (12) 04571 #define PA3_CFG_BITS (4) 04572 /* PA2_CFG field */ 04573 #define PA2_CFG (0x00000F00u) 04574 #define PA2_CFG_MASK (0x00000F00u) 04575 #define PA2_CFG_BIT (8) 04576 #define PA2_CFG_BITS (4) 04577 /* PA1_CFG field */ 04578 #define PA1_CFG (0x000000F0u) 04579 #define PA1_CFG_MASK (0x000000F0u) 04580 #define PA1_CFG_BIT (4) 04581 #define PA1_CFG_BITS (4) 04582 /* PA0_CFG field */ 04583 #define PA0_CFG (0x0000000Fu) 04584 #define PA0_CFG_MASK (0x0000000Fu) 04585 #define PA0_CFG_BIT (0) 04586 #define PA0_CFG_BITS (4) 04587 /* GPIO_PxCFGx Bit Field Values */ 04588 #define GPIOCFG_OUT (0x1u) 04589 #define GPIOCFG_OUT_OD (0x5u) 04590 #define GPIOCFG_OUT_ALT (0x9u) 04591 #define GPIOCFG_OUT_ALT_OD (0xDu) 04592 #define GPIOCFG_ANALOG (0x0u) 04593 #define GPIOCFG_IN (0x4u) 04594 #define GPIOCFG_IN_PUD (0x8u) 04595 04596 #define GPIO_PACFGH *((volatile int32u *)0x4000B004u) 04597 #define GPIO_PACFGH_REG *((volatile int32u *)0x4000B004u) 04598 #define GPIO_PACFGH_ADDR (0x4000B004u) 04599 #define GPIO_PACFGH_RESET (0x00004444u) 04600 /* PA7_CFG field */ 04601 #define PA7_CFG (0x0000F000u) 04602 #define PA7_CFG_MASK (0x0000F000u) 04603 #define PA7_CFG_BIT (12) 04604 #define PA7_CFG_BITS (4) 04605 /* PA6_CFG field */ 04606 #define PA6_CFG (0x00000F00u) 04607 #define PA6_CFG_MASK (0x00000F00u) 04608 #define PA6_CFG_BIT (8) 04609 #define PA6_CFG_BITS (4) 04610 /* PA5_CFG field */ 04611 #define PA5_CFG (0x000000F0u) 04612 #define PA5_CFG_MASK (0x000000F0u) 04613 #define PA5_CFG_BIT (4) 04614 #define PA5_CFG_BITS (4) 04615 /* PA4_CFG field */ 04616 #define PA4_CFG (0x0000000Fu) 04617 #define PA4_CFG_MASK (0x0000000Fu) 04618 #define PA4_CFG_BIT (0) 04619 #define PA4_CFG_BITS (4) 04620 04621 #define GPIO_PAIN *((volatile int32u *)0x4000B008u) 04622 #define GPIO_PAIN_REG *((volatile int32u *)0x4000B008u) 04623 #define GPIO_PAIN_ADDR (0x4000B008u) 04624 #define GPIO_PAIN_RESET (0x00000000u) 04625 /* PA7 field */ 04626 #define PA7 (0x00000080u) 04627 #define PA7_MASK (0x00000080u) 04628 #define PA7_BIT (7) 04629 #define PA7_BITS (1) 04630 /* PA6 field */ 04631 #define PA6 (0x00000040u) 04632 #define PA6_MASK (0x00000040u) 04633 #define PA6_BIT (6) 04634 #define PA6_BITS (1) 04635 /* PA5 field */ 04636 #define PA5 (0x00000020u) 04637 #define PA5_MASK (0x00000020u) 04638 #define PA5_BIT (5) 04639 #define PA5_BITS (1) 04640 /* PA4 field */ 04641 #define PA4 (0x00000010u) 04642 #define PA4_MASK (0x00000010u) 04643 #define PA4_BIT (4) 04644 #define PA4_BITS (1) 04645 /* PA3 field */ 04646 #define PA3 (0x00000008u) 04647 #define PA3_MASK (0x00000008u) 04648 #define PA3_BIT (3) 04649 #define PA3_BITS (1) 04650 /* PA2 field */ 04651 #define PA2 (0x00000004u) 04652 #define PA2_MASK (0x00000004u) 04653 #define PA2_BIT (2) 04654 #define PA2_BITS (1) 04655 /* PA1 field */ 04656 #define PA1 (0x00000002u) 04657 #define PA1_MASK (0x00000002u) 04658 #define PA1_BIT (1) 04659 #define PA1_BITS (1) 04660 /* PA0 field */ 04661 #define PA0 (0x00000001u) 04662 #define PA0_MASK (0x00000001u) 04663 #define PA0_BIT (0) 04664 #define PA0_BITS (1) 04665 04666 #define GPIO_PAOUT *((volatile int32u *)0x4000B00Cu) 04667 #define GPIO_PAOUT_REG *((volatile int32u *)0x4000B00Cu) 04668 #define GPIO_PAOUT_ADDR (0x4000B00Cu) 04669 #define GPIO_PAOUT_RESET (0x00000000u) 04670 /* PA7 field */ 04671 #define PA7 (0x00000080u) 04672 #define PA7_MASK (0x00000080u) 04673 #define PA7_BIT (7) 04674 #define PA7_BITS (1) 04675 /* PA6 field */ 04676 #define PA6 (0x00000040u) 04677 #define PA6_MASK (0x00000040u) 04678 #define PA6_BIT (6) 04679 #define PA6_BITS (1) 04680 /* PA5 field */ 04681 #define PA5 (0x00000020u) 04682 #define PA5_MASK (0x00000020u) 04683 #define PA5_BIT (5) 04684 #define PA5_BITS (1) 04685 /* PA4 field */ 04686 #define PA4 (0x00000010u) 04687 #define PA4_MASK (0x00000010u) 04688 #define PA4_BIT (4) 04689 #define PA4_BITS (1) 04690 /* PA3 field */ 04691 #define PA3 (0x00000008u) 04692 #define PA3_MASK (0x00000008u) 04693 #define PA3_BIT (3) 04694 #define PA3_BITS (1) 04695 /* PA2 field */ 04696 #define PA2 (0x00000004u) 04697 #define PA2_MASK (0x00000004u) 04698 #define PA2_BIT (2) 04699 #define PA2_BITS (1) 04700 /* PA1 field */ 04701 #define PA1 (0x00000002u) 04702 #define PA1_MASK (0x00000002u) 04703 #define PA1_BIT (1) 04704 #define PA1_BITS (1) 04705 /* PA0 field */ 04706 #define PA0 (0x00000001u) 04707 #define PA0_MASK (0x00000001u) 04708 #define PA0_BIT (0) 04709 #define PA0_BITS (1) 04710 /* GPIO_PxOUT Bit Field Values */ 04711 #define GPIOOUT_PULLUP (0x1u) 04712 #define GPIOOUT_PULLDOWN (0x0u) 04713 04714 #define GPIO_PASET *((volatile int32u *)0x4000B010u) 04715 #define GPIO_PASET_REG *((volatile int32u *)0x4000B010u) 04716 #define GPIO_PASET_ADDR (0x4000B010u) 04717 #define GPIO_PASET_RESET (0x00000000u) 04718 /* GPIO_PXSETRSVD field */ 04719 #define GPIO_PXSETRSVD (0x0000FF00u) 04720 #define GPIO_PXSETRSVD_MASK (0x0000FF00u) 04721 #define GPIO_PXSETRSVD_BIT (8) 04722 #define GPIO_PXSETRSVD_BITS (8) 04723 /* PA7 field */ 04724 #define PA7 (0x00000080u) 04725 #define PA7_MASK (0x00000080u) 04726 #define PA7_BIT (7) 04727 #define PA7_BITS (1) 04728 /* PA6 field */ 04729 #define PA6 (0x00000040u) 04730 #define PA6_MASK (0x00000040u) 04731 #define PA6_BIT (6) 04732 #define PA6_BITS (1) 04733 /* PA5 field */ 04734 #define PA5 (0x00000020u) 04735 #define PA5_MASK (0x00000020u) 04736 #define PA5_BIT (5) 04737 #define PA5_BITS (1) 04738 /* PA4 field */ 04739 #define PA4 (0x00000010u) 04740 #define PA4_MASK (0x00000010u) 04741 #define PA4_BIT (4) 04742 #define PA4_BITS (1) 04743 /* PA3 field */ 04744 #define PA3 (0x00000008u) 04745 #define PA3_MASK (0x00000008u) 04746 #define PA3_BIT (3) 04747 #define PA3_BITS (1) 04748 /* PA2 field */ 04749 #define PA2 (0x00000004u) 04750 #define PA2_MASK (0x00000004u) 04751 #define PA2_BIT (2) 04752 #define PA2_BITS (1) 04753 /* PA1 field */ 04754 #define PA1 (0x00000002u) 04755 #define PA1_MASK (0x00000002u) 04756 #define PA1_BIT (1) 04757 #define PA1_BITS (1) 04758 /* PA0 field */ 04759 #define PA0 (0x00000001u) 04760 #define PA0_MASK (0x00000001u) 04761 #define PA0_BIT (0) 04762 #define PA0_BITS (1) 04763 04764 #define GPIO_PACLR *((volatile int32u *)0x4000B014u) 04765 #define GPIO_PACLR_REG *((volatile int32u *)0x4000B014u) 04766 #define GPIO_PACLR_ADDR (0x4000B014u) 04767 #define GPIO_PACLR_RESET (0x00000000u) 04768 /* PA7 field */ 04769 #define PA7 (0x00000080u) 04770 #define PA7_MASK (0x00000080u) 04771 #define PA7_BIT (7) 04772 #define PA7_BITS (1) 04773 /* PA6 field */ 04774 #define PA6 (0x00000040u) 04775 #define PA6_MASK (0x00000040u) 04776 #define PA6_BIT (6) 04777 #define PA6_BITS (1) 04778 /* PA5 field */ 04779 #define PA5 (0x00000020u) 04780 #define PA5_MASK (0x00000020u) 04781 #define PA5_BIT (5) 04782 #define PA5_BITS (1) 04783 /* PA4 field */ 04784 #define PA4 (0x00000010u) 04785 #define PA4_MASK (0x00000010u) 04786 #define PA4_BIT (4) 04787 #define PA4_BITS (1) 04788 /* PA3 field */ 04789 #define PA3 (0x00000008u) 04790 #define PA3_MASK (0x00000008u) 04791 #define PA3_BIT (3) 04792 #define PA3_BITS (1) 04793 /* PA2 field */ 04794 #define PA2 (0x00000004u) 04795 #define PA2_MASK (0x00000004u) 04796 #define PA2_BIT (2) 04797 #define PA2_BITS (1) 04798 /* PA1 field */ 04799 #define PA1 (0x00000002u) 04800 #define PA1_MASK (0x00000002u) 04801 #define PA1_BIT (1) 04802 #define PA1_BITS (1) 04803 /* PA0 field */ 04804 #define PA0 (0x00000001u) 04805 #define PA0_MASK (0x00000001u) 04806 #define PA0_BIT (0) 04807 #define PA0_BITS (1) 04808 04809 #define GPIO_PBCFGL *((volatile int32u *)0x4000B400u) 04810 #define GPIO_PBCFGL_REG *((volatile int32u *)0x4000B400u) 04811 #define GPIO_PBCFGL_ADDR (0x4000B400u) 04812 #define GPIO_PBCFGL_RESET (0x00004444u) 04813 /* PB3_CFG field */ 04814 #define PB3_CFG (0x0000F000u) 04815 #define PB3_CFG_MASK (0x0000F000u) 04816 #define PB3_CFG_BIT (12) 04817 #define PB3_CFG_BITS (4) 04818 /* PB2_CFG field */ 04819 #define PB2_CFG (0x00000F00u) 04820 #define PB2_CFG_MASK (0x00000F00u) 04821 #define PB2_CFG_BIT (8) 04822 #define PB2_CFG_BITS (4) 04823 /* PB1_CFG field */ 04824 #define PB1_CFG (0x000000F0u) 04825 #define PB1_CFG_MASK (0x000000F0u) 04826 #define PB1_CFG_BIT (4) 04827 #define PB1_CFG_BITS (4) 04828 /* PB0_CFG field */ 04829 #define PB0_CFG (0x0000000Fu) 04830 #define PB0_CFG_MASK (0x0000000Fu) 04831 #define PB0_CFG_BIT (0) 04832 #define PB0_CFG_BITS (4) 04833 04834 #define GPIO_PBCFGH *((volatile int32u *)0x4000B404u) 04835 #define GPIO_PBCFGH_REG *((volatile int32u *)0x4000B404u) 04836 #define GPIO_PBCFGH_ADDR (0x4000B404u) 04837 #define GPIO_PBCFGH_RESET (0x00004444u) 04838 /* PB7_CFG field */ 04839 #define PB7_CFG (0x0000F000u) 04840 #define PB7_CFG_MASK (0x0000F000u) 04841 #define PB7_CFG_BIT (12) 04842 #define PB7_CFG_BITS (4) 04843 /* PB6_CFG field */ 04844 #define PB6_CFG (0x00000F00u) 04845 #define PB6_CFG_MASK (0x00000F00u) 04846 #define PB6_CFG_BIT (8) 04847 #define PB6_CFG_BITS (4) 04848 /* PB5_CFG field */ 04849 #define PB5_CFG (0x000000F0u) 04850 #define PB5_CFG_MASK (0x000000F0u) 04851 #define PB5_CFG_BIT (4) 04852 #define PB5_CFG_BITS (4) 04853 /* PB4_CFG field */ 04854 #define PB4_CFG (0x0000000Fu) 04855 #define PB4_CFG_MASK (0x0000000Fu) 04856 #define PB4_CFG_BIT (0) 04857 #define PB4_CFG_BITS (4) 04858 04859 #define GPIO_PBIN *((volatile int32u *)0x4000B408u) 04860 #define GPIO_PBIN_REG *((volatile int32u *)0x4000B408u) 04861 #define GPIO_PBIN_ADDR (0x4000B408u) 04862 #define GPIO_PBIN_RESET (0x00000000u) 04863 /* PB7 field */ 04864 #define PB7 (0x00000080u) 04865 #define PB7_MASK (0x00000080u) 04866 #define PB7_BIT (7) 04867 #define PB7_BITS (1) 04868 /* PB6 field */ 04869 #define PB6 (0x00000040u) 04870 #define PB6_MASK (0x00000040u) 04871 #define PB6_BIT (6) 04872 #define PB6_BITS (1) 04873 /* PB5 field */ 04874 #define PB5 (0x00000020u) 04875 #define PB5_MASK (0x00000020u) 04876 #define PB5_BIT (5) 04877 #define PB5_BITS (1) 04878 /* PB4 field */ 04879 #define PB4 (0x00000010u) 04880 #define PB4_MASK (0x00000010u) 04881 #define PB4_BIT (4) 04882 #define PB4_BITS (1) 04883 /* PB3 field */ 04884 #define PB3 (0x00000008u) 04885 #define PB3_MASK (0x00000008u) 04886 #define PB3_BIT (3) 04887 #define PB3_BITS (1) 04888 /* PB2 field */ 04889 #define PB2 (0x00000004u) 04890 #define PB2_MASK (0x00000004u) 04891 #define PB2_BIT (2) 04892 #define PB2_BITS (1) 04893 /* PB1 field */ 04894 #define PB1 (0x00000002u) 04895 #define PB1_MASK (0x00000002u) 04896 #define PB1_BIT (1) 04897 #define PB1_BITS (1) 04898 /* PB0 field */ 04899 #define PB0 (0x00000001u) 04900 #define PB0_MASK (0x00000001u) 04901 #define PB0_BIT (0) 04902 #define PB0_BITS (1) 04903 04904 #define GPIO_PBOUT *((volatile int32u *)0x4000B40Cu) 04905 #define GPIO_PBOUT_REG *((volatile int32u *)0x4000B40Cu) 04906 #define GPIO_PBOUT_ADDR (0x4000B40Cu) 04907 #define GPIO_PBOUT_RESET (0x00000000u) 04908 /* PB7 field */ 04909 #define PB7 (0x00000080u) 04910 #define PB7_MASK (0x00000080u) 04911 #define PB7_BIT (7) 04912 #define PB7_BITS (1) 04913 /* PB6 field */ 04914 #define PB6 (0x00000040u) 04915 #define PB6_MASK (0x00000040u) 04916 #define PB6_BIT (6) 04917 #define PB6_BITS (1) 04918 /* PB5 field */ 04919 #define PB5 (0x00000020u) 04920 #define PB5_MASK (0x00000020u) 04921 #define PB5_BIT (5) 04922 #define PB5_BITS (1) 04923 /* PB4 field */ 04924 #define PB4 (0x00000010u) 04925 #define PB4_MASK (0x00000010u) 04926 #define PB4_BIT (4) 04927 #define PB4_BITS (1) 04928 /* PB3 field */ 04929 #define PB3 (0x00000008u) 04930 #define PB3_MASK (0x00000008u) 04931 #define PB3_BIT (3) 04932 #define PB3_BITS (1) 04933 /* PB2 field */ 04934 #define PB2 (0x00000004u) 04935 #define PB2_MASK (0x00000004u) 04936 #define PB2_BIT (2) 04937 #define PB2_BITS (1) 04938 /* PB1 field */ 04939 #define PB1 (0x00000002u) 04940 #define PB1_MASK (0x00000002u) 04941 #define PB1_BIT (1) 04942 #define PB1_BITS (1) 04943 /* PB0 field */ 04944 #define PB0 (0x00000001u) 04945 #define PB0_MASK (0x00000001u) 04946 #define PB0_BIT (0) 04947 #define PB0_BITS (1) 04948 04949 #define GPIO_PBSET *((volatile int32u *)0x4000B410u) 04950 #define GPIO_PBSET_REG *((volatile int32u *)0x4000B410u) 04951 #define GPIO_PBSET_ADDR (0x4000B410u) 04952 #define GPIO_PBSET_RESET (0x00000000u) 04953 /* GPIO_PXSETRSVD field */ 04954 #define GPIO_PXSETRSVD (0x0000FF00u) 04955 #define GPIO_PXSETRSVD_MASK (0x0000FF00u) 04956 #define GPIO_PXSETRSVD_BIT (8) 04957 #define GPIO_PXSETRSVD_BITS (8) 04958 /* PB7 field */ 04959 #define PB7 (0x00000080u) 04960 #define PB7_MASK (0x00000080u) 04961 #define PB7_BIT (7) 04962 #define PB7_BITS (1) 04963 /* PB6 field */ 04964 #define PB6 (0x00000040u) 04965 #define PB6_MASK (0x00000040u) 04966 #define PB6_BIT (6) 04967 #define PB6_BITS (1) 04968 /* PB5 field */ 04969 #define PB5 (0x00000020u) 04970 #define PB5_MASK (0x00000020u) 04971 #define PB5_BIT (5) 04972 #define PB5_BITS (1) 04973 /* PB4 field */ 04974 #define PB4 (0x00000010u) 04975 #define PB4_MASK (0x00000010u) 04976 #define PB4_BIT (4) 04977 #define PB4_BITS (1) 04978 /* PB3 field */ 04979 #define PB3 (0x00000008u) 04980 #define PB3_MASK (0x00000008u) 04981 #define PB3_BIT (3) 04982 #define PB3_BITS (1) 04983 /* PB2 field */ 04984 #define PB2 (0x00000004u) 04985 #define PB2_MASK (0x00000004u) 04986 #define PB2_BIT (2) 04987 #define PB2_BITS (1) 04988 /* PB1 field */ 04989 #define PB1 (0x00000002u) 04990 #define PB1_MASK (0x00000002u) 04991 #define PB1_BIT (1) 04992 #define PB1_BITS (1) 04993 /* PB0 field */ 04994 #define PB0 (0x00000001u) 04995 #define PB0_MASK (0x00000001u) 04996 #define PB0_BIT (0) 04997 #define PB0_BITS (1) 04998 04999 #define GPIO_PBCLR *((volatile int32u *)0x4000B414u) 05000 #define GPIO_PBCLR_REG *((volatile int32u *)0x4000B414u) 05001 #define GPIO_PBCLR_ADDR (0x4000B414u) 05002 #define GPIO_PBCLR_RESET (0x00000000u) 05003 /* PB7 field */ 05004 #define PB7 (0x00000080u) 05005 #define PB7_MASK (0x00000080u) 05006 #define PB7_BIT (7) 05007 #define PB7_BITS (1) 05008 /* PB6 field */ 05009 #define PB6 (0x00000040u) 05010 #define PB6_MASK (0x00000040u) 05011 #define PB6_BIT (6) 05012 #define PB6_BITS (1) 05013 /* PB5 field */ 05014 #define PB5 (0x00000020u) 05015 #define PB5_MASK (0x00000020u) 05016 #define PB5_BIT (5) 05017 #define PB5_BITS (1) 05018 /* PB4 field */ 05019 #define PB4 (0x00000010u) 05020 #define PB4_MASK (0x00000010u) 05021 #define PB4_BIT (4) 05022 #define PB4_BITS (1) 05023 /* PB3 field */ 05024 #define PB3 (0x00000008u) 05025 #define PB3_MASK (0x00000008u) 05026 #define PB3_BIT (3) 05027 #define PB3_BITS (1) 05028 /* PB2 field */ 05029 #define PB2 (0x00000004u) 05030 #define PB2_MASK (0x00000004u) 05031 #define PB2_BIT (2) 05032 #define PB2_BITS (1) 05033 /* PB1 field */ 05034 #define PB1 (0x00000002u) 05035 #define PB1_MASK (0x00000002u) 05036 #define PB1_BIT (1) 05037 #define PB1_BITS (1) 05038 /* PB0 field */ 05039 #define PB0 (0x00000001u) 05040 #define PB0_MASK (0x00000001u) 05041 #define PB0_BIT (0) 05042 #define PB0_BITS (1) 05043 05044 #define GPIO_PCCFGL *((volatile int32u *)0x4000B800u) 05045 #define GPIO_PCCFGL_REG *((volatile int32u *)0x4000B800u) 05046 #define GPIO_PCCFGL_ADDR (0x4000B800u) 05047 #define GPIO_PCCFGL_RESET (0x00004444u) 05048 /* PC3_CFG field */ 05049 #define PC3_CFG (0x0000F000u) 05050 #define PC3_CFG_MASK (0x0000F000u) 05051 #define PC3_CFG_BIT (12) 05052 #define PC3_CFG_BITS (4) 05053 /* PC2_CFG field */ 05054 #define PC2_CFG (0x00000F00u) 05055 #define PC2_CFG_MASK (0x00000F00u) 05056 #define PC2_CFG_BIT (8) 05057 #define PC2_CFG_BITS (4) 05058 /* PC1_CFG field */ 05059 #define PC1_CFG (0x000000F0u) 05060 #define PC1_CFG_MASK (0x000000F0u) 05061 #define PC1_CFG_BIT (4) 05062 #define PC1_CFG_BITS (4) 05063 /* PC0_CFG field */ 05064 #define PC0_CFG (0x0000000Fu) 05065 #define PC0_CFG_MASK (0x0000000Fu) 05066 #define PC0_CFG_BIT (0) 05067 #define PC0_CFG_BITS (4) 05068 05069 #define GPIO_PCCFGH *((volatile int32u *)0x4000B804u) 05070 #define GPIO_PCCFGH_REG *((volatile int32u *)0x4000B804u) 05071 #define GPIO_PCCFGH_ADDR (0x4000B804u) 05072 #define GPIO_PCCFGH_RESET (0x00004444u) 05073 /* PC7_CFG field */ 05074 #define PC7_CFG (0x0000F000u) 05075 #define PC7_CFG_MASK (0x0000F000u) 05076 #define PC7_CFG_BIT (12) 05077 #define PC7_CFG_BITS (4) 05078 /* PC6_CFG field */ 05079 #define PC6_CFG (0x00000F00u) 05080 #define PC6_CFG_MASK (0x00000F00u) 05081 #define PC6_CFG_BIT (8) 05082 #define PC6_CFG_BITS (4) 05083 /* PC5_CFG field */ 05084 #define PC5_CFG (0x000000F0u) 05085 #define PC5_CFG_MASK (0x000000F0u) 05086 #define PC5_CFG_BIT (4) 05087 #define PC5_CFG_BITS (4) 05088 /* PC4_CFG field */ 05089 #define PC4_CFG (0x0000000Fu) 05090 #define PC4_CFG_MASK (0x0000000Fu) 05091 #define PC4_CFG_BIT (0) 05092 #define PC4_CFG_BITS (4) 05093 05094 #define GPIO_PCIN *((volatile int32u *)0x4000B808u) 05095 #define GPIO_PCIN_REG *((volatile int32u *)0x4000B808u) 05096 #define GPIO_PCIN_ADDR (0x4000B808u) 05097 #define GPIO_PCIN_RESET (0x00000000u) 05098 /* PC7 field */ 05099 #define PC7 (0x00000080u) 05100 #define PC7_MASK (0x00000080u) 05101 #define PC7_BIT (7) 05102 #define PC7_BITS (1) 05103 /* PC6 field */ 05104 #define PC6 (0x00000040u) 05105 #define PC6_MASK (0x00000040u) 05106 #define PC6_BIT (6) 05107 #define PC6_BITS (1) 05108 /* PC5 field */ 05109 #define PC5 (0x00000020u) 05110 #define PC5_MASK (0x00000020u) 05111 #define PC5_BIT (5) 05112 #define PC5_BITS (1) 05113 /* PC4 field */ 05114 #define PC4 (0x00000010u) 05115 #define PC4_MASK (0x00000010u) 05116 #define PC4_BIT (4) 05117 #define PC4_BITS (1) 05118 /* PC3 field */ 05119 #define PC3 (0x00000008u) 05120 #define PC3_MASK (0x00000008u) 05121 #define PC3_BIT (3) 05122 #define PC3_BITS (1) 05123 /* PC2 field */ 05124 #define PC2 (0x00000004u) 05125 #define PC2_MASK (0x00000004u) 05126 #define PC2_BIT (2) 05127 #define PC2_BITS (1) 05128 /* PC1 field */ 05129 #define PC1 (0x00000002u) 05130 #define PC1_MASK (0x00000002u) 05131 #define PC1_BIT (1) 05132 #define PC1_BITS (1) 05133 /* PC0 field */ 05134 #define PC0 (0x00000001u) 05135 #define PC0_MASK (0x00000001u) 05136 #define PC0_BIT (0) 05137 #define PC0_BITS (1) 05138 05139 #define GPIO_PCOUT *((volatile int32u *)0x4000B80Cu) 05140 #define GPIO_PCOUT_REG *((volatile int32u *)0x4000B80Cu) 05141 #define GPIO_PCOUT_ADDR (0x4000B80Cu) 05142 #define GPIO_PCOUT_RESET (0x00000000u) 05143 /* PC7 field */ 05144 #define PC7 (0x00000080u) 05145 #define PC7_MASK (0x00000080u) 05146 #define PC7_BIT (7) 05147 #define PC7_BITS (1) 05148 /* PC6 field */ 05149 #define PC6 (0x00000040u) 05150 #define PC6_MASK (0x00000040u) 05151 #define PC6_BIT (6) 05152 #define PC6_BITS (1) 05153 /* PC5 field */ 05154 #define PC5 (0x00000020u) 05155 #define PC5_MASK (0x00000020u) 05156 #define PC5_BIT (5) 05157 #define PC5_BITS (1) 05158 /* PC4 field */ 05159 #define PC4 (0x00000010u) 05160 #define PC4_MASK (0x00000010u) 05161 #define PC4_BIT (4) 05162 #define PC4_BITS (1) 05163 /* PC3 field */ 05164 #define PC3 (0x00000008u) 05165 #define PC3_MASK (0x00000008u) 05166 #define PC3_BIT (3) 05167 #define PC3_BITS (1) 05168 /* PC2 field */ 05169 #define PC2 (0x00000004u) 05170 #define PC2_MASK (0x00000004u) 05171 #define PC2_BIT (2) 05172 #define PC2_BITS (1) 05173 /* PC1 field */ 05174 #define PC1 (0x00000002u) 05175 #define PC1_MASK (0x00000002u) 05176 #define PC1_BIT (1) 05177 #define PC1_BITS (1) 05178 /* PC0 field */ 05179 #define PC0 (0x00000001u) 05180 #define PC0_MASK (0x00000001u) 05181 #define PC0_BIT (0) 05182 #define PC0_BITS (1) 05183 05184 #define GPIO_PCSET *((volatile int32u *)0x4000B810u) 05185 #define GPIO_PCSET_REG *((volatile int32u *)0x4000B810u) 05186 #define GPIO_PCSET_ADDR (0x4000B810u) 05187 #define GPIO_PCSET_RESET (0x00000000u) 05188 /* GPIO_PXSETRSVD field */ 05189 #define GPIO_PXSETRSVD (0x0000FF00u) 05190 #define GPIO_PXSETRSVD_MASK (0x0000FF00u) 05191 #define GPIO_PXSETRSVD_BIT (8) 05192 #define GPIO_PXSETRSVD_BITS (8) 05193 /* PC7 field */ 05194 #define PC7 (0x00000080u) 05195 #define PC7_MASK (0x00000080u) 05196 #define PC7_BIT (7) 05197 #define PC7_BITS (1) 05198 /* PC6 field */ 05199 #define PC6 (0x00000040u) 05200 #define PC6_MASK (0x00000040u) 05201 #define PC6_BIT (6) 05202 #define PC6_BITS (1) 05203 /* PC5 field */ 05204 #define PC5 (0x00000020u) 05205 #define PC5_MASK (0x00000020u) 05206 #define PC5_BIT (5) 05207 #define PC5_BITS (1) 05208 /* PC4 field */ 05209 #define PC4 (0x00000010u) 05210 #define PC4_MASK (0x00000010u) 05211 #define PC4_BIT (4) 05212 #define PC4_BITS (1) 05213 /* PC3 field */ 05214 #define PC3 (0x00000008u) 05215 #define PC3_MASK (0x00000008u) 05216 #define PC3_BIT (3) 05217 #define PC3_BITS (1) 05218 /* PC2 field */ 05219 #define PC2 (0x00000004u) 05220 #define PC2_MASK (0x00000004u) 05221 #define PC2_BIT (2) 05222 #define PC2_BITS (1) 05223 /* PC1 field */ 05224 #define PC1 (0x00000002u) 05225 #define PC1_MASK (0x00000002u) 05226 #define PC1_BIT (1) 05227 #define PC1_BITS (1) 05228 /* PC0 field */ 05229 #define PC0 (0x00000001u) 05230 #define PC0_MASK (0x00000001u) 05231 #define PC0_BIT (0) 05232 #define PC0_BITS (1) 05233 05234 #define GPIO_PCCLR *((volatile int32u *)0x4000B814u) 05235 #define GPIO_PCCLR_REG *((volatile int32u *)0x4000B814u) 05236 #define GPIO_PCCLR_ADDR (0x4000B814u) 05237 #define GPIO_PCCLR_RESET (0x00000000u) 05238 /* PC7 field */ 05239 #define PC7 (0x00000080u) 05240 #define PC7_MASK (0x00000080u) 05241 #define PC7_BIT (7) 05242 #define PC7_BITS (1) 05243 /* PC6 field */ 05244 #define PC6 (0x00000040u) 05245 #define PC6_MASK (0x00000040u) 05246 #define PC6_BIT (6) 05247 #define PC6_BITS (1) 05248 /* PC5 field */ 05249 #define PC5 (0x00000020u) 05250 #define PC5_MASK (0x00000020u) 05251 #define PC5_BIT (5) 05252 #define PC5_BITS (1) 05253 /* PC4 field */ 05254 #define PC4 (0x00000010u) 05255 #define PC4_MASK (0x00000010u) 05256 #define PC4_BIT (4) 05257 #define PC4_BITS (1) 05258 /* PC3 field */ 05259 #define PC3 (0x00000008u) 05260 #define PC3_MASK (0x00000008u) 05261 #define PC3_BIT (3) 05262 #define PC3_BITS (1) 05263 /* PC2 field */ 05264 #define PC2 (0x00000004u) 05265 #define PC2_MASK (0x00000004u) 05266 #define PC2_BIT (2) 05267 #define PC2_BITS (1) 05268 /* PC1 field */ 05269 #define PC1 (0x00000002u) 05270 #define PC1_MASK (0x00000002u) 05271 #define PC1_BIT (1) 05272 #define PC1_BITS (1) 05273 /* PC0 field */ 05274 #define PC0 (0x00000001u) 05275 #define PC0_MASK (0x00000001u) 05276 #define PC0_BIT (0) 05277 #define PC0_BITS (1) 05278 05279 #define GPIO_DBGCFG *((volatile int32u *)0x4000BC00u) 05280 #define GPIO_DBGCFG_REG *((volatile int32u *)0x4000BC00u) 05281 #define GPIO_DBGCFG_ADDR (0x4000BC00u) 05282 #define GPIO_DBGCFG_RESET (0x00000010u) 05283 /* GPIO_DEBUGDIS field */ 05284 #define GPIO_DEBUGDIS (0x00000020u) 05285 #define GPIO_DEBUGDIS_MASK (0x00000020u) 05286 #define GPIO_DEBUGDIS_BIT (5) 05287 #define GPIO_DEBUGDIS_BITS (1) 05288 /* GPIO_EXTREGEN field */ 05289 #define GPIO_EXTREGEN (0x00000010u) 05290 #define GPIO_EXTREGEN_MASK (0x00000010u) 05291 #define GPIO_EXTREGEN_BIT (4) 05292 #define GPIO_EXTREGEN_BITS (1) 05293 /* GPIO_DBGCFGRSVD field */ 05294 #define GPIO_DBGCFGRSVD (0x00000008u) 05295 #define GPIO_DBGCFGRSVD_MASK (0x00000008u) 05296 #define GPIO_DBGCFGRSVD_BIT (3) 05297 #define GPIO_DBGCFGRSVD_BITS (1) 05298 05299 #define GPIO_DBGSTAT *((volatile int32u *)0x4000BC04u) 05300 #define GPIO_DBGSTAT_REG *((volatile int32u *)0x4000BC04u) 05301 #define GPIO_DBGSTAT_ADDR (0x4000BC04u) 05302 #define GPIO_DBGSTAT_RESET (0x00000000u) 05303 /* GPIO_BOOTMODE field */ 05304 #define GPIO_BOOTMODE (0x00000008u) 05305 #define GPIO_BOOTMODE_MASK (0x00000008u) 05306 #define GPIO_BOOTMODE_BIT (3) 05307 #define GPIO_BOOTMODE_BITS (1) 05308 /* GPIO_FORCEDBG field */ 05309 #define GPIO_FORCEDBG (0x00000002u) 05310 #define GPIO_FORCEDBG_MASK (0x00000002u) 05311 #define GPIO_FORCEDBG_BIT (1) 05312 #define GPIO_FORCEDBG_BITS (1) 05313 /* GPIO_SWEN field */ 05314 #define GPIO_SWEN (0x00000001u) 05315 #define GPIO_SWEN_MASK (0x00000001u) 05316 #define GPIO_SWEN_BIT (0) 05317 #define GPIO_SWEN_BITS (1) 05318 05319 #define GPIO_PAWAKE *((volatile int32u *)0x4000BC08u) 05320 #define GPIO_PAWAKE_REG *((volatile int32u *)0x4000BC08u) 05321 #define GPIO_PAWAKE_ADDR (0x4000BC08u) 05322 #define GPIO_PAWAKE_RESET (0x00000000u) 05323 /* PA7 field */ 05324 #define PA7 (0x00000080u) 05325 #define PA7_MASK (0x00000080u) 05326 #define PA7_BIT (7) 05327 #define PA7_BITS (1) 05328 /* PA6 field */ 05329 #define PA6 (0x00000040u) 05330 #define PA6_MASK (0x00000040u) 05331 #define PA6_BIT (6) 05332 #define PA6_BITS (1) 05333 /* PA5 field */ 05334 #define PA5 (0x00000020u) 05335 #define PA5_MASK (0x00000020u) 05336 #define PA5_BIT (5) 05337 #define PA5_BITS (1) 05338 /* PA4 field */ 05339 #define PA4 (0x00000010u) 05340 #define PA4_MASK (0x00000010u) 05341 #define PA4_BIT (4) 05342 #define PA4_BITS (1) 05343 /* PA3 field */ 05344 #define PA3 (0x00000008u) 05345 #define PA3_MASK (0x00000008u) 05346 #define PA3_BIT (3) 05347 #define PA3_BITS (1) 05348 /* PA2 field */ 05349 #define PA2 (0x00000004u) 05350 #define PA2_MASK (0x00000004u) 05351 #define PA2_BIT (2) 05352 #define PA2_BITS (1) 05353 /* PA1 field */ 05354 #define PA1 (0x00000002u) 05355 #define PA1_MASK (0x00000002u) 05356 #define PA1_BIT (1) 05357 #define PA1_BITS (1) 05358 /* PA0 field */ 05359 #define PA0 (0x00000001u) 05360 #define PA0_MASK (0x00000001u) 05361 #define PA0_BIT (0) 05362 #define PA0_BITS (1) 05363 05364 #define GPIO_PBWAKE *((volatile int32u *)0x4000BC0Cu) 05365 #define GPIO_PBWAKE_REG *((volatile int32u *)0x4000BC0Cu) 05366 #define GPIO_PBWAKE_ADDR (0x4000BC0Cu) 05367 #define GPIO_PBWAKE_RESET (0x00000000u) 05368 /* PB7 field */ 05369 #define PB7 (0x00000080u) 05370 #define PB7_MASK (0x00000080u) 05371 #define PB7_BIT (7) 05372 #define PB7_BITS (1) 05373 /* PB6 field */ 05374 #define PB6 (0x00000040u) 05375 #define PB6_MASK (0x00000040u) 05376 #define PB6_BIT (6) 05377 #define PB6_BITS (1) 05378 /* PB5 field */ 05379 #define PB5 (0x00000020u) 05380 #define PB5_MASK (0x00000020u) 05381 #define PB5_BIT (5) 05382 #define PB5_BITS (1) 05383 /* PB4 field */ 05384 #define PB4 (0x00000010u) 05385 #define PB4_MASK (0x00000010u) 05386 #define PB4_BIT (4) 05387 #define PB4_BITS (1) 05388 /* PB3 field */ 05389 #define PB3 (0x00000008u) 05390 #define PB3_MASK (0x00000008u) 05391 #define PB3_BIT (3) 05392 #define PB3_BITS (1) 05393 /* PB2 field */ 05394 #define PB2 (0x00000004u) 05395 #define PB2_MASK (0x00000004u) 05396 #define PB2_BIT (2) 05397 #define PB2_BITS (1) 05398 /* PB1 field */ 05399 #define PB1 (0x00000002u) 05400 #define PB1_MASK (0x00000002u) 05401 #define PB1_BIT (1) 05402 #define PB1_BITS (1) 05403 /* PB0 field */ 05404 #define PB0 (0x00000001u) 05405 #define PB0_MASK (0x00000001u) 05406 #define PB0_BIT (0) 05407 #define PB0_BITS (1) 05408 05409 #define GPIO_PCWAKE *((volatile int32u *)0x4000BC10u) 05410 #define GPIO_PCWAKE_REG *((volatile int32u *)0x4000BC10u) 05411 #define GPIO_PCWAKE_ADDR (0x4000BC10u) 05412 #define GPIO_PCWAKE_RESET (0x00000000u) 05413 /* PC7 field */ 05414 #define PC7 (0x00000080u) 05415 #define PC7_MASK (0x00000080u) 05416 #define PC7_BIT (7) 05417 #define PC7_BITS (1) 05418 /* PC6 field */ 05419 #define PC6 (0x00000040u) 05420 #define PC6_MASK (0x00000040u) 05421 #define PC6_BIT (6) 05422 #define PC6_BITS (1) 05423 /* PC5 field */ 05424 #define PC5 (0x00000020u) 05425 #define PC5_MASK (0x00000020u) 05426 #define PC5_BIT (5) 05427 #define PC5_BITS (1) 05428 /* PC4 field */ 05429 #define PC4 (0x00000010u) 05430 #define PC4_MASK (0x00000010u) 05431 #define PC4_BIT (4) 05432 #define PC4_BITS (1) 05433 /* PC3 field */ 05434 #define PC3 (0x00000008u) 05435 #define PC3_MASK (0x00000008u) 05436 #define PC3_BIT (3) 05437 #define PC3_BITS (1) 05438 /* PC2 field */ 05439 #define PC2 (0x00000004u) 05440 #define PC2_MASK (0x00000004u) 05441 #define PC2_BIT (2) 05442 #define PC2_BITS (1) 05443 /* PC1 field */ 05444 #define PC1 (0x00000002u) 05445 #define PC1_MASK (0x00000002u) 05446 #define PC1_BIT (1) 05447 #define PC1_BITS (1) 05448 /* PC0 field */ 05449 #define PC0 (0x00000001u) 05450 #define PC0_MASK (0x00000001u) 05451 #define PC0_BIT (0) 05452 #define PC0_BITS (1) 05453 05454 #define GPIO_IRQCSEL *((volatile int32u *)0x4000BC14u) 05455 #define GPIO_IRQCSEL_REG *((volatile int32u *)0x4000BC14u) 05456 #define GPIO_IRQCSEL_ADDR (0x4000BC14u) 05457 #define GPIO_IRQCSEL_RESET (0x0000000Fu) 05458 /* SEL_GPIO field */ 05459 #define SEL_GPIO (0x0000001Fu) 05460 #define SEL_GPIO_MASK (0x0000001Fu) 05461 #define SEL_GPIO_BIT (0) 05462 #define SEL_GPIO_BITS (5) 05463 05464 #define GPIO_IRQDSEL *((volatile int32u *)0x4000BC18u) 05465 #define GPIO_IRQDSEL_REG *((volatile int32u *)0x4000BC18u) 05466 #define GPIO_IRQDSEL_ADDR (0x4000BC18u) 05467 #define GPIO_IRQDSEL_RESET (0x00000010u) 05468 /* SEL_GPIO field */ 05469 #define SEL_GPIO (0x0000001Fu) 05470 #define SEL_GPIO_MASK (0x0000001Fu) 05471 #define SEL_GPIO_BIT (0) 05472 #define SEL_GPIO_BITS (5) 05473 05474 #define GPIO_WAKEFILT *((volatile int32u *)0x4000BC1Cu) 05475 #define GPIO_WAKEFILT_REG *((volatile int32u *)0x4000BC1Cu) 05476 #define GPIO_WAKEFILT_ADDR (0x4000BC1Cu) 05477 #define GPIO_WAKEFILT_RESET (0x00000000u) 05478 /* IRQD_WAKE_FILTER field */ 05479 #define IRQD_WAKE_FILTER (0x00000008u) 05480 #define IRQD_WAKE_FILTER_MASK (0x00000008u) 05481 #define IRQD_WAKE_FILTER_BIT (3) 05482 #define IRQD_WAKE_FILTER_BITS (1) 05483 /* SC2_WAKE_FILTER field */ 05484 #define SC2_WAKE_FILTER (0x00000004u) 05485 #define SC2_WAKE_FILTER_MASK (0x00000004u) 05486 #define SC2_WAKE_FILTER_BIT (2) 05487 #define SC2_WAKE_FILTER_BITS (1) 05488 /* SC1_WAKE_FILTER field */ 05489 #define SC1_WAKE_FILTER (0x00000002u) 05490 #define SC1_WAKE_FILTER_MASK (0x00000002u) 05491 #define SC1_WAKE_FILTER_BIT (1) 05492 #define SC1_WAKE_FILTER_BITS (1) 05493 /* GPIO_WAKE_FILTER field */ 05494 #define GPIO_WAKE_FILTER (0x00000001u) 05495 #define GPIO_WAKE_FILTER_MASK (0x00000001u) 05496 #define GPIO_WAKE_FILTER_BIT (0) 05497 #define GPIO_WAKE_FILTER_BITS (1) 05498 05499 /* SERIAL block */ 05500 #define BLOCK_SERIAL_BASE (0x4000C000u) 05501 #define BLOCK_SERIAL_END (0x4000C870u) 05502 #define BLOCK_SERIAL_SIZE (BLOCK_SERIAL_END - BLOCK_SERIAL_BASE + 1) 05503 05504 #define SC2_RXBEGA *((volatile int32u *)0x4000C000u) 05505 #define SC2_RXBEGA_REG *((volatile int32u *)0x4000C000u) 05506 #define SC2_RXBEGA_ADDR (0x4000C000u) 05507 #define SC2_RXBEGA_RESET (0x20000000u) 05508 /* FIXED field */ 05509 #define SC2_RXBEGA_FIXED (0xFFFFE000u) 05510 #define SC2_RXBEGA_FIXED_MASK (0xFFFFE000u) 05511 #define SC2_RXBEGA_FIXED_BIT (13) 05512 #define SC2_RXBEGA_FIXED_BITS (19) 05513 /* SC_RXBEGA field */ 05514 #define SC_RXBEGA (0x00001FFFu) 05515 #define SC_RXBEGA_MASK (0x00001FFFu) 05516 #define SC_RXBEGA_BIT (0) 05517 #define SC_RXBEGA_BITS (13) 05518 05519 #define SC2_RXENDA *((volatile int32u *)0x4000C004u) 05520 #define SC2_RXENDA_REG *((volatile int32u *)0x4000C004u) 05521 #define SC2_RXENDA_ADDR (0x4000C004u) 05522 #define SC2_RXENDA_RESET (0x20000000u) 05523 /* FIXED field */ 05524 #define SC2_RXENDA_FIXED (0xFFFFE000u) 05525 #define SC2_RXENDA_FIXED_MASK (0xFFFFE000u) 05526 #define SC2_RXENDA_FIXED_BIT (13) 05527 #define SC2_RXENDA_FIXED_BITS (19) 05528 /* SC_RXENDA field */ 05529 #define SC_RXENDA (0x00001FFFu) 05530 #define SC_RXENDA_MASK (0x00001FFFu) 05531 #define SC_RXENDA_BIT (0) 05532 #define SC_RXENDA_BITS (13) 05533 05534 #define SC2_RXBEGB *((volatile int32u *)0x4000C008u) 05535 #define SC2_RXBEGB_REG *((volatile int32u *)0x4000C008u) 05536 #define SC2_RXBEGB_ADDR (0x4000C008u) 05537 #define SC2_RXBEGB_RESET (0x20000000u) 05538 /* FIXED field */ 05539 #define SC2_RXBEGB_FIXED (0xFFFFE000u) 05540 #define SC2_RXBEGB_FIXED_MASK (0xFFFFE000u) 05541 #define SC2_RXBEGB_FIXED_BIT (13) 05542 #define SC2_RXBEGB_FIXED_BITS (19) 05543 /* SC_RXBEGB field */ 05544 #define SC_RXBEGB (0x00001FFFu) 05545 #define SC_RXBEGB_MASK (0x00001FFFu) 05546 #define SC_RXBEGB_BIT (0) 05547 #define SC_RXBEGB_BITS (13) 05548 05549 #define SC2_RXENDB *((volatile int32u *)0x4000C00Cu) 05550 #define SC2_RXENDB_REG *((volatile int32u *)0x4000C00Cu) 05551 #define SC2_RXENDB_ADDR (0x4000C00Cu) 05552 #define SC2_RXENDB_RESET (0x20000000u) 05553 /* FIXED field */ 05554 #define SC2_RXENDB_FIXED (0xFFFFE000u) 05555 #define SC2_RXENDB_FIXED_MASK (0xFFFFE000u) 05556 #define SC2_RXENDB_FIXED_BIT (13) 05557 #define SC2_RXENDB_FIXED_BITS (19) 05558 /* SC_RXENDB field */ 05559 #define SC_RXENDB (0x00001FFFu) 05560 #define SC_RXENDB_MASK (0x00001FFFu) 05561 #define SC_RXENDB_BIT (0) 05562 #define SC_RXENDB_BITS (13) 05563 05564 #define SC2_TXBEGA *((volatile int32u *)0x4000C010u) 05565 #define SC2_TXBEGA_REG *((volatile int32u *)0x4000C010u) 05566 #define SC2_TXBEGA_ADDR (0x4000C010u) 05567 #define SC2_TXBEGA_RESET (0x20000000u) 05568 /* FIXED field */ 05569 #define SC2_TXBEGA_FIXED (0xFFFFE000u) 05570 #define SC2_TXBEGA_FIXED_MASK (0xFFFFE000u) 05571 #define SC2_TXBEGA_FIXED_BIT (13) 05572 #define SC2_TXBEGA_FIXED_BITS (19) 05573 /* SC_TXBEGA field */ 05574 #define SC_TXBEGA (0x00001FFFu) 05575 #define SC_TXBEGA_MASK (0x00001FFFu) 05576 #define SC_TXBEGA_BIT (0) 05577 #define SC_TXBEGA_BITS (13) 05578 05579 #define SC2_TXENDA *((volatile int32u *)0x4000C014u) 05580 #define SC2_TXENDA_REG *((volatile int32u *)0x4000C014u) 05581 #define SC2_TXENDA_ADDR (0x4000C014u) 05582 #define SC2_TXENDA_RESET (0x20000000u) 05583 /* FIXED field */ 05584 #define SC2_TXENDA_FIXED (0xFFFFE000u) 05585 #define SC2_TXENDA_FIXED_MASK (0xFFFFE000u) 05586 #define SC2_TXENDA_FIXED_BIT (13) 05587 #define SC2_TXENDA_FIXED_BITS (19) 05588 /* SC_TXENDA field */ 05589 #define SC_TXENDA (0x00001FFFu) 05590 #define SC_TXENDA_MASK (0x00001FFFu) 05591 #define SC_TXENDA_BIT (0) 05592 #define SC_TXENDA_BITS (13) 05593 05594 #define SC2_TXBEGB *((volatile int32u *)0x4000C018u) 05595 #define SC2_TXBEGB_REG *((volatile int32u *)0x4000C018u) 05596 #define SC2_TXBEGB_ADDR (0x4000C018u) 05597 #define SC2_TXBEGB_RESET (0x20000000u) 05598 /* FIXED field */ 05599 #define SC2_TXBEGB_FIXED (0xFFFFE000u) 05600 #define SC2_TXBEGB_FIXED_MASK (0xFFFFE000u) 05601 #define SC2_TXBEGB_FIXED_BIT (13) 05602 #define SC2_TXBEGB_FIXED_BITS (19) 05603 /* SC_TXBEGB field */ 05604 #define SC_TXBEGB (0x00001FFFu) 05605 #define SC_TXBEGB_MASK (0x00001FFFu) 05606 #define SC_TXBEGB_BIT (0) 05607 #define SC_TXBEGB_BITS (13) 05608 05609 #define SC2_TXENDB *((volatile int32u *)0x4000C01Cu) 05610 #define SC2_TXENDB_REG *((volatile int32u *)0x4000C01Cu) 05611 #define SC2_TXENDB_ADDR (0x4000C01Cu) 05612 #define SC2_TXENDB_RESET (0x20000000u) 05613 /* FIXED field */ 05614 #define SC2_TXENDB_FIXED (0xFFFFE000u) 05615 #define SC2_TXENDB_FIXED_MASK (0xFFFFE000u) 05616 #define SC2_TXENDB_FIXED_BIT (13) 05617 #define SC2_TXENDB_FIXED_BITS (19) 05618 /* SC_TXENDB field */ 05619 #define SC_TXENDB (0x00001FFFu) 05620 #define SC_TXENDB_MASK (0x00001FFFu) 05621 #define SC_TXENDB_BIT (0) 05622 #define SC_TXENDB_BITS (13) 05623 05624 #define SC2_RXCNTA *((volatile int32u *)0x4000C020u) 05625 #define SC2_RXCNTA_REG *((volatile int32u *)0x4000C020u) 05626 #define SC2_RXCNTA_ADDR (0x4000C020u) 05627 #define SC2_RXCNTA_RESET (0x00000000u) 05628 /* SC_RXCNTA field */ 05629 #define SC_RXCNTA (0x00001FFFu) 05630 #define SC_RXCNTA_MASK (0x00001FFFu) 05631 #define SC_RXCNTA_BIT (0) 05632 #define SC_RXCNTA_BITS (13) 05633 05634 #define SC2_RXCNTB *((volatile int32u *)0x4000C024u) 05635 #define SC2_RXCNTB_REG *((volatile int32u *)0x4000C024u) 05636 #define SC2_RXCNTB_ADDR (0x4000C024u) 05637 #define SC2_RXCNTB_RESET (0x00000000u) 05638 /* SC_RXCNTB field */ 05639 #define SC_RXCNTB (0x00001FFFu) 05640 #define SC_RXCNTB_MASK (0x00001FFFu) 05641 #define SC_RXCNTB_BIT (0) 05642 #define SC_RXCNTB_BITS (13) 05643 05644 #define SC2_TXCNT *((volatile int32u *)0x4000C028u) 05645 #define SC2_TXCNT_REG *((volatile int32u *)0x4000C028u) 05646 #define SC2_TXCNT_ADDR (0x4000C028u) 05647 #define SC2_TXCNT_RESET (0x00000000u) 05648 /* SC_TXCNT field */ 05649 #define SC_TXCNT (0x00001FFFu) 05650 #define SC_TXCNT_MASK (0x00001FFFu) 05651 #define SC_TXCNT_BIT (0) 05652 #define SC_TXCNT_BITS (13) 05653 05654 #define SC2_DMASTAT *((volatile int32u *)0x4000C02Cu) 05655 #define SC2_DMASTAT_REG *((volatile int32u *)0x4000C02Cu) 05656 #define SC2_DMASTAT_ADDR (0x4000C02Cu) 05657 #define SC2_DMASTAT_RESET (0x00000000u) 05658 /* SC_RXSSEL field */ 05659 #define SC_RXSSEL (0x00001C00u) 05660 #define SC_RXSSEL_MASK (0x00001C00u) 05661 #define SC_RXSSEL_BIT (10) 05662 #define SC_RXSSEL_BITS (3) 05663 /* SC_RXOVFB field */ 05664 #define SC_RXOVFB (0x00000020u) 05665 #define SC_RXOVFB_MASK (0x00000020u) 05666 #define SC_RXOVFB_BIT (5) 05667 #define SC_RXOVFB_BITS (1) 05668 /* SC_RXOVFA field */ 05669 #define SC_RXOVFA (0x00000010u) 05670 #define SC_RXOVFA_MASK (0x00000010u) 05671 #define SC_RXOVFA_BIT (4) 05672 #define SC_RXOVFA_BITS (1) 05673 /* SC_TXACTB field */ 05674 #define SC_TXACTB (0x00000008u) 05675 #define SC_TXACTB_MASK (0x00000008u) 05676 #define SC_TXACTB_BIT (3) 05677 #define SC_TXACTB_BITS (1) 05678 /* SC_TXACTA field */ 05679 #define SC_TXACTA (0x00000004u) 05680 #define SC_TXACTA_MASK (0x00000004u) 05681 #define SC_TXACTA_BIT (2) 05682 #define SC_TXACTA_BITS (1) 05683 /* SC_RXACTB field */ 05684 #define SC_RXACTB (0x00000002u) 05685 #define SC_RXACTB_MASK (0x00000002u) 05686 #define SC_RXACTB_BIT (1) 05687 #define SC_RXACTB_BITS (1) 05688 /* SC_RXACTA field */ 05689 #define SC_RXACTA (0x00000001u) 05690 #define SC_RXACTA_MASK (0x00000001u) 05691 #define SC_RXACTA_BIT (0) 05692 #define SC_RXACTA_BITS (1) 05693 05694 #define SC2_DMACTRL *((volatile int32u *)0x4000C030u) 05695 #define SC2_DMACTRL_REG *((volatile int32u *)0x4000C030u) 05696 #define SC2_DMACTRL_ADDR (0x4000C030u) 05697 #define SC2_DMACTRL_RESET (0x00000000u) 05698 /* SC_TXDMARST field */ 05699 #define SC_TXDMARST (0x00000020u) 05700 #define SC_TXDMARST_MASK (0x00000020u) 05701 #define SC_TXDMARST_BIT (5) 05702 #define SC_TXDMARST_BITS (1) 05703 /* SC_RXDMARST field */ 05704 #define SC_RXDMARST (0x00000010u) 05705 #define SC_RXDMARST_MASK (0x00000010u) 05706 #define SC_RXDMARST_BIT (4) 05707 #define SC_RXDMARST_BITS (1) 05708 /* SC_TXLODB field */ 05709 #define SC_TXLODB (0x00000008u) 05710 #define SC_TXLODB_MASK (0x00000008u) 05711 #define SC_TXLODB_BIT (3) 05712 #define SC_TXLODB_BITS (1) 05713 /* SC_TXLODA field */ 05714 #define SC_TXLODA (0x00000004u) 05715 #define SC_TXLODA_MASK (0x00000004u) 05716 #define SC_TXLODA_BIT (2) 05717 #define SC_TXLODA_BITS (1) 05718 /* SC_RXLODB field */ 05719 #define SC_RXLODB (0x00000002u) 05720 #define SC_RXLODB_MASK (0x00000002u) 05721 #define SC_RXLODB_BIT (1) 05722 #define SC_RXLODB_BITS (1) 05723 /* SC_RXLODA field */ 05724 #define SC_RXLODA (0x00000001u) 05725 #define SC_RXLODA_MASK (0x00000001u) 05726 #define SC_RXLODA_BIT (0) 05727 #define SC_RXLODA_BITS (1) 05728 05729 #define SC2_RXERRA *((volatile int32u *)0x4000C034u) 05730 #define SC2_RXERRA_REG *((volatile int32u *)0x4000C034u) 05731 #define SC2_RXERRA_ADDR (0x4000C034u) 05732 #define SC2_RXERRA_RESET (0x00000000u) 05733 /* SC_RXERRA field */ 05734 #define SC_RXERRA (0x00001FFFu) 05735 #define SC_RXERRA_MASK (0x00001FFFu) 05736 #define SC_RXERRA_BIT (0) 05737 #define SC_RXERRA_BITS (13) 05738 05739 #define SC2_RXERRB *((volatile int32u *)0x4000C038u) 05740 #define SC2_RXERRB_REG *((volatile int32u *)0x4000C038u) 05741 #define SC2_RXERRB_ADDR (0x4000C038u) 05742 #define SC2_RXERRB_RESET (0x00000000u) 05743 /* SC_RXERRB field */ 05744 #define SC_RXERRB (0x00001FFFu) 05745 #define SC_RXERRB_MASK (0x00001FFFu) 05746 #define SC_RXERRB_BIT (0) 05747 #define SC_RXERRB_BITS (13) 05748 05749 #define SC2_DATA *((volatile int32u *)0x4000C03Cu) 05750 #define SC2_DATA_REG *((volatile int32u *)0x4000C03Cu) 05751 #define SC2_DATA_ADDR (0x4000C03Cu) 05752 #define SC2_DATA_RESET (0x00000000u) 05753 /* SC_DATA field */ 05754 #define SC_DATA (0x000000FFu) 05755 #define SC_DATA_MASK (0x000000FFu) 05756 #define SC_DATA_BIT (0) 05757 #define SC_DATA_BITS (8) 05758 05759 #define SC2_SPISTAT *((volatile int32u *)0x4000C040u) 05760 #define SC2_SPISTAT_REG *((volatile int32u *)0x4000C040u) 05761 #define SC2_SPISTAT_ADDR (0x4000C040u) 05762 #define SC2_SPISTAT_RESET (0x00000000u) 05763 /* SC_SPITXIDLE field */ 05764 #define SC_SPITXIDLE (0x00000008u) 05765 #define SC_SPITXIDLE_MASK (0x00000008u) 05766 #define SC_SPITXIDLE_BIT (3) 05767 #define SC_SPITXIDLE_BITS (1) 05768 /* SC_SPITXFREE field */ 05769 #define SC_SPITXFREE (0x00000004u) 05770 #define SC_SPITXFREE_MASK (0x00000004u) 05771 #define SC_SPITXFREE_BIT (2) 05772 #define SC_SPITXFREE_BITS (1) 05773 /* SC_SPIRXVAL field */ 05774 #define SC_SPIRXVAL (0x00000002u) 05775 #define SC_SPIRXVAL_MASK (0x00000002u) 05776 #define SC_SPIRXVAL_BIT (1) 05777 #define SC_SPIRXVAL_BITS (1) 05778 /* SC_SPIRXOVF field */ 05779 #define SC_SPIRXOVF (0x00000001u) 05780 #define SC_SPIRXOVF_MASK (0x00000001u) 05781 #define SC_SPIRXOVF_BIT (0) 05782 #define SC_SPIRXOVF_BITS (1) 05783 05784 #define SC2_TWISTAT *((volatile int32u *)0x4000C044u) 05785 #define SC2_TWISTAT_REG *((volatile int32u *)0x4000C044u) 05786 #define SC2_TWISTAT_ADDR (0x4000C044u) 05787 #define SC2_TWISTAT_RESET (0x00000000u) 05788 /* SC_TWICMDFIN field */ 05789 #define SC_TWICMDFIN (0x00000008u) 05790 #define SC_TWICMDFIN_MASK (0x00000008u) 05791 #define SC_TWICMDFIN_BIT (3) 05792 #define SC_TWICMDFIN_BITS (1) 05793 /* SC_TWIRXFIN field */ 05794 #define SC_TWIRXFIN (0x00000004u) 05795 #define SC_TWIRXFIN_MASK (0x00000004u) 05796 #define SC_TWIRXFIN_BIT (2) 05797 #define SC_TWIRXFIN_BITS (1) 05798 /* SC_TWITXFIN field */ 05799 #define SC_TWITXFIN (0x00000002u) 05800 #define SC_TWITXFIN_MASK (0x00000002u) 05801 #define SC_TWITXFIN_BIT (1) 05802 #define SC_TWITXFIN_BITS (1) 05803 /* SC_TWIRXNAK field */ 05804 #define SC_TWIRXNAK (0x00000001u) 05805 #define SC_TWIRXNAK_MASK (0x00000001u) 05806 #define SC_TWIRXNAK_BIT (0) 05807 #define SC_TWIRXNAK_BITS (1) 05808 05809 #define SC2_TWICTRL1 *((volatile int32u *)0x4000C04Cu) 05810 #define SC2_TWICTRL1_REG *((volatile int32u *)0x4000C04Cu) 05811 #define SC2_TWICTRL1_ADDR (0x4000C04Cu) 05812 #define SC2_TWICTRL1_RESET (0x00000000u) 05813 /* SC_TWISTOP field */ 05814 #define SC_TWISTOP (0x00000008u) 05815 #define SC_TWISTOP_MASK (0x00000008u) 05816 #define SC_TWISTOP_BIT (3) 05817 #define SC_TWISTOP_BITS (1) 05818 /* SC_TWISTART field */ 05819 #define SC_TWISTART (0x00000004u) 05820 #define SC_TWISTART_MASK (0x00000004u) 05821 #define SC_TWISTART_BIT (2) 05822 #define SC_TWISTART_BITS (1) 05823 /* SC_TWISEND field */ 05824 #define SC_TWISEND (0x00000002u) 05825 #define SC_TWISEND_MASK (0x00000002u) 05826 #define SC_TWISEND_BIT (1) 05827 #define SC_TWISEND_BITS (1) 05828 /* SC_TWIRECV field */ 05829 #define SC_TWIRECV (0x00000001u) 05830 #define SC_TWIRECV_MASK (0x00000001u) 05831 #define SC_TWIRECV_BIT (0) 05832 #define SC_TWIRECV_BITS (1) 05833 05834 #define SC2_TWICTRL2 *((volatile int32u *)0x4000C050u) 05835 #define SC2_TWICTRL2_REG *((volatile int32u *)0x4000C050u) 05836 #define SC2_TWICTRL2_ADDR (0x4000C050u) 05837 #define SC2_TWICTRL2_RESET (0x00000000u) 05838 /* SC_TWIACK field */ 05839 #define SC_TWIACK (0x00000001u) 05840 #define SC_TWIACK_MASK (0x00000001u) 05841 #define SC_TWIACK_BIT (0) 05842 #define SC_TWIACK_BITS (1) 05843 05844 #define SC2_MODE *((volatile int32u *)0x4000C054u) 05845 #define SC2_MODE_REG *((volatile int32u *)0x4000C054u) 05846 #define SC2_MODE_ADDR (0x4000C054u) 05847 #define SC2_MODE_RESET (0x00000000u) 05848 /* SC_MODE field */ 05849 #define SC_MODE (0x00000003u) 05850 #define SC_MODE_MASK (0x00000003u) 05851 #define SC_MODE_BIT (0) 05852 #define SC_MODE_BITS (2) 05853 /* SC_MODE Bit Field Values */ 05854 #define SC2_MODE_DISABLED (0) 05855 #define SC2_MODE_SPI (2) 05856 #define SC2_MODE_I2C (3) 05857 05858 #define SC2_SPICFG *((volatile int32u *)0x4000C058u) 05859 #define SC2_SPICFG_REG *((volatile int32u *)0x4000C058u) 05860 #define SC2_SPICFG_ADDR (0x4000C058u) 05861 #define SC2_SPICFG_RESET (0x00000000u) 05862 /* SC_SPIRXDRV field */ 05863 #define SC_SPIRXDRV (0x00000020u) 05864 #define SC_SPIRXDRV_MASK (0x00000020u) 05865 #define SC_SPIRXDRV_BIT (5) 05866 #define SC_SPIRXDRV_BITS (1) 05867 /* SC_SPIMST field */ 05868 #define SC_SPIMST (0x00000010u) 05869 #define SC_SPIMST_MASK (0x00000010u) 05870 #define SC_SPIMST_BIT (4) 05871 #define SC_SPIMST_BITS (1) 05872 /* SC_SPIRPT field */ 05873 #define SC_SPIRPT (0x00000008u) 05874 #define SC_SPIRPT_MASK (0x00000008u) 05875 #define SC_SPIRPT_BIT (3) 05876 #define SC_SPIRPT_BITS (1) 05877 /* SC_SPIORD field */ 05878 #define SC_SPIORD (0x00000004u) 05879 #define SC_SPIORD_MASK (0x00000004u) 05880 #define SC_SPIORD_BIT (2) 05881 #define SC_SPIORD_BITS (1) 05882 /* SC_SPIPHA field */ 05883 #define SC_SPIPHA (0x00000002u) 05884 #define SC_SPIPHA_MASK (0x00000002u) 05885 #define SC_SPIPHA_BIT (1) 05886 #define SC_SPIPHA_BITS (1) 05887 /* SC_SPIPOL field */ 05888 #define SC_SPIPOL (0x00000001u) 05889 #define SC_SPIPOL_MASK (0x00000001u) 05890 #define SC_SPIPOL_BIT (0) 05891 #define SC_SPIPOL_BITS (1) 05892 05893 #define SC2_RATELIN *((volatile int32u *)0x4000C060u) 05894 #define SC2_RATELIN_REG *((volatile int32u *)0x4000C060u) 05895 #define SC2_RATELIN_ADDR (0x4000C060u) 05896 #define SC2_RATELIN_RESET (0x00000000u) 05897 /* SC_RATELIN field */ 05898 #define SC_RATELIN (0x0000000Fu) 05899 #define SC_RATELIN_MASK (0x0000000Fu) 05900 #define SC_RATELIN_BIT (0) 05901 #define SC_RATELIN_BITS (4) 05902 05903 #define SC2_RATEEXP *((volatile int32u *)0x4000C064u) 05904 #define SC2_RATEEXP_REG *((volatile int32u *)0x4000C064u) 05905 #define SC2_RATEEXP_ADDR (0x4000C064u) 05906 #define SC2_RATEEXP_RESET (0x00000000u) 05907 /* SC_RATEEXP field */ 05908 #define SC_RATEEXP (0x0000000Fu) 05909 #define SC_RATEEXP_MASK (0x0000000Fu) 05910 #define SC_RATEEXP_BIT (0) 05911 #define SC_RATEEXP_BITS (4) 05912 05913 #define SC2_RXCNTSAVED *((volatile int32u *)0x4000C070u) 05914 #define SC2_RXCNTSAVED_REG *((volatile int32u *)0x4000C070u) 05915 #define SC2_RXCNTSAVED_ADDR (0x4000C070u) 05916 #define SC2_RXCNTSAVED_RESET (0x00000000u) 05917 /* SC_RXCNTSAVED field */ 05918 #define SC_RXCNTSAVED (0x00001FFFu) 05919 #define SC_RXCNTSAVED_MASK (0x00001FFFu) 05920 #define SC_RXCNTSAVED_BIT (0) 05921 #define SC_RXCNTSAVED_BITS (13) 05922 05923 #define SC1_RXBEGA *((volatile int32u *)0x4000C800u) 05924 #define SC1_RXBEGA_REG *((volatile int32u *)0x4000C800u) 05925 #define SC1_RXBEGA_ADDR (0x4000C800u) 05926 #define SC1_RXBEGA_RESET (0x20000000u) 05927 /* FIXED field */ 05928 #define SC1_RXBEGA_FIXED (0xFFFFE000u) 05929 #define SC1_RXBEGA_FIXED_MASK (0xFFFFE000u) 05930 #define SC1_RXBEGA_FIXED_BIT (13) 05931 #define SC1_RXBEGA_FIXED_BITS (19) 05932 /* SC_RXBEGA field */ 05933 #define SC_RXBEGA (0x00001FFFu) 05934 #define SC_RXBEGA_MASK (0x00001FFFu) 05935 #define SC_RXBEGA_BIT (0) 05936 #define SC_RXBEGA_BITS (13) 05937 05938 #define SC1_RXENDA *((volatile int32u *)0x4000C804u) 05939 #define SC1_RXENDA_REG *((volatile int32u *)0x4000C804u) 05940 #define SC1_RXENDA_ADDR (0x4000C804u) 05941 #define SC1_RXENDA_RESET (0x20000000u) 05942 /* FIXED field */ 05943 #define SC1_RXENDA_FIXED (0xFFFFE000u) 05944 #define SC1_RXENDA_FIXED_MASK (0xFFFFE000u) 05945 #define SC1_RXENDA_FIXED_BIT (13) 05946 #define SC1_RXENDA_FIXED_BITS (19) 05947 /* SC_RXENDA field */ 05948 #define SC_RXENDA (0x00001FFFu) 05949 #define SC_RXENDA_MASK (0x00001FFFu) 05950 #define SC_RXENDA_BIT (0) 05951 #define SC_RXENDA_BITS (13) 05952 05953 #define SC1_RXBEGB *((volatile int32u *)0x4000C808u) 05954 #define SC1_RXBEGB_REG *((volatile int32u *)0x4000C808u) 05955 #define SC1_RXBEGB_ADDR (0x4000C808u) 05956 #define SC1_RXBEGB_RESET (0x20000000u) 05957 /* FIXED field */ 05958 #define SC1_RXBEGB_FIXED (0xFFFFE000u) 05959 #define SC1_RXBEGB_FIXED_MASK (0xFFFFE000u) 05960 #define SC1_RXBEGB_FIXED_BIT (13) 05961 #define SC1_RXBEGB_FIXED_BITS (19) 05962 /* SC_RXBEGB field */ 05963 #define SC_RXBEGB (0x00001FFFu) 05964 #define SC_RXBEGB_MASK (0x00001FFFu) 05965 #define SC_RXBEGB_BIT (0) 05966 #define SC_RXBEGB_BITS (13) 05967 05968 #define SC1_RXENDB *((volatile int32u *)0x4000C80Cu) 05969 #define SC1_RXENDB_REG *((volatile int32u *)0x4000C80Cu) 05970 #define SC1_RXENDB_ADDR (0x4000C80Cu) 05971 #define SC1_RXENDB_RESET (0x20000000u) 05972 /* FIXED field */ 05973 #define SC1_RXENDB_FIXED (0xFFFFE000u) 05974 #define SC1_RXENDB_FIXED_MASK (0xFFFFE000u) 05975 #define SC1_RXENDB_FIXED_BIT (13) 05976 #define SC1_RXENDB_FIXED_BITS (19) 05977 /* SC_RXENDB field */ 05978 #define SC_RXENDB (0x00001FFFu) 05979 #define SC_RXENDB_MASK (0x00001FFFu) 05980 #define SC_RXENDB_BIT (0) 05981 #define SC_RXENDB_BITS (13) 05982 05983 #define SC1_TXBEGA *((volatile int32u *)0x4000C810u) 05984 #define SC1_TXBEGA_REG *((volatile int32u *)0x4000C810u) 05985 #define SC1_TXBEGA_ADDR (0x4000C810u) 05986 #define SC1_TXBEGA_RESET (0x20000000u) 05987 /* FIXED field */ 05988 #define SC1_TXBEGA_FIXED (0xFFFFE000u) 05989 #define SC1_TXBEGA_FIXED_MASK (0xFFFFE000u) 05990 #define SC1_TXBEGA_FIXED_BIT (13) 05991 #define SC1_TXBEGA_FIXED_BITS (19) 05992 /* SC_TXBEGA field */ 05993 #define SC_TXBEGA (0x00001FFFu) 05994 #define SC_TXBEGA_MASK (0x00001FFFu) 05995 #define SC_TXBEGA_BIT (0) 05996 #define SC_TXBEGA_BITS (13) 05997 05998 #define SC1_TXENDA *((volatile int32u *)0x4000C814u) 05999 #define SC1_TXENDA_REG *((volatile int32u *)0x4000C814u) 06000 #define SC1_TXENDA_ADDR (0x4000C814u) 06001 #define SC1_TXENDA_RESET (0x20000000u) 06002 /* FIXED field */ 06003 #define SC1_TXENDA_FIXED (0xFFFFE000u) 06004 #define SC1_TXENDA_FIXED_MASK (0xFFFFE000u) 06005 #define SC1_TXENDA_FIXED_BIT (13) 06006 #define SC1_TXENDA_FIXED_BITS (19) 06007 /* SC_TXENDA field */ 06008 #define SC_TXENDA (0x00001FFFu) 06009 #define SC_TXENDA_MASK (0x00001FFFu) 06010 #define SC_TXENDA_BIT (0) 06011 #define SC_TXENDA_BITS (13) 06012 06013 #define SC1_TXBEGB *((volatile int32u *)0x4000C818u) 06014 #define SC1_TXBEGB_REG *((volatile int32u *)0x4000C818u) 06015 #define SC1_TXBEGB_ADDR (0x4000C818u) 06016 #define SC1_TXBEGB_RESET (0x20000000u) 06017 /* FIXED field */ 06018 #define SC1_TXBEGB_FIXED (0xFFFFE000u) 06019 #define SC1_TXBEGB_FIXED_MASK (0xFFFFE000u) 06020 #define SC1_TXBEGB_FIXED_BIT (13) 06021 #define SC1_TXBEGB_FIXED_BITS (19) 06022 /* SC_TXBEGB field */ 06023 #define SC_TXBEGB (0x00001FFFu) 06024 #define SC_TXBEGB_MASK (0x00001FFFu) 06025 #define SC_TXBEGB_BIT (0) 06026 #define SC_TXBEGB_BITS (13) 06027 06028 #define SC1_TXENDB *((volatile int32u *)0x4000C81Cu) 06029 #define SC1_TXENDB_REG *((volatile int32u *)0x4000C81Cu) 06030 #define SC1_TXENDB_ADDR (0x4000C81Cu) 06031 #define SC1_TXENDB_RESET (0x20000000u) 06032 /* FIXED field */ 06033 #define SC1_TXENDB_FIXED (0xFFFFE000u) 06034 #define SC1_TXENDB_FIXED_MASK (0xFFFFE000u) 06035 #define SC1_TXENDB_FIXED_BIT (13) 06036 #define SC1_TXENDB_FIXED_BITS (19) 06037 /* SC_TXENDB field */ 06038 #define SC_TXENDB (0x00001FFFu) 06039 #define SC_TXENDB_MASK (0x00001FFFu) 06040 #define SC_TXENDB_BIT (0) 06041 #define SC_TXENDB_BITS (13) 06042 06043 #define SC1_RXCNTA *((volatile int32u *)0x4000C820u) 06044 #define SC1_RXCNTA_REG *((volatile int32u *)0x4000C820u) 06045 #define SC1_RXCNTA_ADDR (0x4000C820u) 06046 #define SC1_RXCNTA_RESET (0x00000000u) 06047 /* SC_RXCNTA field */ 06048 #define SC_RXCNTA (0x00001FFFu) 06049 #define SC_RXCNTA_MASK (0x00001FFFu) 06050 #define SC_RXCNTA_BIT (0) 06051 #define SC_RXCNTA_BITS (13) 06052 06053 #define SC1_RXCNTB *((volatile int32u *)0x4000C824u) 06054 #define SC1_RXCNTB_REG *((volatile int32u *)0x4000C824u) 06055 #define SC1_RXCNTB_ADDR (0x4000C824u) 06056 #define SC1_RXCNTB_RESET (0x00000000u) 06057 /* SC_RXCNTB field */ 06058 #define SC_RXCNTB (0x00001FFFu) 06059 #define SC_RXCNTB_MASK (0x00001FFFu) 06060 #define SC_RXCNTB_BIT (0) 06061 #define SC_RXCNTB_BITS (13) 06062 06063 #define SC1_TXCNT *((volatile int32u *)0x4000C828u) 06064 #define SC1_TXCNT_REG *((volatile int32u *)0x4000C828u) 06065 #define SC1_TXCNT_ADDR (0x4000C828u) 06066 #define SC1_TXCNT_RESET (0x00000000u) 06067 /* SC_TXCNT field */ 06068 #define SC_TXCNT (0x00001FFFu) 06069 #define SC_TXCNT_MASK (0x00001FFFu) 06070 #define SC_TXCNT_BIT (0) 06071 #define SC_TXCNT_BITS (13) 06072 06073 #define SC1_DMASTAT *((volatile int32u *)0x4000C82Cu) 06074 #define SC1_DMASTAT_REG *((volatile int32u *)0x4000C82Cu) 06075 #define SC1_DMASTAT_ADDR (0x4000C82Cu) 06076 #define SC1_DMASTAT_RESET (0x00000000u) 06077 /* SC_RXSSEL field */ 06078 #define SC_RXSSEL (0x00001C00u) 06079 #define SC_RXSSEL_MASK (0x00001C00u) 06080 #define SC_RXSSEL_BIT (10) 06081 #define SC_RXSSEL_BITS (3) 06082 /* SC_RXFRMB field */ 06083 #define SC_RXFRMB (0x00000200u) 06084 #define SC_RXFRMB_MASK (0x00000200u) 06085 #define SC_RXFRMB_BIT (9) 06086 #define SC_RXFRMB_BITS (1) 06087 /* SC_RXFRMA field */ 06088 #define SC_RXFRMA (0x00000100u) 06089 #define SC_RXFRMA_MASK (0x00000100u) 06090 #define SC_RXFRMA_BIT (8) 06091 #define SC_RXFRMA_BITS (1) 06092 /* SC_RXPARB field */ 06093 #define SC_RXPARB (0x00000080u) 06094 #define SC_RXPARB_MASK (0x00000080u) 06095 #define SC_RXPARB_BIT (7) 06096 #define SC_RXPARB_BITS (1) 06097 /* SC_RXPARA field */ 06098 #define SC_RXPARA (0x00000040u) 06099 #define SC_RXPARA_MASK (0x00000040u) 06100 #define SC_RXPARA_BIT (6) 06101 #define SC_RXPARA_BITS (1) 06102 /* SC_RXOVFB field */ 06103 #define SC_RXOVFB (0x00000020u) 06104 #define SC_RXOVFB_MASK (0x00000020u) 06105 #define SC_RXOVFB_BIT (5) 06106 #define SC_RXOVFB_BITS (1) 06107 /* SC_RXOVFA field */ 06108 #define SC_RXOVFA (0x00000010u) 06109 #define SC_RXOVFA_MASK (0x00000010u) 06110 #define SC_RXOVFA_BIT (4) 06111 #define SC_RXOVFA_BITS (1) 06112 /* SC_TXACTB field */ 06113 #define SC_TXACTB (0x00000008u) 06114 #define SC_TXACTB_MASK (0x00000008u) 06115 #define SC_TXACTB_BIT (3) 06116 #define SC_TXACTB_BITS (1) 06117 /* SC_TXACTA field */ 06118 #define SC_TXACTA (0x00000004u) 06119 #define SC_TXACTA_MASK (0x00000004u) 06120 #define SC_TXACTA_BIT (2) 06121 #define SC_TXACTA_BITS (1) 06122 /* SC_RXACTB field */ 06123 #define SC_RXACTB (0x00000002u) 06124 #define SC_RXACTB_MASK (0x00000002u) 06125 #define SC_RXACTB_BIT (1) 06126 #define SC_RXACTB_BITS (1) 06127 /* SC_RXACTA field */ 06128 #define SC_RXACTA (0x00000001u) 06129 #define SC_RXACTA_MASK (0x00000001u) 06130 #define SC_RXACTA_BIT (0) 06131 #define SC_RXACTA_BITS (1) 06132 06133 #define SC1_DMACTRL *((volatile int32u *)0x4000C830u) 06134 #define SC1_DMACTRL_REG *((volatile int32u *)0x4000C830u) 06135 #define SC1_DMACTRL_ADDR (0x4000C830u) 06136 #define SC1_DMACTRL_RESET (0x00000000u) 06137 /* SC_TXDMARST field */ 06138 #define SC_TXDMARST (0x00000020u) 06139 #define SC_TXDMARST_MASK (0x00000020u) 06140 #define SC_TXDMARST_BIT (5) 06141 #define SC_TXDMARST_BITS (1) 06142 /* SC_RXDMARST field */ 06143 #define SC_RXDMARST (0x00000010u) 06144 #define SC_RXDMARST_MASK (0x00000010u) 06145 #define SC_RXDMARST_BIT (4) 06146 #define SC_RXDMARST_BITS (1) 06147 /* SC_TXLODB field */ 06148 #define SC_TXLODB (0x00000008u) 06149 #define SC_TXLODB_MASK (0x00000008u) 06150 #define SC_TXLODB_BIT (3) 06151 #define SC_TXLODB_BITS (1) 06152 /* SC_TXLODA field */ 06153 #define SC_TXLODA (0x00000004u) 06154 #define SC_TXLODA_MASK (0x00000004u) 06155 #define SC_TXLODA_BIT (2) 06156 #define SC_TXLODA_BITS (1) 06157 /* SC_RXLODB field */ 06158 #define SC_RXLODB (0x00000002u) 06159 #define SC_RXLODB_MASK (0x00000002u) 06160 #define SC_RXLODB_BIT (1) 06161 #define SC_RXLODB_BITS (1) 06162 /* SC_RXLODA field */ 06163 #define SC_RXLODA (0x00000001u) 06164 #define SC_RXLODA_MASK (0x00000001u) 06165 #define SC_RXLODA_BIT (0) 06166 #define SC_RXLODA_BITS (1) 06167 06168 #define SC1_RXERRA *((volatile int32u *)0x4000C834u) 06169 #define SC1_RXERRA_REG *((volatile int32u *)0x4000C834u) 06170 #define SC1_RXERRA_ADDR (0x4000C834u) 06171 #define SC1_RXERRA_RESET (0x00000000u) 06172 /* SC_RXERRA field */ 06173 #define SC_RXERRA (0x00001FFFu) 06174 #define SC_RXERRA_MASK (0x00001FFFu) 06175 #define SC_RXERRA_BIT (0) 06176 #define SC_RXERRA_BITS (13) 06177 06178 #define SC1_RXERRB *((volatile int32u *)0x4000C838u) 06179 #define SC1_RXERRB_REG *((volatile int32u *)0x4000C838u) 06180 #define SC1_RXERRB_ADDR (0x4000C838u) 06181 #define SC1_RXERRB_RESET (0x00000000u) 06182 /* SC_RXERRB field */ 06183 #define SC_RXERRB (0x00001FFFu) 06184 #define SC_RXERRB_MASK (0x00001FFFu) 06185 #define SC_RXERRB_BIT (0) 06186 #define SC_RXERRB_BITS (13) 06187 06188 #define SC1_DATA *((volatile int32u *)0x4000C83Cu) 06189 #define SC1_DATA_REG *((volatile int32u *)0x4000C83Cu) 06190 #define SC1_DATA_ADDR (0x4000C83Cu) 06191 #define SC1_DATA_RESET (0x00000000u) 06192 /* SC_DATA field */ 06193 #define SC_DATA (0x000000FFu) 06194 #define SC_DATA_MASK (0x000000FFu) 06195 #define SC_DATA_BIT (0) 06196 #define SC_DATA_BITS (8) 06197 06198 #define SC1_SPISTAT *((volatile int32u *)0x4000C840u) 06199 #define SC1_SPISTAT_REG *((volatile int32u *)0x4000C840u) 06200 #define SC1_SPISTAT_ADDR (0x4000C840u) 06201 #define SC1_SPISTAT_RESET (0x00000000u) 06202 /* SC_SPITXIDLE field */ 06203 #define SC_SPITXIDLE (0x00000008u) 06204 #define SC_SPITXIDLE_MASK (0x00000008u) 06205 #define SC_SPITXIDLE_BIT (3) 06206 #define SC_SPITXIDLE_BITS (1) 06207 /* SC_SPITXFREE field */ 06208 #define SC_SPITXFREE (0x00000004u) 06209 #define SC_SPITXFREE_MASK (0x00000004u) 06210 #define SC_SPITXFREE_BIT (2) 06211 #define SC_SPITXFREE_BITS (1) 06212 /* SC_SPIRXVAL field */ 06213 #define SC_SPIRXVAL (0x00000002u) 06214 #define SC_SPIRXVAL_MASK (0x00000002u) 06215 #define SC_SPIRXVAL_BIT (1) 06216 #define SC_SPIRXVAL_BITS (1) 06217 /* SC_SPIRXOVF field */ 06218 #define SC_SPIRXOVF (0x00000001u) 06219 #define SC_SPIRXOVF_MASK (0x00000001u) 06220 #define SC_SPIRXOVF_BIT (0) 06221 #define SC_SPIRXOVF_BITS (1) 06222 06223 #define SC1_TWISTAT *((volatile int32u *)0x4000C844u) 06224 #define SC1_TWISTAT_REG *((volatile int32u *)0x4000C844u) 06225 #define SC1_TWISTAT_ADDR (0x4000C844u) 06226 #define SC1_TWISTAT_RESET (0x00000000u) 06227 /* SC_TWICMDFIN field */ 06228 #define SC_TWICMDFIN (0x00000008u) 06229 #define SC_TWICMDFIN_MASK (0x00000008u) 06230 #define SC_TWICMDFIN_BIT (3) 06231 #define SC_TWICMDFIN_BITS (1) 06232 /* SC_TWIRXFIN field */ 06233 #define SC_TWIRXFIN (0x00000004u) 06234 #define SC_TWIRXFIN_MASK (0x00000004u) 06235 #define SC_TWIRXFIN_BIT (2) 06236 #define SC_TWIRXFIN_BITS (1) 06237 /* SC_TWITXFIN field */ 06238 #define SC_TWITXFIN (0x00000002u) 06239 #define SC_TWITXFIN_MASK (0x00000002u) 06240 #define SC_TWITXFIN_BIT (1) 06241 #define SC_TWITXFIN_BITS (1) 06242 /* SC_TWIRXNAK field */ 06243 #define SC_TWIRXNAK (0x00000001u) 06244 #define SC_TWIRXNAK_MASK (0x00000001u) 06245 #define SC_TWIRXNAK_BIT (0) 06246 #define SC_TWIRXNAK_BITS (1) 06247 06248 #define SC1_UARTSTAT *((volatile int32u *)0x4000C848u) 06249 #define SC1_UARTSTAT_REG *((volatile int32u *)0x4000C848u) 06250 #define SC1_UARTSTAT_ADDR (0x4000C848u) 06251 #define SC1_UARTSTAT_RESET (0x00000040u) 06252 /* SC_UARTTXIDLE field */ 06253 #define SC_UARTTXIDLE (0x00000040u) 06254 #define SC_UARTTXIDLE_MASK (0x00000040u) 06255 #define SC_UARTTXIDLE_BIT (6) 06256 #define SC_UARTTXIDLE_BITS (1) 06257 /* SC_UARTPARERR field */ 06258 #define SC_UARTPARERR (0x00000020u) 06259 #define SC_UARTPARERR_MASK (0x00000020u) 06260 #define SC_UARTPARERR_BIT (5) 06261 #define SC_UARTPARERR_BITS (1) 06262 /* SC_UARTFRMERR field */ 06263 #define SC_UARTFRMERR (0x00000010u) 06264 #define SC_UARTFRMERR_MASK (0x00000010u) 06265 #define SC_UARTFRMERR_BIT (4) 06266 #define SC_UARTFRMERR_BITS (1) 06267 /* SC_UARTRXOVF field */ 06268 #define SC_UARTRXOVF (0x00000008u) 06269 #define SC_UARTRXOVF_MASK (0x00000008u) 06270 #define SC_UARTRXOVF_BIT (3) 06271 #define SC_UARTRXOVF_BITS (1) 06272 /* SC_UARTTXFREE field */ 06273 #define SC_UARTTXFREE (0x00000004u) 06274 #define SC_UARTTXFREE_MASK (0x00000004u) 06275 #define SC_UARTTXFREE_BIT (2) 06276 #define SC_UARTTXFREE_BITS (1) 06277 /* SC_UARTRXVAL field */ 06278 #define SC_UARTRXVAL (0x00000002u) 06279 #define SC_UARTRXVAL_MASK (0x00000002u) 06280 #define SC_UARTRXVAL_BIT (1) 06281 #define SC_UARTRXVAL_BITS (1) 06282 /* SC_UARTCTS field */ 06283 #define SC_UARTCTS (0x00000001u) 06284 #define SC_UARTCTS_MASK (0x00000001u) 06285 #define SC_UARTCTS_BIT (0) 06286 #define SC_UARTCTS_BITS (1) 06287 06288 #define SC1_TWICTRL1 *((volatile int32u *)0x4000C84Cu) 06289 #define SC1_TWICTRL1_REG *((volatile int32u *)0x4000C84Cu) 06290 #define SC1_TWICTRL1_ADDR (0x4000C84Cu) 06291 #define SC1_TWICTRL1_RESET (0x00000000u) 06292 /* SC_TWISTOP field */ 06293 #define SC_TWISTOP (0x00000008u) 06294 #define SC_TWISTOP_MASK (0x00000008u) 06295 #define SC_TWISTOP_BIT (3) 06296 #define SC_TWISTOP_BITS (1) 06297 /* SC_TWISTART field */ 06298 #define SC_TWISTART (0x00000004u) 06299 #define SC_TWISTART_MASK (0x00000004u) 06300 #define SC_TWISTART_BIT (2) 06301 #define SC_TWISTART_BITS (1) 06302 /* SC_TWISEND field */ 06303 #define SC_TWISEND (0x00000002u) 06304 #define SC_TWISEND_MASK (0x00000002u) 06305 #define SC_TWISEND_BIT (1) 06306 #define SC_TWISEND_BITS (1) 06307 /* SC_TWIRECV field */ 06308 #define SC_TWIRECV (0x00000001u) 06309 #define SC_TWIRECV_MASK (0x00000001u) 06310 #define SC_TWIRECV_BIT (0) 06311 #define SC_TWIRECV_BITS (1) 06312 06313 #define SC1_TWICTRL2 *((volatile int32u *)0x4000C850u) 06314 #define SC1_TWICTRL2_REG *((volatile int32u *)0x4000C850u) 06315 #define SC1_TWICTRL2_ADDR (0x4000C850u) 06316 #define SC1_TWICTRL2_RESET (0x00000000u) 06317 /* SC_TWIACK field */ 06318 #define SC_TWIACK (0x00000001u) 06319 #define SC_TWIACK_MASK (0x00000001u) 06320 #define SC_TWIACK_BIT (0) 06321 #define SC_TWIACK_BITS (1) 06322 06323 #define SC1_MODE *((volatile int32u *)0x4000C854u) 06324 #define SC1_MODE_REG *((volatile int32u *)0x4000C854u) 06325 #define SC1_MODE_ADDR (0x4000C854u) 06326 #define SC1_MODE_RESET (0x00000000u) 06327 /* SC_MODE field */ 06328 #define SC_MODE (0x00000003u) 06329 #define SC_MODE_MASK (0x00000003u) 06330 #define SC_MODE_BIT (0) 06331 #define SC_MODE_BITS (2) 06332 /* SC_MODE Bit Field Values */ 06333 #define SC1_MODE_DISABLED (0) 06334 #define SC1_MODE_UART (1) 06335 #define SC1_MODE_SPI (2) 06336 #define SC1_MODE_I2C (3) 06337 06338 #define SC1_SPICFG *((volatile int32u *)0x4000C858u) 06339 #define SC1_SPICFG_REG *((volatile int32u *)0x4000C858u) 06340 #define SC1_SPICFG_ADDR (0x4000C858u) 06341 #define SC1_SPICFG_RESET (0x00000000u) 06342 /* SC_SPIRXDRV field */ 06343 #define SC_SPIRXDRV (0x00000020u) 06344 #define SC_SPIRXDRV_MASK (0x00000020u) 06345 #define SC_SPIRXDRV_BIT (5) 06346 #define SC_SPIRXDRV_BITS (1) 06347 /* SC_SPIMST field */ 06348 #define SC_SPIMST (0x00000010u) 06349 #define SC_SPIMST_MASK (0x00000010u) 06350 #define SC_SPIMST_BIT (4) 06351 #define SC_SPIMST_BITS (1) 06352 /* SC_SPIRPT field */ 06353 #define SC_SPIRPT (0x00000008u) 06354 #define SC_SPIRPT_MASK (0x00000008u) 06355 #define SC_SPIRPT_BIT (3) 06356 #define SC_SPIRPT_BITS (1) 06357 /* SC_SPIORD field */ 06358 #define SC_SPIORD (0x00000004u) 06359 #define SC_SPIORD_MASK (0x00000004u) 06360 #define SC_SPIORD_BIT (2) 06361 #define SC_SPIORD_BITS (1) 06362 /* SC_SPIPHA field */ 06363 #define SC_SPIPHA (0x00000002u) 06364 #define SC_SPIPHA_MASK (0x00000002u) 06365 #define SC_SPIPHA_BIT (1) 06366 #define SC_SPIPHA_BITS (1) 06367 /* SC_SPIPOL field */ 06368 #define SC_SPIPOL (0x00000001u) 06369 #define SC_SPIPOL_MASK (0x00000001u) 06370 #define SC_SPIPOL_BIT (0) 06371 #define SC_SPIPOL_BITS (1) 06372 06373 #define SC1_UARTCFG *((volatile int32u *)0x4000C85Cu) 06374 #define SC1_UARTCFG_REG *((volatile int32u *)0x4000C85Cu) 06375 #define SC1_UARTCFG_ADDR (0x4000C85Cu) 06376 #define SC1_UARTCFG_RESET (0x00000000u) 06377 /* SC_UARTAUTO field */ 06378 #define SC_UARTAUTO (0x00000040u) 06379 #define SC_UARTAUTO_MASK (0x00000040u) 06380 #define SC_UARTAUTO_BIT (6) 06381 #define SC_UARTAUTO_BITS (1) 06382 /* SC_UARTFLOW field */ 06383 #define SC_UARTFLOW (0x00000020u) 06384 #define SC_UARTFLOW_MASK (0x00000020u) 06385 #define SC_UARTFLOW_BIT (5) 06386 #define SC_UARTFLOW_BITS (1) 06387 /* SC_UARTODD field */ 06388 #define SC_UARTODD (0x00000010u) 06389 #define SC_UARTODD_MASK (0x00000010u) 06390 #define SC_UARTODD_BIT (4) 06391 #define SC_UARTODD_BITS (1) 06392 /* SC_UARTPAR field */ 06393 #define SC_UARTPAR (0x00000008u) 06394 #define SC_UARTPAR_MASK (0x00000008u) 06395 #define SC_UARTPAR_BIT (3) 06396 #define SC_UARTPAR_BITS (1) 06397 /* SC_UART2STP field */ 06398 #define SC_UART2STP (0x00000004u) 06399 #define SC_UART2STP_MASK (0x00000004u) 06400 #define SC_UART2STP_BIT (2) 06401 #define SC_UART2STP_BITS (1) 06402 /* SC_UART8BIT field */ 06403 #define SC_UART8BIT (0x00000002u) 06404 #define SC_UART8BIT_MASK (0x00000002u) 06405 #define SC_UART8BIT_BIT (1) 06406 #define SC_UART8BIT_BITS (1) 06407 /* SC_UARTRTS field */ 06408 #define SC_UARTRTS (0x00000001u) 06409 #define SC_UARTRTS_MASK (0x00000001u) 06410 #define SC_UARTRTS_BIT (0) 06411 #define SC_UARTRTS_BITS (1) 06412 06413 #define SC1_RATELIN *((volatile int32u *)0x4000C860u) 06414 #define SC1_RATELIN_REG *((volatile int32u *)0x4000C860u) 06415 #define SC1_RATELIN_ADDR (0x4000C860u) 06416 #define SC1_RATELIN_RESET (0x00000000u) 06417 /* SC_RATELIN field */ 06418 #define SC_RATELIN (0x0000000Fu) 06419 #define SC_RATELIN_MASK (0x0000000Fu) 06420 #define SC_RATELIN_BIT (0) 06421 #define SC_RATELIN_BITS (4) 06422 06423 #define SC1_RATEEXP *((volatile int32u *)0x4000C864u) 06424 #define SC1_RATEEXP_REG *((volatile int32u *)0x4000C864u) 06425 #define SC1_RATEEXP_ADDR (0x4000C864u) 06426 #define SC1_RATEEXP_RESET (0x00000000u) 06427 /* SC_RATEEXP field */ 06428 #define SC_RATEEXP (0x0000000Fu) 06429 #define SC_RATEEXP_MASK (0x0000000Fu) 06430 #define SC_RATEEXP_BIT (0) 06431 #define SC_RATEEXP_BITS (4) 06432 06433 #define SC1_UARTPER *((volatile int32u *)0x4000C868u) 06434 #define SC1_UARTPER_REG *((volatile int32u *)0x4000C868u) 06435 #define SC1_UARTPER_ADDR (0x4000C868u) 06436 #define SC1_UARTPER_RESET (0x00000000u) 06437 /* SC_UARTPER field */ 06438 #define SC_UARTPER (0x0000FFFFu) 06439 #define SC_UARTPER_MASK (0x0000FFFFu) 06440 #define SC_UARTPER_BIT (0) 06441 #define SC_UARTPER_BITS (16) 06442 06443 #define SC1_UARTFRAC *((volatile int32u *)0x4000C86Cu) 06444 #define SC1_UARTFRAC_REG *((volatile int32u *)0x4000C86Cu) 06445 #define SC1_UARTFRAC_ADDR (0x4000C86Cu) 06446 #define SC1_UARTFRAC_RESET (0x00000000u) 06447 /* SC_UARTFRAC field */ 06448 #define SC_UARTFRAC (0x00000001u) 06449 #define SC_UARTFRAC_MASK (0x00000001u) 06450 #define SC_UARTFRAC_BIT (0) 06451 #define SC_UARTFRAC_BITS (1) 06452 06453 #define SC1_RXCNTSAVED *((volatile int32u *)0x4000C870u) 06454 #define SC1_RXCNTSAVED_REG *((volatile int32u *)0x4000C870u) 06455 #define SC1_RXCNTSAVED_ADDR (0x4000C870u) 06456 #define SC1_RXCNTSAVED_RESET (0x00000000u) 06457 /* SC_RXCNTSAVED field */ 06458 #define SC_RXCNTSAVED (0x00001FFFu) 06459 #define SC_RXCNTSAVED_MASK (0x00001FFFu) 06460 #define SC_RXCNTSAVED_BIT (0) 06461 #define SC_RXCNTSAVED_BITS (13) 06462 06463 /* ADC block */ 06464 #define BLOCK_ADC_BASE (0x4000D000u) 06465 #define BLOCK_ADC_END (0x4000D024u) 06466 #define BLOCK_ADC_SIZE (BLOCK_ADC_END - BLOCK_ADC_BASE + 1) 06467 06468 #define ADC_DATA *((volatile int32u *)0x4000D000u) 06469 #define ADC_DATA_REG *((volatile int32u *)0x4000D000u) 06470 #define ADC_DATA_ADDR (0x4000D000u) 06471 #define ADC_DATA_RESET (0x00000000u) 06472 /* ADC_DATA_FIELD field */ 06473 #define ADC_DATA_FIELD (0x0000FFFFu) 06474 #define ADC_DATA_FIELD_MASK (0x0000FFFFu) 06475 #define ADC_DATA_FIELD_BIT (0) 06476 #define ADC_DATA_FIELD_BITS (16) 06477 06478 #define ADC_CFG *((volatile int32u *)0x4000D004u) 06479 #define ADC_CFG_REG *((volatile int32u *)0x4000D004u) 06480 #define ADC_CFG_ADDR (0x4000D004u) 06481 #define ADC_CFG_RESET (0x00001800u) 06482 /* ADC_PERIOD field */ 06483 #define ADC_PERIOD (0x0000E000u) 06484 #define ADC_PERIOD_MASK (0x0000E000u) 06485 #define ADC_PERIOD_BIT (13) 06486 #define ADC_PERIOD_BITS (3) 06487 /* ADC_HVSELP field */ 06488 #define ADC_HVSELP (0x00001000u) 06489 #define ADC_HVSELP_MASK (0x00001000u) 06490 #define ADC_HVSELP_BIT (12) 06491 #define ADC_HVSELP_BITS (1) 06492 /* ADC_HVSELN field */ 06493 #define ADC_HVSELN (0x00000800u) 06494 #define ADC_HVSELN_MASK (0x00000800u) 06495 #define ADC_HVSELN_BIT (11) 06496 #define ADC_HVSELN_BITS (1) 06497 /* ADC_MUXP field */ 06498 #define ADC_MUXP (0x00000780u) 06499 #define ADC_MUXP_MASK (0x00000780u) 06500 #define ADC_MUXP_BIT (7) 06501 #define ADC_MUXP_BITS (4) 06502 /* ADC_MUXN field */ 06503 #define ADC_MUXN (0x00000078u) 06504 #define ADC_MUXN_MASK (0x00000078u) 06505 #define ADC_MUXN_BIT (3) 06506 #define ADC_MUXN_BITS (4) 06507 /* ADC_1MHZCLK field */ 06508 #define ADC_1MHZCLK (0x00000004u) 06509 #define ADC_1MHZCLK_MASK (0x00000004u) 06510 #define ADC_1MHZCLK_BIT (2) 06511 #define ADC_1MHZCLK_BITS (1) 06512 /* ADC_CFGRSVD field */ 06513 #define ADC_CFGRSVD (0x00000002u) 06514 #define ADC_CFGRSVD_MASK (0x00000002u) 06515 #define ADC_CFGRSVD_BIT (1) 06516 #define ADC_CFGRSVD_BITS (1) 06517 /* ADC_ENABLE field */ 06518 #define ADC_ENABLE (0x00000001u) 06519 #define ADC_ENABLE_MASK (0x00000001u) 06520 #define ADC_ENABLE_BIT (0) 06521 #define ADC_ENABLE_BITS (1) 06522 06523 #define ADC_OFFSET *((volatile int32u *)0x4000D008u) 06524 #define ADC_OFFSET_REG *((volatile int32u *)0x4000D008u) 06525 #define ADC_OFFSET_ADDR (0x4000D008u) 06526 #define ADC_OFFSET_RESET (0x00000000u) 06527 /* ADC_OFFSET_FIELD field */ 06528 #define ADC_OFFSET_FIELD (0x0000FFFFu) 06529 #define ADC_OFFSET_FIELD_MASK (0x0000FFFFu) 06530 #define ADC_OFFSET_FIELD_BIT (0) 06531 #define ADC_OFFSET_FIELD_BITS (16) 06532 06533 #define ADC_GAIN *((volatile int32u *)0x4000D00Cu) 06534 #define ADC_GAIN_REG *((volatile int32u *)0x4000D00Cu) 06535 #define ADC_GAIN_ADDR (0x4000D00Cu) 06536 #define ADC_GAIN_RESET (0x00008000u) 06537 /* ADC_GAIN_FIELD field */ 06538 #define ADC_GAIN_FIELD (0x0000FFFFu) 06539 #define ADC_GAIN_FIELD_MASK (0x0000FFFFu) 06540 #define ADC_GAIN_FIELD_BIT (0) 06541 #define ADC_GAIN_FIELD_BITS (16) 06542 06543 #define ADC_DMACFG *((volatile int32u *)0x4000D010u) 06544 #define ADC_DMACFG_REG *((volatile int32u *)0x4000D010u) 06545 #define ADC_DMACFG_ADDR (0x4000D010u) 06546 #define ADC_DMACFG_RESET (0x00000000u) 06547 /* ADC_DMARST field */ 06548 #define ADC_DMARST (0x00000010u) 06549 #define ADC_DMARST_MASK (0x00000010u) 06550 #define ADC_DMARST_BIT (4) 06551 #define ADC_DMARST_BITS (1) 06552 /* ADC_DMAAUTOWRAP field */ 06553 #define ADC_DMAAUTOWRAP (0x00000002u) 06554 #define ADC_DMAAUTOWRAP_MASK (0x00000002u) 06555 #define ADC_DMAAUTOWRAP_BIT (1) 06556 #define ADC_DMAAUTOWRAP_BITS (1) 06557 /* ADC_DMALOAD field */ 06558 #define ADC_DMALOAD (0x00000001u) 06559 #define ADC_DMALOAD_MASK (0x00000001u) 06560 #define ADC_DMALOAD_BIT (0) 06561 #define ADC_DMALOAD_BITS (1) 06562 06563 #define ADC_DMASTAT *((volatile int32u *)0x4000D014u) 06564 #define ADC_DMASTAT_REG *((volatile int32u *)0x4000D014u) 06565 #define ADC_DMASTAT_ADDR (0x4000D014u) 06566 #define ADC_DMASTAT_RESET (0x00000000u) 06567 /* ADC_DMAOVF field */ 06568 #define ADC_DMAOVF (0x00000002u) 06569 #define ADC_DMAOVF_MASK (0x00000002u) 06570 #define ADC_DMAOVF_BIT (1) 06571 #define ADC_DMAOVF_BITS (1) 06572 /* ADC_DMAACT field */ 06573 #define ADC_DMAACT (0x00000001u) 06574 #define ADC_DMAACT_MASK (0x00000001u) 06575 #define ADC_DMAACT_BIT (0) 06576 #define ADC_DMAACT_BITS (1) 06577 06578 #define ADC_DMABEG *((volatile int32u *)0x4000D018u) 06579 #define ADC_DMABEG_REG *((volatile int32u *)0x4000D018u) 06580 #define ADC_DMABEG_ADDR (0x4000D018u) 06581 #define ADC_DMABEG_RESET (0x20000000u) 06582 /* ADC_DMABEG_FIXED field */ 06583 #define ADC_DMABEG_FIXED (0xFFFFE000u) 06584 #define ADC_DMABEG_FIXED_MASK (0xFFFFE000u) 06585 #define ADC_DMABEG_FIXED_BIT (13) 06586 #define ADC_DMABEG_FIXED_BITS (19) 06587 /* ADC_DMABEG_FIELD field */ 06588 #define ADC_DMABEG_FIELD (0x00001FFFu) 06589 #define ADC_DMABEG_FIELD_MASK (0x00001FFFu) 06590 #define ADC_DMABEG_FIELD_BIT (0) 06591 #define ADC_DMABEG_FIELD_BITS (13) 06592 06593 #define ADC_DMASIZE *((volatile int32u *)0x4000D01Cu) 06594 #define ADC_DMASIZE_REG *((volatile int32u *)0x4000D01Cu) 06595 #define ADC_DMASIZE_ADDR (0x4000D01Cu) 06596 #define ADC_DMASIZE_RESET (0x00000000u) 06597 /* ADC_DMASIZE_FIELD field */ 06598 #define ADC_DMASIZE_FIELD (0x00000FFFu) 06599 #define ADC_DMASIZE_FIELD_MASK (0x00000FFFu) 06600 #define ADC_DMASIZE_FIELD_BIT (0) 06601 #define ADC_DMASIZE_FIELD_BITS (12) 06602 06603 #define ADC_DMACUR *((volatile int32u *)0x4000D020u) 06604 #define ADC_DMACUR_REG *((volatile int32u *)0x4000D020u) 06605 #define ADC_DMACUR_ADDR (0x4000D020u) 06606 #define ADC_DMACUR_RESET (0x20000000u) 06607 /* ADC_DMACUR_FIXED field */ 06608 #define ADC_DMACUR_FIXED (0xFFFFE000u) 06609 #define ADC_DMACUR_FIXED_MASK (0xFFFFE000u) 06610 #define ADC_DMACUR_FIXED_BIT (13) 06611 #define ADC_DMACUR_FIXED_BITS (19) 06612 /* ADC_DMACUR_FIELD field */ 06613 #define ADC_DMACUR_FIELD (0x00001FFFu) 06614 #define ADC_DMACUR_FIELD_MASK (0x00001FFFu) 06615 #define ADC_DMACUR_FIELD_BIT (0) 06616 #define ADC_DMACUR_FIELD_BITS (13) 06617 06618 #define ADC_DMACNT *((volatile int32u *)0x4000D024u) 06619 #define ADC_DMACNT_REG *((volatile int32u *)0x4000D024u) 06620 #define ADC_DMACNT_ADDR (0x4000D024u) 06621 #define ADC_DMACNT_RESET (0x00000000u) 06622 /* ADC_DMACNT_FIELD field */ 06623 #define ADC_DMACNT_FIELD (0x00000FFFu) 06624 #define ADC_DMACNT_FIELD_MASK (0x00000FFFu) 06625 #define ADC_DMACNT_FIELD_BIT (0) 06626 #define ADC_DMACNT_FIELD_BITS (12) 06627 06628 /* TIM1 block */ 06629 #define BLOCK_TIM1_BASE (0x4000E000u) 06630 #define BLOCK_TIM1_END (0x4000E050u) 06631 #define BLOCK_TIM1_SIZE (BLOCK_TIM1_END - BLOCK_TIM1_BASE + 1) 06632 06633 #define TIM1_CR1 *((volatile int32u *)0x4000E000u) 06634 #define TIM1_CR1_REG *((volatile int32u *)0x4000E000u) 06635 #define TIM1_CR1_ADDR (0x4000E000u) 06636 #define TIM1_CR1_RESET (0x00000000u) 06637 /* TIM_ARBE field */ 06638 #define TIM_ARBE (0x00000080u) 06639 #define TIM_ARBE_MASK (0x00000080u) 06640 #define TIM_ARBE_BIT (7) 06641 #define TIM_ARBE_BITS (1) 06642 /* TIM_CMS field */ 06643 #define TIM_CMS (0x00000060u) 06644 #define TIM_CMS_MASK (0x00000060u) 06645 #define TIM_CMS_BIT (5) 06646 #define TIM_CMS_BITS (2) 06647 /* TIM_DIR field */ 06648 #define TIM_DIR (0x00000010u) 06649 #define TIM_DIR_MASK (0x00000010u) 06650 #define TIM_DIR_BIT (4) 06651 #define TIM_DIR_BITS (1) 06652 /* TIM_OPM field */ 06653 #define TIM_OPM (0x00000008u) 06654 #define TIM_OPM_MASK (0x00000008u) 06655 #define TIM_OPM_BIT (3) 06656 #define TIM_OPM_BITS (1) 06657 /* TIM_URS field */ 06658 #define TIM_URS (0x00000004u) 06659 #define TIM_URS_MASK (0x00000004u) 06660 #define TIM_URS_BIT (2) 06661 #define TIM_URS_BITS (1) 06662 /* TIM_UDIS field */ 06663 #define TIM_UDIS (0x00000002u) 06664 #define TIM_UDIS_MASK (0x00000002u) 06665 #define TIM_UDIS_BIT (1) 06666 #define TIM_UDIS_BITS (1) 06667 /* TIM_CEN field */ 06668 #define TIM_CEN (0x00000001u) 06669 #define TIM_CEN_MASK (0x00000001u) 06670 #define TIM_CEN_BIT (0) 06671 #define TIM_CEN_BITS (1) 06672 06673 #define TIM1_CR2 *((volatile int32u *)0x4000E004u) 06674 #define TIM1_CR2_REG *((volatile int32u *)0x4000E004u) 06675 #define TIM1_CR2_ADDR (0x4000E004u) 06676 #define TIM1_CR2_RESET (0x00000000u) 06677 /* TIM_TI1S field */ 06678 #define TIM_TI1S (0x00000080u) 06679 #define TIM_TI1S_MASK (0x00000080u) 06680 #define TIM_TI1S_BIT (7) 06681 #define TIM_TI1S_BITS (1) 06682 /* TIM_MMS field */ 06683 #define TIM_MMS (0x00000070u) 06684 #define TIM_MMS_MASK (0x00000070u) 06685 #define TIM_MMS_BIT (4) 06686 #define TIM_MMS_BITS (3) 06687 06688 #define TIM1_SMCR *((volatile int32u *)0x4000E008u) 06689 #define TIM1_SMCR_REG *((volatile int32u *)0x4000E008u) 06690 #define TIM1_SMCR_ADDR (0x4000E008u) 06691 #define TIM1_SMCR_RESET (0x00000000u) 06692 /* TIM_ETP field */ 06693 #define TIM_ETP (0x00008000u) 06694 #define TIM_ETP_MASK (0x00008000u) 06695 #define TIM_ETP_BIT (15) 06696 #define TIM_ETP_BITS (1) 06697 /* TIM_ECE field */ 06698 #define TIM_ECE (0x00004000u) 06699 #define TIM_ECE_MASK (0x00004000u) 06700 #define TIM_ECE_BIT (14) 06701 #define TIM_ECE_BITS (1) 06702 /* TIM_ETPS field */ 06703 #define TIM_ETPS (0x00003000u) 06704 #define TIM_ETPS_MASK (0x00003000u) 06705 #define TIM_ETPS_BIT (12) 06706 #define TIM_ETPS_BITS (2) 06707 /* TIM_ETF field */ 06708 #define TIM_ETF (0x00000F00u) 06709 #define TIM_ETF_MASK (0x00000F00u) 06710 #define TIM_ETF_BIT (8) 06711 #define TIM_ETF_BITS (4) 06712 /* TIM_MSM field */ 06713 #define TIM_MSM (0x00000080u) 06714 #define TIM_MSM_MASK (0x00000080u) 06715 #define TIM_MSM_BIT (7) 06716 #define TIM_MSM_BITS (1) 06717 /* TIM_TS field */ 06718 #define TIM_TS (0x00000070u) 06719 #define TIM_TS_MASK (0x00000070u) 06720 #define TIM_TS_BIT (4) 06721 #define TIM_TS_BITS (3) 06722 /* TIM_SMS field */ 06723 #define TIM_SMS (0x00000007u) 06724 #define TIM_SMS_MASK (0x00000007u) 06725 #define TIM_SMS_BIT (0) 06726 #define TIM_SMS_BITS (3) 06727 06728 #define TMR1_DIER *((volatile int32u *)0x4000E00Cu) 06729 #define TMR1_DIER_REG *((volatile int32u *)0x4000E00Cu) 06730 #define TMR1_DIER_ADDR (0x4000E00Cu) 06731 #define TMR1_DIER_RESET (0x00000000u) 06732 /* TIE field */ 06733 #define TMR1_DIER_TIE (0x00000040u) 06734 #define TMR1_DIER_TIE_MASK (0x00000040u) 06735 #define TMR1_DIER_TIE_BIT (6) 06736 #define TMR1_DIER_TIE_BITS (1) 06737 /* CC4IE field */ 06738 #define TMR1_DIER_CC4IE (0x00000010u) 06739 #define TMR1_DIER_CC4IE_MASK (0x00000010u) 06740 #define TMR1_DIER_CC4IE_BIT (4) 06741 #define TMR1_DIER_CC4IE_BITS (1) 06742 /* CC3IE field */ 06743 #define TMR1_DIER_CC3IE (0x00000008u) 06744 #define TMR1_DIER_CC3IE_MASK (0x00000008u) 06745 #define TMR1_DIER_CC3IE_BIT (3) 06746 #define TMR1_DIER_CC3IE_BITS (1) 06747 /* CC2IE field */ 06748 #define TMR1_DIER_CC2IE (0x00000004u) 06749 #define TMR1_DIER_CC2IE_MASK (0x00000004u) 06750 #define TMR1_DIER_CC2IE_BIT (2) 06751 #define TMR1_DIER_CC2IE_BITS (1) 06752 /* CC1IE field */ 06753 #define TMR1_DIER_CC1IE (0x00000002u) 06754 #define TMR1_DIER_CC1IE_MASK (0x00000002u) 06755 #define TMR1_DIER_CC1IE_BIT (1) 06756 #define TMR1_DIER_CC1IE_BITS (1) 06757 /* UIE field */ 06758 #define TMR1_DIER_UIE (0x00000001u) 06759 #define TMR1_DIER_UIE_MASK (0x00000001u) 06760 #define TMR1_DIER_UIE_BIT (0) 06761 #define TMR1_DIER_UIE_BITS (1) 06762 06763 #define TMR1_SR *((volatile int32u *)0x4000E010u) 06764 #define TMR1_SR_REG *((volatile int32u *)0x4000E010u) 06765 #define TMR1_SR_ADDR (0x4000E010u) 06766 #define TMR1_SR_RESET (0x00000000u) 06767 /* CC4OF field */ 06768 #define TMR1_SR_CC4OF (0x00001000u) 06769 #define TMR1_SR_CC4OF_MASK (0x00001000u) 06770 #define TMR1_SR_CC4OF_BIT (12) 06771 #define TMR1_SR_CC4OF_BITS (1) 06772 /* CC3OF field */ 06773 #define TMR1_SR_CC3OF (0x00000800u) 06774 #define TMR1_SR_CC3OF_MASK (0x00000800u) 06775 #define TMR1_SR_CC3OF_BIT (11) 06776 #define TMR1_SR_CC3OF_BITS (1) 06777 /* CC2OF field */ 06778 #define TMR1_SR_CC2OF (0x00000400u) 06779 #define TMR1_SR_CC2OF_MASK (0x00000400u) 06780 #define TMR1_SR_CC2OF_BIT (10) 06781 #define TMR1_SR_CC2OF_BITS (1) 06782 /* CC1OF field */ 06783 #define TMR1_SR_CC1OF (0x00000200u) 06784 #define TMR1_SR_CC1OF_MASK (0x00000200u) 06785 #define TMR1_SR_CC1OF_BIT (9) 06786 #define TMR1_SR_CC1OF_BITS (1) 06787 /* TIF field */ 06788 #define TMR1_SR_TIF (0x00000040u) 06789 #define TMR1_SR_TIF_MASK (0x00000040u) 06790 #define TMR1_SR_TIF_BIT (6) 06791 #define TMR1_SR_TIF_BITS (1) 06792 /* CC4IF field */ 06793 #define TMR1_SR_CC4IF (0x00000010u) 06794 #define TMR1_SR_CC4IF_MASK (0x00000010u) 06795 #define TMR1_SR_CC4IF_BIT (4) 06796 #define TMR1_SR_CC4IF_BITS (1) 06797 /* CC3IF field */ 06798 #define TMR1_SR_CC3IF (0x00000008u) 06799 #define TMR1_SR_CC3IF_MASK (0x00000008u) 06800 #define TMR1_SR_CC3IF_BIT (3) 06801 #define TMR1_SR_CC3IF_BITS (1) 06802 /* CC2IF field */ 06803 #define TMR1_SR_CC2IF (0x00000004u) 06804 #define TMR1_SR_CC2IF_MASK (0x00000004u) 06805 #define TMR1_SR_CC2IF_BIT (2) 06806 #define TMR1_SR_CC2IF_BITS (1) 06807 /* CC1IF field */ 06808 #define TMR1_SR_CC1IF (0x00000002u) 06809 #define TMR1_SR_CC1IF_MASK (0x00000002u) 06810 #define TMR1_SR_CC1IF_BIT (1) 06811 #define TMR1_SR_CC1IF_BITS (1) 06812 /* UIF field */ 06813 #define TMR1_SR_UIF (0x00000001u) 06814 #define TMR1_SR_UIF_MASK (0x00000001u) 06815 #define TMR1_SR_UIF_BIT (0) 06816 #define TMR1_SR_UIF_BITS (1) 06817 06818 #define TIM1_EGR *((volatile int32u *)0x4000E014u) 06819 #define TIM1_EGR_REG *((volatile int32u *)0x4000E014u) 06820 #define TIM1_EGR_ADDR (0x4000E014u) 06821 #define TIM1_EGR_RESET (0x00000000u) 06822 /* TIM_TG field */ 06823 #define TIM_TG (0x00000040u) 06824 #define TIM_TG_MASK (0x00000040u) 06825 #define TIM_TG_BIT (6) 06826 #define TIM_TG_BITS (1) 06827 /* TIM_CC4G field */ 06828 #define TIM_CC4G (0x00000010u) 06829 #define TIM_CC4G_MASK (0x00000010u) 06830 #define TIM_CC4G_BIT (4) 06831 #define TIM_CC4G_BITS (1) 06832 /* TIM_CC3G field */ 06833 #define TIM_CC3G (0x00000008u) 06834 #define TIM_CC3G_MASK (0x00000008u) 06835 #define TIM_CC3G_BIT (3) 06836 #define TIM_CC3G_BITS (1) 06837 /* TIM_CC2G field */ 06838 #define TIM_CC2G (0x00000004u) 06839 #define TIM_CC2G_MASK (0x00000004u) 06840 #define TIM_CC2G_BIT (2) 06841 #define TIM_CC2G_BITS (1) 06842 /* TIM_CC1G field */ 06843 #define TIM_CC1G (0x00000002u) 06844 #define TIM_CC1G_MASK (0x00000002u) 06845 #define TIM_CC1G_BIT (1) 06846 #define TIM_CC1G_BITS (1) 06847 /* TIM_UG field */ 06848 #define TIM_UG (0x00000001u) 06849 #define TIM_UG_MASK (0x00000001u) 06850 #define TIM_UG_BIT (0) 06851 #define TIM_UG_BITS (1) 06852 06853 #define TIM1_CCMR1 *((volatile int32u *)0x4000E018u) 06854 #define TIM1_CCMR1_REG *((volatile int32u *)0x4000E018u) 06855 #define TIM1_CCMR1_ADDR (0x4000E018u) 06856 #define TIM1_CCMR1_RESET (0x00000000u) 06857 /* TIM_IC2F field */ 06858 #define TIM_IC2F (0x0000F000u) 06859 #define TIM_IC2F_MASK (0x0000F000u) 06860 #define TIM_IC2F_BIT (12) 06861 #define TIM_IC2F_BITS (4) 06862 /* TIM_IC2PSC field */ 06863 #define TIM_IC2PSC (0x00000C00u) 06864 #define TIM_IC2PSC_MASK (0x00000C00u) 06865 #define TIM_IC2PSC_BIT (10) 06866 #define TIM_IC2PSC_BITS (2) 06867 /* TIM_IC1F field */ 06868 #define TIM_IC1F (0x000000F0u) 06869 #define TIM_IC1F_MASK (0x000000F0u) 06870 #define TIM_IC1F_BIT (4) 06871 #define TIM_IC1F_BITS (4) 06872 /* TIM_IC1PSC field */ 06873 #define TIM_IC1PSC (0x0000000Cu) 06874 #define TIM_IC1PSC_MASK (0x0000000Cu) 06875 #define TIM_IC1PSC_BIT (2) 06876 #define TIM_IC1PSC_BITS (2) 06877 /* TIM_OC2CE field */ 06878 #define TIM_OC2CE (0x00008000u) 06879 #define TIM_OC2CE_MASK (0x00008000u) 06880 #define TIM_OC2CE_BIT (15) 06881 #define TIM_OC2CE_BITS (1) 06882 /* TIM_OC2M field */ 06883 #define TIM_OC2M (0x00007000u) 06884 #define TIM_OC2M_MASK (0x00007000u) 06885 #define TIM_OC2M_BIT (12) 06886 #define TIM_OC2M_BITS (3) 06887 /* TIM_OC2BE field */ 06888 #define TIM_OC2BE (0x00000800u) 06889 #define TIM_OC2BE_MASK (0x00000800u) 06890 #define TIM_OC2BE_BIT (11) 06891 #define TIM_OC2BE_BITS (1) 06892 /* TIM_OC2FE field */ 06893 #define TIM_OC2FE (0x00000400u) 06894 #define TIM_OC2FE_MASK (0x00000400u) 06895 #define TIM_OC2FE_BIT (10) 06896 #define TIM_OC2FE_BITS (1) 06897 /* TIM_CC2S field */ 06898 #define TIM_CC2S (0x00000300u) 06899 #define TIM_CC2S_MASK (0x00000300u) 06900 #define TIM_CC2S_BIT (8) 06901 #define TIM_CC2S_BITS (2) 06902 /* TIM_OC1CE field */ 06903 #define TIM_OC1CE (0x00000080u) 06904 #define TIM_OC1CE_MASK (0x00000080u) 06905 #define TIM_OC1CE_BIT (7) 06906 #define TIM_OC1CE_BITS (1) 06907 /* TIM_OC1M field */ 06908 #define TIM_OC1M (0x00000070u) 06909 #define TIM_OC1M_MASK (0x00000070u) 06910 #define TIM_OC1M_BIT (4) 06911 #define TIM_OC1M_BITS (3) 06912 /* TIM_OC1PE field */ 06913 #define TIM_OC1PE (0x00000008u) 06914 #define TIM_OC1PE_MASK (0x00000008u) 06915 #define TIM_OC1PE_BIT (3) 06916 #define TIM_OC1PE_BITS (1) 06917 /* TIM_OC1FE field */ 06918 #define TIM_OC1FE (0x00000004u) 06919 #define TIM_OC1FE_MASK (0x00000004u) 06920 #define TIM_OC1FE_BIT (2) 06921 #define TIM_OC1FE_BITS (1) 06922 /* TIM_CC1S field */ 06923 #define TIM_CC1S (0x00000003u) 06924 #define TIM_CC1S_MASK (0x00000003u) 06925 #define TIM_CC1S_BIT (0) 06926 #define TIM_CC1S_BITS (2) 06927 06928 #define TIM1_CCMR2 *((volatile int32u *)0x4000E01Cu) 06929 #define TIM1_CCMR2_REG *((volatile int32u *)0x4000E01Cu) 06930 #define TIM1_CCMR2_ADDR (0x4000E01Cu) 06931 #define TIM1_CCMR2_RESET (0x00000000u) 06932 /* TIM_IC4F field */ 06933 #define TIM_IC4F (0x0000F000u) 06934 #define TIM_IC4F_MASK (0x0000F000u) 06935 #define TIM_IC4F_BIT (12) 06936 #define TIM_IC4F_BITS (4) 06937 /* TIM_IC4PSC field */ 06938 #define TIM_IC4PSC (0x00000C00u) 06939 #define TIM_IC4PSC_MASK (0x00000C00u) 06940 #define TIM_IC4PSC_BIT (10) 06941 #define TIM_IC4PSC_BITS (2) 06942 /* TIM_IC3F field */ 06943 #define TIM_IC3F (0x000000F0u) 06944 #define TIM_IC3F_MASK (0x000000F0u) 06945 #define TIM_IC3F_BIT (4) 06946 #define TIM_IC3F_BITS (4) 06947 /* TIM_IC3PSC field */ 06948 #define TIM_IC3PSC (0x0000000Cu) 06949 #define TIM_IC3PSC_MASK (0x0000000Cu) 06950 #define TIM_IC3PSC_BIT (2) 06951 #define TIM_IC3PSC_BITS (2) 06952 /* TIM_OC4CE field */ 06953 #define TIM_OC4CE (0x00008000u) 06954 #define TIM_OC4CE_MASK (0x00008000u) 06955 #define TIM_OC4CE_BIT (15) 06956 #define TIM_OC4CE_BITS (1) 06957 /* TIM_OC4M field */ 06958 #define TIM_OC4M (0x00007000u) 06959 #define TIM_OC4M_MASK (0x00007000u) 06960 #define TIM_OC4M_BIT (12) 06961 #define TIM_OC4M_BITS (3) 06962 /* TIM_OC4BE field */ 06963 #define TIM_OC4BE (0x00000800u) 06964 #define TIM_OC4BE_MASK (0x00000800u) 06965 #define TIM_OC4BE_BIT (11) 06966 #define TIM_OC4BE_BITS (1) 06967 /* TIM_OC4FE field */ 06968 #define TIM_OC4FE (0x00000400u) 06969 #define TIM_OC4FE_MASK (0x00000400u) 06970 #define TIM_OC4FE_BIT (10) 06971 #define TIM_OC4FE_BITS (1) 06972 /* TIM_CC4S field */ 06973 #define TIM_CC4S (0x00000300u) 06974 #define TIM_CC4S_MASK (0x00000300u) 06975 #define TIM_CC4S_BIT (8) 06976 #define TIM_CC4S_BITS (2) 06977 /* TIM_OC3CE field */ 06978 #define TIM_OC3CE (0x00000080u) 06979 #define TIM_OC3CE_MASK (0x00000080u) 06980 #define TIM_OC3CE_BIT (7) 06981 #define TIM_OC3CE_BITS (1) 06982 /* TIM_OC3M field */ 06983 #define TIM_OC3M (0x00000070u) 06984 #define TIM_OC3M_MASK (0x00000070u) 06985 #define TIM_OC3M_BIT (4) 06986 #define TIM_OC3M_BITS (3) 06987 /* TIM_OC3BE field */ 06988 #define TIM_OC3BE (0x00000008u) 06989 #define TIM_OC3BE_MASK (0x00000008u) 06990 #define TIM_OC3BE_BIT (3) 06991 #define TIM_OC3BE_BITS (1) 06992 /* TIM_OC3FE field */ 06993 #define TIM_OC3FE (0x00000004u) 06994 #define TIM_OC3FE_MASK (0x00000004u) 06995 #define TIM_OC3FE_BIT (2) 06996 #define TIM_OC3FE_BITS (1) 06997 /* TIM_CC3S field */ 06998 #define TIM_CC3S (0x00000003u) 06999 #define TIM_CC3S_MASK (0x00000003u) 07000 #define TIM_CC3S_BIT (0) 07001 #define TIM_CC3S_BITS (2) 07002 07003 #define TIM1_CCER *((volatile int32u *)0x4000E020u) 07004 #define TIM1_CCER_REG *((volatile int32u *)0x4000E020u) 07005 #define TIM1_CCER_ADDR (0x4000E020u) 07006 #define TIM1_CCER_RESET (0x00000000u) 07007 /* TIM_CC4P field */ 07008 #define TIM_CC4P (0x00002000u) 07009 #define TIM_CC4P_MASK (0x00002000u) 07010 #define TIM_CC4P_BIT (13) 07011 #define TIM_CC4P_BITS (1) 07012 /* TIM_CC4E field */ 07013 #define TIM_CC4E (0x00001000u) 07014 #define TIM_CC4E_MASK (0x00001000u) 07015 #define TIM_CC4E_BIT (12) 07016 #define TIM_CC4E_BITS (1) 07017 /* TIM_CC3P field */ 07018 #define TIM_CC3P (0x00000200u) 07019 #define TIM_CC3P_MASK (0x00000200u) 07020 #define TIM_CC3P_BIT (9) 07021 #define TIM_CC3P_BITS (1) 07022 /* TIM_CC3E field */ 07023 #define TIM_CC3E (0x00000100u) 07024 #define TIM_CC3E_MASK (0x00000100u) 07025 #define TIM_CC3E_BIT (8) 07026 #define TIM_CC3E_BITS (1) 07027 /* TIM_CC2P field */ 07028 #define TIM_CC2P (0x00000020u) 07029 #define TIM_CC2P_MASK (0x00000020u) 07030 #define TIM_CC2P_BIT (5) 07031 #define TIM_CC2P_BITS (1) 07032 /* TIM_CC2E field */ 07033 #define TIM_CC2E (0x00000010u) 07034 #define TIM_CC2E_MASK (0x00000010u) 07035 #define TIM_CC2E_BIT (4) 07036 #define TIM_CC2E_BITS (1) 07037 /* TIM_CC1P field */ 07038 #define TIM_CC1P (0x00000002u) 07039 #define TIM_CC1P_MASK (0x00000002u) 07040 #define TIM_CC1P_BIT (1) 07041 #define TIM_CC1P_BITS (1) 07042 /* TIM_CC1E field */ 07043 #define TIM_CC1E (0x00000001u) 07044 #define TIM_CC1E_MASK (0x00000001u) 07045 #define TIM_CC1E_BIT (0) 07046 #define TIM_CC1E_BITS (1) 07047 07048 #define TIM1_CNT *((volatile int32u *)0x4000E024u) 07049 #define TIM1_CNT_REG *((volatile int32u *)0x4000E024u) 07050 #define TIM1_CNT_ADDR (0x4000E024u) 07051 #define TIM1_CNT_RESET (0x00000000u) 07052 /* TIM_CNT field */ 07053 #define TIM_CNT (0x0000FFFFu) 07054 #define TIM_CNT_MASK (0x0000FFFFu) 07055 #define TIM_CNT_BIT (0) 07056 #define TIM_CNT_BITS (16) 07057 07058 #define TIM1_PSC *((volatile int32u *)0x4000E028u) 07059 #define TIM1_PSC_REG *((volatile int32u *)0x4000E028u) 07060 #define TIM1_PSC_ADDR (0x4000E028u) 07061 #define TIM1_PSC_RESET (0x00000000u) 07062 /* TIM_PSC field */ 07063 #define TIM_PSC (0x0000000Fu) 07064 #define TIM_PSC_MASK (0x0000000Fu) 07065 #define TIM_PSC_BIT (0) 07066 #define TIM_PSC_BITS (4) 07067 07068 #define TIM1_ARR *((volatile int32u *)0x4000E02Cu) 07069 #define TIM1_ARR_REG *((volatile int32u *)0x4000E02Cu) 07070 #define TIM1_ARR_ADDR (0x4000E02Cu) 07071 #define TIM1_ARR_RESET (0x0000FFFFu) 07072 /* TIM_ARR field */ 07073 #define TIM_ARR (0x0000FFFFu) 07074 #define TIM_ARR_MASK (0x0000FFFFu) 07075 #define TIM_ARR_BIT (0) 07076 #define TIM_ARR_BITS (16) 07077 07078 #define TIM1_CCR1 *((volatile int32u *)0x4000E034u) 07079 #define TIM1_CCR1_REG *((volatile int32u *)0x4000E034u) 07080 #define TIM1_CCR1_ADDR (0x4000E034u) 07081 #define TIM1_CCR1_RESET (0x00000000u) 07082 /* TIM_CCR field */ 07083 #define TIM_CCR (0x0000FFFFu) 07084 #define TIM_CCR_MASK (0x0000FFFFu) 07085 #define TIM_CCR_BIT (0) 07086 #define TIM_CCR_BITS (16) 07087 07088 #define TIM1_CCR2 *((volatile int32u *)0x4000E038u) 07089 #define TIM1_CCR2_REG *((volatile int32u *)0x4000E038u) 07090 #define TIM1_CCR2_ADDR (0x4000E038u) 07091 #define TIM1_CCR2_RESET (0x00000000u) 07092 /* TIM_CCR field */ 07093 #define TIM_CCR (0x0000FFFFu) 07094 #define TIM_CCR_MASK (0x0000FFFFu) 07095 #define TIM_CCR_BIT (0) 07096 #define TIM_CCR_BITS (16) 07097 07098 #define TIM1_CCR3 *((volatile int32u *)0x4000E03Cu) 07099 #define TIM1_CCR3_REG *((volatile int32u *)0x4000E03Cu) 07100 #define TIM1_CCR3_ADDR (0x4000E03Cu) 07101 #define TIM1_CCR3_RESET (0x00000000u) 07102 /* TIM_CCR field */ 07103 #define TIM_CCR (0x0000FFFFu) 07104 #define TIM_CCR_MASK (0x0000FFFFu) 07105 #define TIM_CCR_BIT (0) 07106 #define TIM_CCR_BITS (16) 07107 07108 #define TIM1_CCR4 *((volatile int32u *)0x4000E040u) 07109 #define TIM1_CCR4_REG *((volatile int32u *)0x4000E040u) 07110 #define TIM1_CCR4_ADDR (0x4000E040u) 07111 #define TIM1_CCR4_RESET (0x00000000u) 07112 /* TIM_CCR field */ 07113 #define TIM_CCR (0x0000FFFFu) 07114 #define TIM_CCR_MASK (0x0000FFFFu) 07115 #define TIM_CCR_BIT (0) 07116 #define TIM_CCR_BITS (16) 07117 07118 #define TIM1_OR *((volatile int32u *)0x4000E050u) 07119 #define TIM1_OR_REG *((volatile int32u *)0x4000E050u) 07120 #define TIM1_OR_ADDR (0x4000E050u) 07121 #define TIM1_OR_RESET (0x00000000u) 07122 /* TIM_ORRSVD field */ 07123 #define TIM_ORRSVD (0x00000008u) 07124 #define TIM_ORRSVD_MASK (0x00000008u) 07125 #define TIM_ORRSVD_BIT (3) 07126 #define TIM_ORRSVD_BITS (1) 07127 /* TIM_CLKMSKEN field */ 07128 #define TIM_CLKMSKEN (0x00000004u) 07129 #define TIM_CLKMSKEN_MASK (0x00000004u) 07130 #define TIM_CLKMSKEN_BIT (2) 07131 #define TIM_CLKMSKEN_BITS (1) 07132 /* TIM1_EXTRIGSEL field */ 07133 #define TIM1_EXTRIGSEL (0x00000003u) 07134 #define TIM1_EXTRIGSEL_MASK (0x00000003u) 07135 #define TIM1_EXTRIGSEL_BIT (0) 07136 #define TIM1_EXTRIGSEL_BITS (2) 07137 07138 /* TIM2 block */ 07139 #define BLOCK_TIM2_BASE (0x4000F000u) 07140 #define BLOCK_TIM2_END (0x4000F050u) 07141 #define BLOCK_TIM2_SIZE (BLOCK_TIM2_END - BLOCK_TIM2_BASE + 1) 07142 07143 #define TIM2_CR1 *((volatile int32u *)0x4000F000u) 07144 #define TIM2_CR1_REG *((volatile int32u *)0x4000F000u) 07145 #define TIM2_CR1_ADDR (0x4000F000u) 07146 #define TIM2_CR1_RESET (0x00000000u) 07147 /* TIM_ARBE field */ 07148 #define TIM_ARBE (0x00000080u) 07149 #define TIM_ARBE_MASK (0x00000080u) 07150 #define TIM_ARBE_BIT (7) 07151 #define TIM_ARBE_BITS (1) 07152 /* TIM_CMS field */ 07153 #define TIM_CMS (0x00000060u) 07154 #define TIM_CMS_MASK (0x00000060u) 07155 #define TIM_CMS_BIT (5) 07156 #define TIM_CMS_BITS (2) 07157 /* TIM_DIR field */ 07158 #define TIM_DIR (0x00000010u) 07159 #define TIM_DIR_MASK (0x00000010u) 07160 #define TIM_DIR_BIT (4) 07161 #define TIM_DIR_BITS (1) 07162 /* TIM_OPM field */ 07163 #define TIM_OPM (0x00000008u) 07164 #define TIM_OPM_MASK (0x00000008u) 07165 #define TIM_OPM_BIT (3) 07166 #define TIM_OPM_BITS (1) 07167 /* TIM_URS field */ 07168 #define TIM_URS (0x00000004u) 07169 #define TIM_URS_MASK (0x00000004u) 07170 #define TIM_URS_BIT (2) 07171 #define TIM_URS_BITS (1) 07172 /* TIM_UDIS field */ 07173 #define TIM_UDIS (0x00000002u) 07174 #define TIM_UDIS_MASK (0x00000002u) 07175 #define TIM_UDIS_BIT (1) 07176 #define TIM_UDIS_BITS (1) 07177 /* TIM_CEN field */ 07178 #define TIM_CEN (0x00000001u) 07179 #define TIM_CEN_MASK (0x00000001u) 07180 #define TIM_CEN_BIT (0) 07181 #define TIM_CEN_BITS (1) 07182 07183 #define TIM2_CR2 *((volatile int32u *)0x4000F004u) 07184 #define TIM2_CR2_REG *((volatile int32u *)0x4000F004u) 07185 #define TIM2_CR2_ADDR (0x4000F004u) 07186 #define TIM2_CR2_RESET (0x00000000u) 07187 /* TIM_TI1S field */ 07188 #define TIM_TI1S (0x00000080u) 07189 #define TIM_TI1S_MASK (0x00000080u) 07190 #define TIM_TI1S_BIT (7) 07191 #define TIM_TI1S_BITS (1) 07192 /* TIM_MMS field */ 07193 #define TIM_MMS (0x00000070u) 07194 #define TIM_MMS_MASK (0x00000070u) 07195 #define TIM_MMS_BIT (4) 07196 #define TIM_MMS_BITS (3) 07197 07198 #define TIM2_SMCR *((volatile int32u *)0x4000F008u) 07199 #define TIM2_SMCR_REG *((volatile int32u *)0x4000F008u) 07200 #define TIM2_SMCR_ADDR (0x4000F008u) 07201 #define TIM2_SMCR_RESET (0x00000000u) 07202 /* TIM_ETP field */ 07203 #define TIM_ETP (0x00008000u) 07204 #define TIM_ETP_MASK (0x00008000u) 07205 #define TIM_ETP_BIT (15) 07206 #define TIM_ETP_BITS (1) 07207 /* TIM_ECE field */ 07208 #define TIM_ECE (0x00004000u) 07209 #define TIM_ECE_MASK (0x00004000u) 07210 #define TIM_ECE_BIT (14) 07211 #define TIM_ECE_BITS (1) 07212 /* TIM_ETPS field */ 07213 #define TIM_ETPS (0x00003000u) 07214 #define TIM_ETPS_MASK (0x00003000u) 07215 #define TIM_ETPS_BIT (12) 07216 #define TIM_ETPS_BITS (2) 07217 /* TIM_ETF field */ 07218 #define TIM_ETF (0x00000F00u) 07219 #define TIM_ETF_MASK (0x00000F00u) 07220 #define TIM_ETF_BIT (8) 07221 #define TIM_ETF_BITS (4) 07222 /* TIM_MSM field */ 07223 #define TIM_MSM (0x00000080u) 07224 #define TIM_MSM_MASK (0x00000080u) 07225 #define TIM_MSM_BIT (7) 07226 #define TIM_MSM_BITS (1) 07227 /* TIM_TS field */ 07228 #define TIM_TS (0x00000070u) 07229 #define TIM_TS_MASK (0x00000070u) 07230 #define TIM_TS_BIT (4) 07231 #define TIM_TS_BITS (3) 07232 /* TIM_SMS field */ 07233 #define TIM_SMS (0x00000007u) 07234 #define TIM_SMS_MASK (0x00000007u) 07235 #define TIM_SMS_BIT (0) 07236 #define TIM_SMS_BITS (3) 07237 07238 #define TMR2_DIER *((volatile int32u *)0x4000F00Cu) 07239 #define TMR2_DIER_REG *((volatile int32u *)0x4000F00Cu) 07240 #define TMR2_DIER_ADDR (0x4000F00Cu) 07241 #define TMR2_DIER_RESET (0x00000000u) 07242 /* TIE field */ 07243 #define TMR2_DIER_TIE (0x00000040u) 07244 #define TMR2_DIER_TIE_MASK (0x00000040u) 07245 #define TMR2_DIER_TIE_BIT (6) 07246 #define TMR2_DIER_TIE_BITS (1) 07247 /* CC4IE field */ 07248 #define TMR2_DIER_CC4IE (0x00000010u) 07249 #define TMR2_DIER_CC4IE_MASK (0x00000010u) 07250 #define TMR2_DIER_CC4IE_BIT (4) 07251 #define TMR2_DIER_CC4IE_BITS (1) 07252 /* CC3IE field */ 07253 #define TMR2_DIER_CC3IE (0x00000008u) 07254 #define TMR2_DIER_CC3IE_MASK (0x00000008u) 07255 #define TMR2_DIER_CC3IE_BIT (3) 07256 #define TMR2_DIER_CC3IE_BITS (1) 07257 /* CC2IE field */ 07258 #define TMR2_DIER_CC2IE (0x00000004u) 07259 #define TMR2_DIER_CC2IE_MASK (0x00000004u) 07260 #define TMR2_DIER_CC2IE_BIT (2) 07261 #define TMR2_DIER_CC2IE_BITS (1) 07262 /* CC1IE field */ 07263 #define TMR2_DIER_CC1IE (0x00000002u) 07264 #define TMR2_DIER_CC1IE_MASK (0x00000002u) 07265 #define TMR2_DIER_CC1IE_BIT (1) 07266 #define TMR2_DIER_CC1IE_BITS (1) 07267 /* UIE field */ 07268 #define TMR2_DIER_UIE (0x00000001u) 07269 #define TMR2_DIER_UIE_MASK (0x00000001u) 07270 #define TMR2_DIER_UIE_BIT (0) 07271 #define TMR2_DIER_UIE_BITS (1) 07272 07273 #define TMR2_SR *((volatile int32u *)0x4000F010u) 07274 #define TMR2_SR_REG *((volatile int32u *)0x4000F010u) 07275 #define TMR2_SR_ADDR (0x4000F010u) 07276 #define TMR2_SR_RESET (0x00000000u) 07277 /* CC4OF field */ 07278 #define TMR2_SR_CC4OF (0x00001000u) 07279 #define TMR2_SR_CC4OF_MASK (0x00001000u) 07280 #define TMR2_SR_CC4OF_BIT (12) 07281 #define TMR2_SR_CC4OF_BITS (1) 07282 /* CC3OF field */ 07283 #define TMR2_SR_CC3OF (0x00000800u) 07284 #define TMR2_SR_CC3OF_MASK (0x00000800u) 07285 #define TMR2_SR_CC3OF_BIT (11) 07286 #define TMR2_SR_CC3OF_BITS (1) 07287 /* CC2OF field */ 07288 #define TMR2_SR_CC2OF (0x00000400u) 07289 #define TMR2_SR_CC2OF_MASK (0x00000400u) 07290 #define TMR2_SR_CC2OF_BIT (10) 07291 #define TMR2_SR_CC2OF_BITS (1) 07292 /* CC1OF field */ 07293 #define TMR2_SR_CC1OF (0x00000200u) 07294 #define TMR2_SR_CC1OF_MASK (0x00000200u) 07295 #define TMR2_SR_CC1OF_BIT (9) 07296 #define TMR2_SR_CC1OF_BITS (1) 07297 /* TIF field */ 07298 #define TMR2_SR_TIF (0x00000040u) 07299 #define TMR2_SR_TIF_MASK (0x00000040u) 07300 #define TMR2_SR_TIF_BIT (6) 07301 #define TMR2_SR_TIF_BITS (1) 07302 /* CC4IF field */ 07303 #define TMR2_SR_CC4IF (0x00000010u) 07304 #define TMR2_SR_CC4IF_MASK (0x00000010u) 07305 #define TMR2_SR_CC4IF_BIT (4) 07306 #define TMR2_SR_CC4IF_BITS (1) 07307 /* CC3IF field */ 07308 #define TMR2_SR_CC3IF (0x00000008u) 07309 #define TMR2_SR_CC3IF_MASK (0x00000008u) 07310 #define TMR2_SR_CC3IF_BIT (3) 07311 #define TMR2_SR_CC3IF_BITS (1) 07312 /* CC2IF field */ 07313 #define TMR2_SR_CC2IF (0x00000004u) 07314 #define TMR2_SR_CC2IF_MASK (0x00000004u) 07315 #define TMR2_SR_CC2IF_BIT (2) 07316 #define TMR2_SR_CC2IF_BITS (1) 07317 /* CC1IF field */ 07318 #define TMR2_SR_CC1IF (0x00000002u) 07319 #define TMR2_SR_CC1IF_MASK (0x00000002u) 07320 #define TMR2_SR_CC1IF_BIT (1) 07321 #define TMR2_SR_CC1IF_BITS (1) 07322 /* UIF field */ 07323 #define TMR2_SR_UIF (0x00000001u) 07324 #define TMR2_SR_UIF_MASK (0x00000001u) 07325 #define TMR2_SR_UIF_BIT (0) 07326 #define TMR2_SR_UIF_BITS (1) 07327 07328 #define TIM2_EGR *((volatile int32u *)0x4000F014u) 07329 #define TIM2_EGR_REG *((volatile int32u *)0x4000F014u) 07330 #define TIM2_EGR_ADDR (0x4000F014u) 07331 #define TIM2_EGR_RESET (0x00000000u) 07332 /* TIM_TG field */ 07333 #define TIM_TG (0x00000040u) 07334 #define TIM_TG_MASK (0x00000040u) 07335 #define TIM_TG_BIT (6) 07336 #define TIM_TG_BITS (1) 07337 /* TIM_CC4G field */ 07338 #define TIM_CC4G (0x00000010u) 07339 #define TIM_CC4G_MASK (0x00000010u) 07340 #define TIM_CC4G_BIT (4) 07341 #define TIM_CC4G_BITS (1) 07342 /* TIM_CC3G field */ 07343 #define TIM_CC3G (0x00000008u) 07344 #define TIM_CC3G_MASK (0x00000008u) 07345 #define TIM_CC3G_BIT (3) 07346 #define TIM_CC3G_BITS (1) 07347 /* TIM_CC2G field */ 07348 #define TIM_CC2G (0x00000004u) 07349 #define TIM_CC2G_MASK (0x00000004u) 07350 #define TIM_CC2G_BIT (2) 07351 #define TIM_CC2G_BITS (1) 07352 /* TIM_CC1G field */ 07353 #define TIM_CC1G (0x00000002u) 07354 #define TIM_CC1G_MASK (0x00000002u) 07355 #define TIM_CC1G_BIT (1) 07356 #define TIM_CC1G_BITS (1) 07357 /* TIM_UG field */ 07358 #define TIM_UG (0x00000001u) 07359 #define TIM_UG_MASK (0x00000001u) 07360 #define TIM_UG_BIT (0) 07361 #define TIM_UG_BITS (1) 07362 07363 #define TIM2_CCMR1 *((volatile int32u *)0x4000F018u) 07364 #define TIM2_CCMR1_REG *((volatile int32u *)0x4000F018u) 07365 #define TIM2_CCMR1_ADDR (0x4000F018u) 07366 #define TIM2_CCMR1_RESET (0x00000000u) 07367 /* TIM_IC2F field */ 07368 #define TIM_IC2F (0x0000F000u) 07369 #define TIM_IC2F_MASK (0x0000F000u) 07370 #define TIM_IC2F_BIT (12) 07371 #define TIM_IC2F_BITS (4) 07372 /* TIM_IC2PSC field */ 07373 #define TIM_IC2PSC (0x00000C00u) 07374 #define TIM_IC2PSC_MASK (0x00000C00u) 07375 #define TIM_IC2PSC_BIT (10) 07376 #define TIM_IC2PSC_BITS (2) 07377 /* TIM_IC1F field */ 07378 #define TIM_IC1F (0x000000F0u) 07379 #define TIM_IC1F_MASK (0x000000F0u) 07380 #define TIM_IC1F_BIT (4) 07381 #define TIM_IC1F_BITS (4) 07382 /* TIM_IC1PSC field */ 07383 #define TIM_IC1PSC (0x0000000Cu) 07384 #define TIM_IC1PSC_MASK (0x0000000Cu) 07385 #define TIM_IC1PSC_BIT (2) 07386 #define TIM_IC1PSC_BITS (2) 07387 /* TIM_OC2CE field */ 07388 #define TIM_OC2CE (0x00008000u) 07389 #define TIM_OC2CE_MASK (0x00008000u) 07390 #define TIM_OC2CE_BIT (15) 07391 #define TIM_OC2CE_BITS (1) 07392 /* TIM_OC2M field */ 07393 #define TIM_OC2M (0x00007000u) 07394 #define TIM_OC2M_MASK (0x00007000u) 07395 #define TIM_OC2M_BIT (12) 07396 #define TIM_OC2M_BITS (3) 07397 /* TIM_OC2BE field */ 07398 #define TIM_OC2BE (0x00000800u) 07399 #define TIM_OC2BE_MASK (0x00000800u) 07400 #define TIM_OC2BE_BIT (11) 07401 #define TIM_OC2BE_BITS (1) 07402 /* TIM_OC2FE field */ 07403 #define TIM_OC2FE (0x00000400u) 07404 #define TIM_OC2FE_MASK (0x00000400u) 07405 #define TIM_OC2FE_BIT (10) 07406 #define TIM_OC2FE_BITS (1) 07407 /* TIM_CC2S field */ 07408 #define TIM_CC2S (0x00000300u) 07409 #define TIM_CC2S_MASK (0x00000300u) 07410 #define TIM_CC2S_BIT (8) 07411 #define TIM_CC2S_BITS (2) 07412 /* TIM_OC1CE field */ 07413 #define TIM_OC1CE (0x00000080u) 07414 #define TIM_OC1CE_MASK (0x00000080u) 07415 #define TIM_OC1CE_BIT (7) 07416 #define TIM_OC1CE_BITS (1) 07417 /* TIM_OC1M field */ 07418 #define TIM_OC1M (0x00000070u) 07419 #define TIM_OC1M_MASK (0x00000070u) 07420 #define TIM_OC1M_BIT (4) 07421 #define TIM_OC1M_BITS (3) 07422 /* TIM_OC1PE field */ 07423 #define TIM_OC1PE (0x00000008u) 07424 #define TIM_OC1PE_MASK (0x00000008u) 07425 #define TIM_OC1PE_BIT (3) 07426 #define TIM_OC1PE_BITS (1) 07427 /* TIM_OC1FE field */ 07428 #define TIM_OC1FE (0x00000004u) 07429 #define TIM_OC1FE_MASK (0x00000004u) 07430 #define TIM_OC1FE_BIT (2) 07431 #define TIM_OC1FE_BITS (1) 07432 /* TIM_CC1S field */ 07433 #define TIM_CC1S (0x00000003u) 07434 #define TIM_CC1S_MASK (0x00000003u) 07435 #define TIM_CC1S_BIT (0) 07436 #define TIM_CC1S_BITS (2) 07437 07438 #define TIM2_CCMR2 *((volatile int32u *)0x4000F01Cu) 07439 #define TIM2_CCMR2_REG *((volatile int32u *)0x4000F01Cu) 07440 #define TIM2_CCMR2_ADDR (0x4000F01Cu) 07441 #define TIM2_CCMR2_RESET (0x00000000u) 07442 /* TIM_IC4F field */ 07443 #define TIM_IC4F (0x0000F000u) 07444 #define TIM_IC4F_MASK (0x0000F000u) 07445 #define TIM_IC4F_BIT (12) 07446 #define TIM_IC4F_BITS (4) 07447 /* TIM_IC4PSC field */ 07448 #define TIM_IC4PSC (0x00000C00u) 07449 #define TIM_IC4PSC_MASK (0x00000C00u) 07450 #define TIM_IC4PSC_BIT (10) 07451 #define TIM_IC4PSC_BITS (2) 07452 /* TIM_IC3F field */ 07453 #define TIM_IC3F (0x000000F0u) 07454 #define TIM_IC3F_MASK (0x000000F0u) 07455 #define TIM_IC3F_BIT (4) 07456 #define TIM_IC3F_BITS (4) 07457 /* TIM_IC3PSC field */ 07458 #define TIM_IC3PSC (0x0000000Cu) 07459 #define TIM_IC3PSC_MASK (0x0000000Cu) 07460 #define TIM_IC3PSC_BIT (2) 07461 #define TIM_IC3PSC_BITS (2) 07462 /* TIM_OC4CE field */ 07463 #define TIM_OC4CE (0x00008000u) 07464 #define TIM_OC4CE_MASK (0x00008000u) 07465 #define TIM_OC4CE_BIT (15) 07466 #define TIM_OC4CE_BITS (1) 07467 /* TIM_OC4M field */ 07468 #define TIM_OC4M (0x00007000u) 07469 #define TIM_OC4M_MASK (0x00007000u) 07470 #define TIM_OC4M_BIT (12) 07471 #define TIM_OC4M_BITS (3) 07472 /* TIM_OC4BE field */ 07473 #define TIM_OC4BE (0x00000800u) 07474 #define TIM_OC4BE_MASK (0x00000800u) 07475 #define TIM_OC4BE_BIT (11) 07476 #define TIM_OC4BE_BITS (1) 07477 /* TIM_OC4FE field */ 07478 #define TIM_OC4FE (0x00000400u) 07479 #define TIM_OC4FE_MASK (0x00000400u) 07480 #define TIM_OC4FE_BIT (10) 07481 #define TIM_OC4FE_BITS (1) 07482 /* TIM_CC4S field */ 07483 #define TIM_CC4S (0x00000300u) 07484 #define TIM_CC4S_MASK (0x00000300u) 07485 #define TIM_CC4S_BIT (8) 07486 #define TIM_CC4S_BITS (2) 07487 /* TIM_OC3CE field */ 07488 #define TIM_OC3CE (0x00000080u) 07489 #define TIM_OC3CE_MASK (0x00000080u) 07490 #define TIM_OC3CE_BIT (7) 07491 #define TIM_OC3CE_BITS (1) 07492 /* TIM_OC3M field */ 07493 #define TIM_OC3M (0x00000070u) 07494 #define TIM_OC3M_MASK (0x00000070u) 07495 #define TIM_OC3M_BIT (4) 07496 #define TIM_OC3M_BITS (3) 07497 /* TIM_OC3BE field */ 07498 #define TIM_OC3BE (0x00000008u) 07499 #define TIM_OC3BE_MASK (0x00000008u) 07500 #define TIM_OC3BE_BIT (3) 07501 #define TIM_OC3BE_BITS (1) 07502 /* TIM_OC3FE field */ 07503 #define TIM_OC3FE (0x00000004u) 07504 #define TIM_OC3FE_MASK (0x00000004u) 07505 #define TIM_OC3FE_BIT (2) 07506 #define TIM_OC3FE_BITS (1) 07507 /* TIM_CC3S field */ 07508 #define TIM_CC3S (0x00000003u) 07509 #define TIM_CC3S_MASK (0x00000003u) 07510 #define TIM_CC3S_BIT (0) 07511 #define TIM_CC3S_BITS (2) 07512 07513 #define TIM2_CCER *((volatile int32u *)0x4000F020u) 07514 #define TIM2_CCER_REG *((volatile int32u *)0x4000F020u) 07515 #define TIM2_CCER_ADDR (0x4000F020u) 07516 #define TIM2_CCER_RESET (0x00000000u) 07517 /* TIM_CC4P field */ 07518 #define TIM_CC4P (0x00002000u) 07519 #define TIM_CC4P_MASK (0x00002000u) 07520 #define TIM_CC4P_BIT (13) 07521 #define TIM_CC4P_BITS (1) 07522 /* TIM_CC4E field */ 07523 #define TIM_CC4E (0x00001000u) 07524 #define TIM_CC4E_MASK (0x00001000u) 07525 #define TIM_CC4E_BIT (12) 07526 #define TIM_CC4E_BITS (1) 07527 /* TIM_CC3P field */ 07528 #define TIM_CC3P (0x00000200u) 07529 #define TIM_CC3P_MASK (0x00000200u) 07530 #define TIM_CC3P_BIT (9) 07531 #define TIM_CC3P_BITS (1) 07532 /* TIM_CC3E field */ 07533 #define TIM_CC3E (0x00000100u) 07534 #define TIM_CC3E_MASK (0x00000100u) 07535 #define TIM_CC3E_BIT (8) 07536 #define TIM_CC3E_BITS (1) 07537 /* TIM_CC2P field */ 07538 #define TIM_CC2P (0x00000020u) 07539 #define TIM_CC2P_MASK (0x00000020u) 07540 #define TIM_CC2P_BIT (5) 07541 #define TIM_CC2P_BITS (1) 07542 /* TIM_CC2E field */ 07543 #define TIM_CC2E (0x00000010u) 07544 #define TIM_CC2E_MASK (0x00000010u) 07545 #define TIM_CC2E_BIT (4) 07546 #define TIM_CC2E_BITS (1) 07547 /* TIM_CC1P field */ 07548 #define TIM_CC1P (0x00000002u) 07549 #define TIM_CC1P_MASK (0x00000002u) 07550 #define TIM_CC1P_BIT (1) 07551 #define TIM_CC1P_BITS (1) 07552 /* TIM_CC1E field */ 07553 #define TIM_CC1E (0x00000001u) 07554 #define TIM_CC1E_MASK (0x00000001u) 07555 #define TIM_CC1E_BIT (0) 07556 #define TIM_CC1E_BITS (1) 07557 07558 #define TIM2_CNT *((volatile int32u *)0x4000F024u) 07559 #define TIM2_CNT_REG *((volatile int32u *)0x4000F024u) 07560 #define TIM2_CNT_ADDR (0x4000F024u) 07561 #define TIM2_CNT_RESET (0x00000000u) 07562 /* TIM_CNT field */ 07563 #define TIM_CNT (0x0000FFFFu) 07564 #define TIM_CNT_MASK (0x0000FFFFu) 07565 #define TIM_CNT_BIT (0) 07566 #define TIM_CNT_BITS (16) 07567 07568 #define TIM2_PSC *((volatile int32u *)0x4000F028u) 07569 #define TIM2_PSC_REG *((volatile int32u *)0x4000F028u) 07570 #define TIM2_PSC_ADDR (0x4000F028u) 07571 #define TIM2_PSC_RESET (0x00000000u) 07572 /* TIM_PSC field */ 07573 #define TIM_PSC (0x0000000Fu) 07574 #define TIM_PSC_MASK (0x0000000Fu) 07575 #define TIM_PSC_BIT (0) 07576 #define TIM_PSC_BITS (4) 07577 07578 #define TIM2_ARR *((volatile int32u *)0x4000F02Cu) 07579 #define TIM2_ARR_REG *((volatile int32u *)0x4000F02Cu) 07580 #define TIM2_ARR_ADDR (0x4000F02Cu) 07581 #define TIM2_ARR_RESET (0x0000FFFFu) 07582 /* TIM_ARR field */ 07583 #define TIM_ARR (0x0000FFFFu) 07584 #define TIM_ARR_MASK (0x0000FFFFu) 07585 #define TIM_ARR_BIT (0) 07586 #define TIM_ARR_BITS (16) 07587 07588 #define TIM2_CCR1 *((volatile int32u *)0x4000F034u) 07589 #define TIM2_CCR1_REG *((volatile int32u *)0x4000F034u) 07590 #define TIM2_CCR1_ADDR (0x4000F034u) 07591 #define TIM2_CCR1_RESET (0x00000000u) 07592 /* TIM_CCR field */ 07593 #define TIM_CCR (0x0000FFFFu) 07594 #define TIM_CCR_MASK (0x0000FFFFu) 07595 #define TIM_CCR_BIT (0) 07596 #define TIM_CCR_BITS (16) 07597 07598 #define TIM2_CCR2 *((volatile int32u *)0x4000F038u) 07599 #define TIM2_CCR2_REG *((volatile int32u *)0x4000F038u) 07600 #define TIM2_CCR2_ADDR (0x4000F038u) 07601 #define TIM2_CCR2_RESET (0x00000000u) 07602 /* TIM_CCR field */ 07603 #define TIM_CCR (0x0000FFFFu) 07604 #define TIM_CCR_MASK (0x0000FFFFu) 07605 #define TIM_CCR_BIT (0) 07606 #define TIM_CCR_BITS (16) 07607 07608 #define TIM2_CCR3 *((volatile int32u *)0x4000F03Cu) 07609 #define TIM2_CCR3_REG *((volatile int32u *)0x4000F03Cu) 07610 #define TIM2_CCR3_ADDR (0x4000F03Cu) 07611 #define TIM2_CCR3_RESET (0x00000000u) 07612 /* TIM_CCR field */ 07613 #define TIM_CCR (0x0000FFFFu) 07614 #define TIM_CCR_MASK (0x0000FFFFu) 07615 #define TIM_CCR_BIT (0) 07616 #define TIM_CCR_BITS (16) 07617 07618 #define TIM2_CCR4 *((volatile int32u *)0x4000F040u) 07619 #define TIM2_CCR4_REG *((volatile int32u *)0x4000F040u) 07620 #define TIM2_CCR4_ADDR (0x4000F040u) 07621 #define TIM2_CCR4_RESET (0x00000000u) 07622 /* TIM_CCR field */ 07623 #define TIM_CCR (0x0000FFFFu) 07624 #define TIM_CCR_MASK (0x0000FFFFu) 07625 #define TIM_CCR_BIT (0) 07626 #define TIM_CCR_BITS (16) 07627 07628 #define TIM2_OR *((volatile int32u *)0x4000F050u) 07629 #define TIM2_OR_REG *((volatile int32u *)0x4000F050u) 07630 #define TIM2_OR_ADDR (0x4000F050u) 07631 #define TIM2_OR_RESET (0x00000000u) 07632 /* TIM_REMAPC4 field */ 07633 #define TIM_REMAPC4 (0x00000080u) 07634 #define TIM_REMAPC4_MASK (0x00000080u) 07635 #define TIM_REMAPC4_BIT (7) 07636 #define TIM_REMAPC4_BITS (1) 07637 /* TIM_REMAPC3 field */ 07638 #define TIM_REMAPC3 (0x00000040u) 07639 #define TIM_REMAPC3_MASK (0x00000040u) 07640 #define TIM_REMAPC3_BIT (6) 07641 #define TIM_REMAPC3_BITS (1) 07642 /* TIM_REMAPC2 field */ 07643 #define TIM_REMAPC2 (0x00000020u) 07644 #define TIM_REMAPC2_MASK (0x00000020u) 07645 #define TIM_REMAPC2_BIT (5) 07646 #define TIM_REMAPC2_BITS (1) 07647 /* TIM_REMAPC1 field */ 07648 #define TIM_REMAPC1 (0x00000010u) 07649 #define TIM_REMAPC1_MASK (0x00000010u) 07650 #define TIM_REMAPC1_BIT (4) 07651 #define TIM_REMAPC1_BITS (1) 07652 /* TIM_ORRSVD field */ 07653 #define TIM_ORRSVD (0x00000008u) 07654 #define TIM_ORRSVD_MASK (0x00000008u) 07655 #define TIM_ORRSVD_BIT (3) 07656 #define TIM_ORRSVD_BITS (1) 07657 /* TIM_CLKMSKEN field */ 07658 #define TIM_CLKMSKEN (0x00000004u) 07659 #define TIM_CLKMSKEN_MASK (0x00000004u) 07660 #define TIM_CLKMSKEN_BIT (2) 07661 #define TIM_CLKMSKEN_BITS (1) 07662 /* TIM1_EXTRIGSEL field */ 07663 #define TIM1_EXTRIGSEL (0x00000003u) 07664 #define TIM1_EXTRIGSEL_MASK (0x00000003u) 07665 #define TIM1_EXTRIGSEL_BIT (0) 07666 #define TIM1_EXTRIGSEL_BITS (2) 07667 07668 /* EXT_RAM block */ 07669 #define DATA_EXT_RAM_BASE (0x60000000u) 07670 #define DATA_EXT_RAM_END (0x9FFFFFFFu) 07671 #define DATA_EXT_RAM_SIZE (DATA_EXT_RAM_END - DATA_EXT_RAM_BASE + 1) 07672 07673 /* EXT_DEVICE block */ 07674 #define DATA_EXT_DEVICE_BASE (0xA0000000u) 07675 #define DATA_EXT_DEVICE_END (0xDFFFFFFFu) 07676 #define DATA_EXT_DEVICE_SIZE (DATA_EXT_DEVICE_END - DATA_EXT_DEVICE_BASE + 1) 07677 07678 /* ITM block */ 07679 #define DATA_ITM_BASE (0xE0000000u) 07680 #define DATA_ITM_END (0xE0000FFFu) 07681 #define DATA_ITM_SIZE (DATA_ITM_END - DATA_ITM_BASE + 1) 07682 07683 #define ITM_SP0 *((volatile int32u *)0xE0000000u) 07684 #define ITM_SP0_REG *((volatile int32u *)0xE0000000u) 07685 #define ITM_SP0_ADDR (0xE0000000u) 07686 #define ITM_SP0_RESET (0x00000000u) 07687 /* FIFOREADY field */ 07688 #define ITM_SP0_FIFOREADY (0x00000001u) 07689 #define ITM_SP0_FIFOREADY_MASK (0x00000001u) 07690 #define ITM_SP0_FIFOREADY_BIT (0) 07691 #define ITM_SP0_FIFOREADY_BITS (1) 07692 /* STIMULUS field */ 07693 #define ITM_SP0_STIMULUS (0xFFFFFFFFu) 07694 #define ITM_SP0_STIMULUS_MASK (0xFFFFFFFFu) 07695 #define ITM_SP0_STIMULUS_BIT (0) 07696 #define ITM_SP0_STIMULUS_BITS (32) 07697 07698 #define ITM_SP1 *((volatile int32u *)0xE0000004u) 07699 #define ITM_SP1_REG *((volatile int32u *)0xE0000004u) 07700 #define ITM_SP1_ADDR (0xE0000004u) 07701 #define ITM_SP1_RESET (0x00000000u) 07702 /* FIFOREADY field */ 07703 #define ITM_SP1_FIFOREADY (0x00000001u) 07704 #define ITM_SP1_FIFOREADY_MASK (0x00000001u) 07705 #define ITM_SP1_FIFOREADY_BIT (0) 07706 #define ITM_SP1_FIFOREADY_BITS (1) 07707 /* STIMULUS field */ 07708 #define ITM_SP1_STIMULUS (0xFFFFFFFFu) 07709 #define ITM_SP1_STIMULUS_MASK (0xFFFFFFFFu) 07710 #define ITM_SP1_STIMULUS_BIT (0) 07711 #define ITM_SP1_STIMULUS_BITS (32) 07712 07713 #define ITM_SP2 *((volatile int32u *)0xE0000008u) 07714 #define ITM_SP2_REG *((volatile int32u *)0xE0000008u) 07715 #define ITM_SP2_ADDR (0xE0000008u) 07716 #define ITM_SP2_RESET (0x00000000u) 07717 /* FIFOREADY field */ 07718 #define ITM_SP2_FIFOREADY (0x00000001u) 07719 #define ITM_SP2_FIFOREADY_MASK (0x00000001u) 07720 #define ITM_SP2_FIFOREADY_BIT (0) 07721 #define ITM_SP2_FIFOREADY_BITS (1) 07722 /* STIMULUS field */ 07723 #define ITM_SP2_STIMULUS (0xFFFFFFFFu) 07724 #define ITM_SP2_STIMULUS_MASK (0xFFFFFFFFu) 07725 #define ITM_SP2_STIMULUS_BIT (0) 07726 #define ITM_SP2_STIMULUS_BITS (32) 07727 07728 #define ITM_SP3 *((volatile int32u *)0xE000000Cu) 07729 #define ITM_SP3_REG *((volatile int32u *)0xE000000Cu) 07730 #define ITM_SP3_ADDR (0xE000000Cu) 07731 #define ITM_SP3_RESET (0x00000000u) 07732 /* FIFOREADY field */ 07733 #define ITM_SP3_FIFOREADY (0x00000001u) 07734 #define ITM_SP3_FIFOREADY_MASK (0x00000001u) 07735 #define ITM_SP3_FIFOREADY_BIT (0) 07736 #define ITM_SP3_FIFOREADY_BITS (1) 07737 /* STIMULUS field */ 07738 #define ITM_SP3_STIMULUS (0xFFFFFFFFu) 07739 #define ITM_SP3_STIMULUS_MASK (0xFFFFFFFFu) 07740 #define ITM_SP3_STIMULUS_BIT (0) 07741 #define ITM_SP3_STIMULUS_BITS (32) 07742 07743 #define ITM_SP4 *((volatile int32u *)0xE0000010u) 07744 #define ITM_SP4_REG *((volatile int32u *)0xE0000010u) 07745 #define ITM_SP4_ADDR (0xE0000010u) 07746 #define ITM_SP4_RESET (0x00000000u) 07747 /* FIFOREADY field */ 07748 #define ITM_SP4_FIFOREADY (0x00000001u) 07749 #define ITM_SP4_FIFOREADY_MASK (0x00000001u) 07750 #define ITM_SP4_FIFOREADY_BIT (0) 07751 #define ITM_SP4_FIFOREADY_BITS (1) 07752 /* STIMULUS field */ 07753 #define ITM_SP4_STIMULUS (0xFFFFFFFFu) 07754 #define ITM_SP4_STIMULUS_MASK (0xFFFFFFFFu) 07755 #define ITM_SP4_STIMULUS_BIT (0) 07756 #define ITM_SP4_STIMULUS_BITS (32) 07757 07758 #define ITM_SP5 *((volatile int32u *)0xE0000014u) 07759 #define ITM_SP5_REG *((volatile int32u *)0xE0000014u) 07760 #define ITM_SP5_ADDR (0xE0000014u) 07761 #define ITM_SP5_RESET (0x00000000u) 07762 /* FIFOREADY field */ 07763 #define ITM_SP5_FIFOREADY (0x00000001u) 07764 #define ITM_SP5_FIFOREADY_MASK (0x00000001u) 07765 #define ITM_SP5_FIFOREADY_BIT (0) 07766 #define ITM_SP5_FIFOREADY_BITS (1) 07767 /* STIMULUS field */ 07768 #define ITM_SP5_STIMULUS (0xFFFFFFFFu) 07769 #define ITM_SP5_STIMULUS_MASK (0xFFFFFFFFu) 07770 #define ITM_SP5_STIMULUS_BIT (0) 07771 #define ITM_SP5_STIMULUS_BITS (32) 07772 07773 #define ITM_SP6 *((volatile int32u *)0xE0000018u) 07774 #define ITM_SP6_REG *((volatile int32u *)0xE0000018u) 07775 #define ITM_SP6_ADDR (0xE0000018u) 07776 #define ITM_SP6_RESET (0x00000000u) 07777 /* FIFOREADY field */ 07778 #define ITM_SP6_FIFOREADY (0x00000001u) 07779 #define ITM_SP6_FIFOREADY_MASK (0x00000001u) 07780 #define ITM_SP6_FIFOREADY_BIT (0) 07781 #define ITM_SP6_FIFOREADY_BITS (1) 07782 /* STIMULUS field */ 07783 #define ITM_SP6_STIMULUS (0xFFFFFFFFu) 07784 #define ITM_SP6_STIMULUS_MASK (0xFFFFFFFFu) 07785 #define ITM_SP6_STIMULUS_BIT (0) 07786 #define ITM_SP6_STIMULUS_BITS (32) 07787 07788 #define ITM_SP7 *((volatile int32u *)0xE000001Cu) 07789 #define ITM_SP7_REG *((volatile int32u *)0xE000001Cu) 07790 #define ITM_SP7_ADDR (0xE000001Cu) 07791 #define ITM_SP7_RESET (0x00000000u) 07792 /* FIFOREADY field */ 07793 #define ITM_SP7_FIFOREADY (0x00000001u) 07794 #define ITM_SP7_FIFOREADY_MASK (0x00000001u) 07795 #define ITM_SP7_FIFOREADY_BIT (0) 07796 #define ITM_SP7_FIFOREADY_BITS (1) 07797 /* STIMULUS field */ 07798 #define ITM_SP7_STIMULUS (0xFFFFFFFFu) 07799 #define ITM_SP7_STIMULUS_MASK (0xFFFFFFFFu) 07800 #define ITM_SP7_STIMULUS_BIT (0) 07801 #define ITM_SP7_STIMULUS_BITS (32) 07802 07803 #define ITM_SP8 *((volatile int32u *)0xE0000020u) 07804 #define ITM_SP8_REG *((volatile int32u *)0xE0000020u) 07805 #define ITM_SP8_ADDR (0xE0000020u) 07806 #define ITM_SP8_RESET (0x00000000u) 07807 /* FIFOREADY field */ 07808 #define ITM_SP8_FIFOREADY (0x00000001u) 07809 #define ITM_SP8_FIFOREADY_MASK (0x00000001u) 07810 #define ITM_SP8_FIFOREADY_BIT (0) 07811 #define ITM_SP8_FIFOREADY_BITS (1) 07812 /* STIMULUS field */ 07813 #define ITM_SP8_STIMULUS (0xFFFFFFFFu) 07814 #define ITM_SP8_STIMULUS_MASK (0xFFFFFFFFu) 07815 #define ITM_SP8_STIMULUS_BIT (0) 07816 #define ITM_SP8_STIMULUS_BITS (32) 07817 07818 #define ITM_SP9 *((volatile int32u *)0xE0000024u) 07819 #define ITM_SP9_REG *((volatile int32u *)0xE0000024u) 07820 #define ITM_SP9_ADDR (0xE0000024u) 07821 #define ITM_SP9_RESET (0x00000000u) 07822 /* FIFOREADY field */ 07823 #define ITM_SP9_FIFOREADY (0x00000001u) 07824 #define ITM_SP9_FIFOREADY_MASK (0x00000001u) 07825 #define ITM_SP9_FIFOREADY_BIT (0) 07826 #define ITM_SP9_FIFOREADY_BITS (1) 07827 /* STIMULUS field */ 07828 #define ITM_SP9_STIMULUS (0xFFFFFFFFu) 07829 #define ITM_SP9_STIMULUS_MASK (0xFFFFFFFFu) 07830 #define ITM_SP9_STIMULUS_BIT (0) 07831 #define ITM_SP9_STIMULUS_BITS (32) 07832 07833 #define ITM_SP10 *((volatile int32u *)0xE0000028u) 07834 #define ITM_SP10_REG *((volatile int32u *)0xE0000028u) 07835 #define ITM_SP10_ADDR (0xE0000028u) 07836 #define ITM_SP10_RESET (0x00000000u) 07837 /* FIFOREADY field */ 07838 #define ITM_SP10_FIFOREADY (0x00000001u) 07839 #define ITM_SP10_FIFOREADY_MASK (0x00000001u) 07840 #define ITM_SP10_FIFOREADY_BIT (0) 07841 #define ITM_SP10_FIFOREADY_BITS (1) 07842 /* STIMULUS field */ 07843 #define ITM_SP10_STIMULUS (0xFFFFFFFFu) 07844 #define ITM_SP10_STIMULUS_MASK (0xFFFFFFFFu) 07845 #define ITM_SP10_STIMULUS_BIT (0) 07846 #define ITM_SP10_STIMULUS_BITS (32) 07847 07848 #define ITM_SP11 *((volatile int32u *)0xE000002Cu) 07849 #define ITM_SP11_REG *((volatile int32u *)0xE000002Cu) 07850 #define ITM_SP11_ADDR (0xE000002Cu) 07851 #define ITM_SP11_RESET (0x00000000u) 07852 /* FIFOREADY field */ 07853 #define ITM_SP11_FIFOREADY (0x00000001u) 07854 #define ITM_SP11_FIFOREADY_MASK (0x00000001u) 07855 #define ITM_SP11_FIFOREADY_BIT (0) 07856 #define ITM_SP11_FIFOREADY_BITS (1) 07857 /* STIMULUS field */ 07858 #define ITM_SP11_STIMULUS (0xFFFFFFFFu) 07859 #define ITM_SP11_STIMULUS_MASK (0xFFFFFFFFu) 07860 #define ITM_SP11_STIMULUS_BIT (0) 07861 #define ITM_SP11_STIMULUS_BITS (32) 07862 07863 #define ITM_SP12 *((volatile int32u *)0xE0000030u) 07864 #define ITM_SP12_REG *((volatile int32u *)0xE0000030u) 07865 #define ITM_SP12_ADDR (0xE0000030u) 07866 #define ITM_SP12_RESET (0x00000000u) 07867 /* FIFOREADY field */ 07868 #define ITM_SP12_FIFOREADY (0x00000001u) 07869 #define ITM_SP12_FIFOREADY_MASK (0x00000001u) 07870 #define ITM_SP12_FIFOREADY_BIT (0) 07871 #define ITM_SP12_FIFOREADY_BITS (1) 07872 /* STIMULUS field */ 07873 #define ITM_SP12_STIMULUS (0xFFFFFFFFu) 07874 #define ITM_SP12_STIMULUS_MASK (0xFFFFFFFFu) 07875 #define ITM_SP12_STIMULUS_BIT (0) 07876 #define ITM_SP12_STIMULUS_BITS (32) 07877 07878 #define ITM_SP13 *((volatile int32u *)0xE0000034u) 07879 #define ITM_SP13_REG *((volatile int32u *)0xE0000034u) 07880 #define ITM_SP13_ADDR (0xE0000034u) 07881 #define ITM_SP13_RESET (0x00000000u) 07882 /* FIFOREADY field */ 07883 #define ITM_SP13_FIFOREADY (0x00000001u) 07884 #define ITM_SP13_FIFOREADY_MASK (0x00000001u) 07885 #define ITM_SP13_FIFOREADY_BIT (0) 07886 #define ITM_SP13_FIFOREADY_BITS (1) 07887 /* STIMULUS field */ 07888 #define ITM_SP13_STIMULUS (0xFFFFFFFFu) 07889 #define ITM_SP13_STIMULUS_MASK (0xFFFFFFFFu) 07890 #define ITM_SP13_STIMULUS_BIT (0) 07891 #define ITM_SP13_STIMULUS_BITS (32) 07892 07893 #define ITM_SP14 *((volatile int32u *)0xE0000038u) 07894 #define ITM_SP14_REG *((volatile int32u *)0xE0000038u) 07895 #define ITM_SP14_ADDR (0xE0000038u) 07896 #define ITM_SP14_RESET (0x00000000u) 07897 /* FIFOREADY field */ 07898 #define ITM_SP14_FIFOREADY (0x00000001u) 07899 #define ITM_SP14_FIFOREADY_MASK (0x00000001u) 07900 #define ITM_SP14_FIFOREADY_BIT (0) 07901 #define ITM_SP14_FIFOREADY_BITS (1) 07902 /* STIMULUS field */ 07903 #define ITM_SP14_STIMULUS (0xFFFFFFFFu) 07904 #define ITM_SP14_STIMULUS_MASK (0xFFFFFFFFu) 07905 #define ITM_SP14_STIMULUS_BIT (0) 07906 #define ITM_SP14_STIMULUS_BITS (32) 07907 07908 #define ITM_SP15 *((volatile int32u *)0xE000003Cu) 07909 #define ITM_SP15_REG *((volatile int32u *)0xE000003Cu) 07910 #define ITM_SP15_ADDR (0xE000003Cu) 07911 #define ITM_SP15_RESET (0x00000000u) 07912 /* FIFOREADY field */ 07913 #define ITM_SP15_FIFOREADY (0x00000001u) 07914 #define ITM_SP15_FIFOREADY_MASK (0x00000001u) 07915 #define ITM_SP15_FIFOREADY_BIT (0) 07916 #define ITM_SP15_FIFOREADY_BITS (1) 07917 /* STIMULUS field */ 07918 #define ITM_SP15_STIMULUS (0xFFFFFFFFu) 07919 #define ITM_SP15_STIMULUS_MASK (0xFFFFFFFFu) 07920 #define ITM_SP15_STIMULUS_BIT (0) 07921 #define ITM_SP15_STIMULUS_BITS (32) 07922 07923 #define ITM_SP16 *((volatile int32u *)0xE0000040u) 07924 #define ITM_SP16_REG *((volatile int32u *)0xE0000040u) 07925 #define ITM_SP16_ADDR (0xE0000040u) 07926 #define ITM_SP16_RESET (0x00000000u) 07927 /* FIFOREADY field */ 07928 #define ITM_SP16_FIFOREADY (0x00000001u) 07929 #define ITM_SP16_FIFOREADY_MASK (0x00000001u) 07930 #define ITM_SP16_FIFOREADY_BIT (0) 07931 #define ITM_SP16_FIFOREADY_BITS (1) 07932 /* STIMULUS field */ 07933 #define ITM_SP16_STIMULUS (0xFFFFFFFFu) 07934 #define ITM_SP16_STIMULUS_MASK (0xFFFFFFFFu) 07935 #define ITM_SP16_STIMULUS_BIT (0) 07936 #define ITM_SP16_STIMULUS_BITS (32) 07937 07938 #define ITM_SP17 *((volatile int32u *)0xE0000044u) 07939 #define ITM_SP17_REG *((volatile int32u *)0xE0000044u) 07940 #define ITM_SP17_ADDR (0xE0000044u) 07941 #define ITM_SP17_RESET (0x00000000u) 07942 /* FIFOREADY field */ 07943 #define ITM_SP17_FIFOREADY (0x00000001u) 07944 #define ITM_SP17_FIFOREADY_MASK (0x00000001u) 07945 #define ITM_SP17_FIFOREADY_BIT (0) 07946 #define ITM_SP17_FIFOREADY_BITS (1) 07947 /* STIMULUS field */ 07948 #define ITM_SP17_STIMULUS (0xFFFFFFFFu) 07949 #define ITM_SP17_STIMULUS_MASK (0xFFFFFFFFu) 07950 #define ITM_SP17_STIMULUS_BIT (0) 07951 #define ITM_SP17_STIMULUS_BITS (32) 07952 07953 #define ITM_SP18 *((volatile int32u *)0xE0000048u) 07954 #define ITM_SP18_REG *((volatile int32u *)0xE0000048u) 07955 #define ITM_SP18_ADDR (0xE0000048u) 07956 #define ITM_SP18_RESET (0x00000000u) 07957 /* FIFOREADY field */ 07958 #define ITM_SP18_FIFOREADY (0x00000001u) 07959 #define ITM_SP18_FIFOREADY_MASK (0x00000001u) 07960 #define ITM_SP18_FIFOREADY_BIT (0) 07961 #define ITM_SP18_FIFOREADY_BITS (1) 07962 /* STIMULUS field */ 07963 #define ITM_SP18_STIMULUS (0xFFFFFFFFu) 07964 #define ITM_SP18_STIMULUS_MASK (0xFFFFFFFFu) 07965 #define ITM_SP18_STIMULUS_BIT (0) 07966 #define ITM_SP18_STIMULUS_BITS (32) 07967 07968 #define ITM_SP19 *((volatile int32u *)0xE000004Cu) 07969 #define ITM_SP19_REG *((volatile int32u *)0xE000004Cu) 07970 #define ITM_SP19_ADDR (0xE000004Cu) 07971 #define ITM_SP19_RESET (0x00000000u) 07972 /* FIFOREADY field */ 07973 #define ITM_SP19_FIFOREADY (0x00000001u) 07974 #define ITM_SP19_FIFOREADY_MASK (0x00000001u) 07975 #define ITM_SP19_FIFOREADY_BIT (0) 07976 #define ITM_SP19_FIFOREADY_BITS (1) 07977 /* STIMULUS field */ 07978 #define ITM_SP19_STIMULUS (0xFFFFFFFFu) 07979 #define ITM_SP19_STIMULUS_MASK (0xFFFFFFFFu) 07980 #define ITM_SP19_STIMULUS_BIT (0) 07981 #define ITM_SP19_STIMULUS_BITS (32) 07982 07983 #define ITM_SP20 *((volatile int32u *)0xE0000050u) 07984 #define ITM_SP20_REG *((volatile int32u *)0xE0000050u) 07985 #define ITM_SP20_ADDR (0xE0000050u) 07986 #define ITM_SP20_RESET (0x00000000u) 07987 /* FIFOREADY field */ 07988 #define ITM_SP20_FIFOREADY (0x00000001u) 07989 #define ITM_SP20_FIFOREADY_MASK (0x00000001u) 07990 #define ITM_SP20_FIFOREADY_BIT (0) 07991 #define ITM_SP20_FIFOREADY_BITS (1) 07992 /* STIMULUS field */ 07993 #define ITM_SP20_STIMULUS (0xFFFFFFFFu) 07994 #define ITM_SP20_STIMULUS_MASK (0xFFFFFFFFu) 07995 #define ITM_SP20_STIMULUS_BIT (0) 07996 #define ITM_SP20_STIMULUS_BITS (32) 07997 07998 #define ITM_SP21 *((volatile int32u *)0xE0000054u) 07999 #define ITM_SP21_REG *((volatile int32u *)0xE0000054u) 08000 #define ITM_SP21_ADDR (0xE0000054u) 08001 #define ITM_SP21_RESET (0x00000000u) 08002 /* FIFOREADY field */ 08003 #define ITM_SP21_FIFOREADY (0x00000001u) 08004 #define ITM_SP21_FIFOREADY_MASK (0x00000001u) 08005 #define ITM_SP21_FIFOREADY_BIT (0) 08006 #define ITM_SP21_FIFOREADY_BITS (1) 08007 /* STIMULUS field */ 08008 #define ITM_SP21_STIMULUS (0xFFFFFFFFu) 08009 #define ITM_SP21_STIMULUS_MASK (0xFFFFFFFFu) 08010 #define ITM_SP21_STIMULUS_BIT (0) 08011 #define ITM_SP21_STIMULUS_BITS (32) 08012 08013 #define ITM_SP22 *((volatile int32u *)0xE0000058u) 08014 #define ITM_SP22_REG *((volatile int32u *)0xE0000058u) 08015 #define ITM_SP22_ADDR (0xE0000058u) 08016 #define ITM_SP22_RESET (0x00000000u) 08017 /* FIFOREADY field */ 08018 #define ITM_SP22_FIFOREADY (0x00000001u) 08019 #define ITM_SP22_FIFOREADY_MASK (0x00000001u) 08020 #define ITM_SP22_FIFOREADY_BIT (0) 08021 #define ITM_SP22_FIFOREADY_BITS (1) 08022 /* STIMULUS field */ 08023 #define ITM_SP22_STIMULUS (0xFFFFFFFFu) 08024 #define ITM_SP22_STIMULUS_MASK (0xFFFFFFFFu) 08025 #define ITM_SP22_STIMULUS_BIT (0) 08026 #define ITM_SP22_STIMULUS_BITS (32) 08027 08028 #define ITM_SP23 *((volatile int32u *)0xE000005Cu) 08029 #define ITM_SP23_REG *((volatile int32u *)0xE000005Cu) 08030 #define ITM_SP23_ADDR (0xE000005Cu) 08031 #define ITM_SP23_RESET (0x00000000u) 08032 /* FIFOREADY field */ 08033 #define ITM_SP23_FIFOREADY (0x00000001u) 08034 #define ITM_SP23_FIFOREADY_MASK (0x00000001u) 08035 #define ITM_SP23_FIFOREADY_BIT (0) 08036 #define ITM_SP23_FIFOREADY_BITS (1) 08037 /* STIMULUS field */ 08038 #define ITM_SP23_STIMULUS (0xFFFFFFFFu) 08039 #define ITM_SP23_STIMULUS_MASK (0xFFFFFFFFu) 08040 #define ITM_SP23_STIMULUS_BIT (0) 08041 #define ITM_SP23_STIMULUS_BITS (32) 08042 08043 #define ITM_SP24 *((volatile int32u *)0xE0000060u) 08044 #define ITM_SP24_REG *((volatile int32u *)0xE0000060u) 08045 #define ITM_SP24_ADDR (0xE0000060u) 08046 #define ITM_SP24_RESET (0x00000000u) 08047 /* FIFOREADY field */ 08048 #define ITM_SP24_FIFOREADY (0x00000001u) 08049 #define ITM_SP24_FIFOREADY_MASK (0x00000001u) 08050 #define ITM_SP24_FIFOREADY_BIT (0) 08051 #define ITM_SP24_FIFOREADY_BITS (1) 08052 /* STIMULUS field */ 08053 #define ITM_SP24_STIMULUS (0xFFFFFFFFu) 08054 #define ITM_SP24_STIMULUS_MASK (0xFFFFFFFFu) 08055 #define ITM_SP24_STIMULUS_BIT (0) 08056 #define ITM_SP24_STIMULUS_BITS (32) 08057 08058 #define ITM_SP25 *((volatile int32u *)0xE0000064u) 08059 #define ITM_SP25_REG *((volatile int32u *)0xE0000064u) 08060 #define ITM_SP25_ADDR (0xE0000064u) 08061 #define ITM_SP25_RESET (0x00000000u) 08062 /* FIFOREADY field */ 08063 #define ITM_SP25_FIFOREADY (0x00000001u) 08064 #define ITM_SP25_FIFOREADY_MASK (0x00000001u) 08065 #define ITM_SP25_FIFOREADY_BIT (0) 08066 #define ITM_SP25_FIFOREADY_BITS (1) 08067 /* STIMULUS field */ 08068 #define ITM_SP25_STIMULUS (0xFFFFFFFFu) 08069 #define ITM_SP25_STIMULUS_MASK (0xFFFFFFFFu) 08070 #define ITM_SP25_STIMULUS_BIT (0) 08071 #define ITM_SP25_STIMULUS_BITS (32) 08072 08073 #define ITM_SP26 *((volatile int32u *)0xE0000068u) 08074 #define ITM_SP26_REG *((volatile int32u *)0xE0000068u) 08075 #define ITM_SP26_ADDR (0xE0000068u) 08076 #define ITM_SP26_RESET (0x00000000u) 08077 /* FIFOREADY field */ 08078 #define ITM_SP26_FIFOREADY (0x00000001u) 08079 #define ITM_SP26_FIFOREADY_MASK (0x00000001u) 08080 #define ITM_SP26_FIFOREADY_BIT (0) 08081 #define ITM_SP26_FIFOREADY_BITS (1) 08082 /* STIMULUS field */ 08083 #define ITM_SP26_STIMULUS (0xFFFFFFFFu) 08084 #define ITM_SP26_STIMULUS_MASK (0xFFFFFFFFu) 08085 #define ITM_SP26_STIMULUS_BIT (0) 08086 #define ITM_SP26_STIMULUS_BITS (32) 08087 08088 #define ITM_SP27 *((volatile int32u *)0xE000006Cu) 08089 #define ITM_SP27_REG *((volatile int32u *)0xE000006Cu) 08090 #define ITM_SP27_ADDR (0xE000006Cu) 08091 #define ITM_SP27_RESET (0x00000000u) 08092 /* FIFOREADY field */ 08093 #define ITM_SP27_FIFOREADY (0x00000001u) 08094 #define ITM_SP27_FIFOREADY_MASK (0x00000001u) 08095 #define ITM_SP27_FIFOREADY_BIT (0) 08096 #define ITM_SP27_FIFOREADY_BITS (1) 08097 /* STIMULUS field */ 08098 #define ITM_SP27_STIMULUS (0xFFFFFFFFu) 08099 #define ITM_SP27_STIMULUS_MASK (0xFFFFFFFFu) 08100 #define ITM_SP27_STIMULUS_BIT (0) 08101 #define ITM_SP27_STIMULUS_BITS (32) 08102 08103 #define ITM_SP28 *((volatile int32u *)0xE0000070u) 08104 #define ITM_SP28_REG *((volatile int32u *)0xE0000070u) 08105 #define ITM_SP28_ADDR (0xE0000070u) 08106 #define ITM_SP28_RESET (0x00000000u) 08107 /* FIFOREADY field */ 08108 #define ITM_SP28_FIFOREADY (0x00000001u) 08109 #define ITM_SP28_FIFOREADY_MASK (0x00000001u) 08110 #define ITM_SP28_FIFOREADY_BIT (0) 08111 #define ITM_SP28_FIFOREADY_BITS (1) 08112 /* STIMULUS field */ 08113 #define ITM_SP28_STIMULUS (0xFFFFFFFFu) 08114 #define ITM_SP28_STIMULUS_MASK (0xFFFFFFFFu) 08115 #define ITM_SP28_STIMULUS_BIT (0) 08116 #define ITM_SP28_STIMULUS_BITS (32) 08117 08118 #define ITM_SP29 *((volatile int32u *)0xE0000074u) 08119 #define ITM_SP29_REG *((volatile int32u *)0xE0000074u) 08120 #define ITM_SP29_ADDR (0xE0000074u) 08121 #define ITM_SP29_RESET (0x00000000u) 08122 /* FIFOREADY field */ 08123 #define ITM_SP29_FIFOREADY (0x00000001u) 08124 #define ITM_SP29_FIFOREADY_MASK (0x00000001u) 08125 #define ITM_SP29_FIFOREADY_BIT (0) 08126 #define ITM_SP29_FIFOREADY_BITS (1) 08127 /* STIMULUS field */ 08128 #define ITM_SP29_STIMULUS (0xFFFFFFFFu) 08129 #define ITM_SP29_STIMULUS_MASK (0xFFFFFFFFu) 08130 #define ITM_SP29_STIMULUS_BIT (0) 08131 #define ITM_SP29_STIMULUS_BITS (32) 08132 08133 #define ITM_SP30 *((volatile int32u *)0xE0000078u) 08134 #define ITM_SP30_REG *((volatile int32u *)0xE0000078u) 08135 #define ITM_SP30_ADDR (0xE0000078u) 08136 #define ITM_SP30_RESET (0x00000000u) 08137 /* FIFOREADY field */ 08138 #define ITM_SP30_FIFOREADY (0x00000001u) 08139 #define ITM_SP30_FIFOREADY_MASK (0x00000001u) 08140 #define ITM_SP30_FIFOREADY_BIT (0) 08141 #define ITM_SP30_FIFOREADY_BITS (1) 08142 /* STIMULUS field */ 08143 #define ITM_SP30_STIMULUS (0xFFFFFFFFu) 08144 #define ITM_SP30_STIMULUS_MASK (0xFFFFFFFFu) 08145 #define ITM_SP30_STIMULUS_BIT (0) 08146 #define ITM_SP30_STIMULUS_BITS (32) 08147 08148 #define ITM_SP31 *((volatile int32u *)0xE000007Cu) 08149 #define ITM_SP31_REG *((volatile int32u *)0xE000007Cu) 08150 #define ITM_SP31_ADDR (0xE000007Cu) 08151 #define ITM_SP31_RESET (0x00000000u) 08152 /* FIFOREADY field */ 08153 #define ITM_SP31_FIFOREADY (0x00000001u) 08154 #define ITM_SP31_FIFOREADY_MASK (0x00000001u) 08155 #define ITM_SP31_FIFOREADY_BIT (0) 08156 #define ITM_SP31_FIFOREADY_BITS (1) 08157 /* STIMULUS field */ 08158 #define ITM_SP31_STIMULUS (0xFFFFFFFFu) 08159 #define ITM_SP31_STIMULUS_MASK (0xFFFFFFFFu) 08160 #define ITM_SP31_STIMULUS_BIT (0) 08161 #define ITM_SP31_STIMULUS_BITS (32) 08162 08163 #define ITM_TER *((volatile int32u *)0xE0000E00u) 08164 #define ITM_TER_REG *((volatile int32u *)0xE0000E00u) 08165 #define ITM_TER_ADDR (0xE0000E00u) 08166 #define ITM_TER_RESET (0x00000000u) 08167 /* STIMENA field */ 08168 #define ITM_TER_STIMENA (0xFFFFFFFFu) 08169 #define ITM_TER_STIMENA_MASK (0xFFFFFFFFu) 08170 #define ITM_TER_STIMENA_BIT (0) 08171 #define ITM_TER_STIMENA_BITS (32) 08172 08173 #define ITM_TPR *((volatile int32u *)0xE0000E40u) 08174 #define ITM_TPR_REG *((volatile int32u *)0xE0000E40u) 08175 #define ITM_TPR_ADDR (0xE0000E40u) 08176 #define ITM_TPR_RESET (0x00000000u) 08177 /* PRIVMASK field */ 08178 #define ITM_TPR_PRIVMASK (0x0000000Fu) 08179 #define ITM_TPR_PRIVMASK_MASK (0x0000000Fu) 08180 #define ITM_TPR_PRIVMASK_BIT (0) 08181 #define ITM_TPR_PRIVMASK_BITS (4) 08182 08183 #define ITM_TCR *((volatile int32u *)0xE0000E80u) 08184 #define ITM_TCR_REG *((volatile int32u *)0xE0000E80u) 08185 #define ITM_TCR_ADDR (0xE0000E80u) 08186 #define ITM_TCR_RESET (0x00000000u) 08187 /* BUSY field */ 08188 #define ITM_TCR_BUSY (0x00800000u) 08189 #define ITM_TCR_BUSY_MASK (0x00800000u) 08190 #define ITM_TCR_BUSY_BIT (23) 08191 #define ITM_TCR_BUSY_BITS (1) 08192 /* ATBID field */ 08193 #define ITM_TCR_ATBID (0x007F0000u) 08194 #define ITM_TCR_ATBID_MASK (0x007F0000u) 08195 #define ITM_TCR_ATBID_BIT (16) 08196 #define ITM_TCR_ATBID_BITS (7) 08197 /* TSPRESCALE field */ 08198 #define ITM_TCR_TSPRESCALE (0x00000300u) 08199 #define ITM_TCR_TSPRESCALE_MASK (0x00000300u) 08200 #define ITM_TCR_TSPRESCALE_BIT (8) 08201 #define ITM_TCR_TSPRESCALE_BITS (2) 08202 /* SWOENA field */ 08203 #define ITM_TCR_SWOENA (0x00000010u) 08204 #define ITM_TCR_SWOENA_MASK (0x00000010u) 08205 #define ITM_TCR_SWOENA_BIT (4) 08206 #define ITM_TCR_SWOENA_BITS (1) 08207 /* DWTENA field */ 08208 #define ITM_TCR_DWTENA (0x00000008u) 08209 #define ITM_TCR_DWTENA_MASK (0x00000008u) 08210 #define ITM_TCR_DWTENA_BIT (3) 08211 #define ITM_TCR_DWTENA_BITS (1) 08212 /* SYNCENA field */ 08213 #define ITM_TCR_SYNCENA (0x00000004u) 08214 #define ITM_TCR_SYNCENA_MASK (0x00000004u) 08215 #define ITM_TCR_SYNCENA_BIT (2) 08216 #define ITM_TCR_SYNCENA_BITS (1) 08217 /* TSENA field */ 08218 #define ITM_TCR_TSENA (0x00000002u) 08219 #define ITM_TCR_TSENA_MASK (0x00000002u) 08220 #define ITM_TCR_TSENA_BIT (1) 08221 #define ITM_TCR_TSENA_BITS (1) 08222 /* ITMEN field */ 08223 #define ITM_TCR_ITMEN (0x00000001u) 08224 #define ITM_TCR_ITMEN_MASK (0x00000001u) 08225 #define ITM_TCR_ITMEN_BIT (0) 08226 #define ITM_TCR_ITMEN_BITS (1) 08227 08228 #define ITM_IW *((volatile int32u *)0xE0000EF8u) 08229 #define ITM_IW_REG *((volatile int32u *)0xE0000EF8u) 08230 #define ITM_IW_ADDR (0xE0000EF8u) 08231 #define ITM_IW_RESET (0x00000000u) 08232 /* ATVALIDM field */ 08233 #define ITM_IW_ATVALIDM (0x00000001u) 08234 #define ITM_IW_ATVALIDM_MASK (0x00000001u) 08235 #define ITM_IW_ATVALIDM_BIT (0) 08236 #define ITM_IW_ATVALIDM_BITS (1) 08237 08238 #define ITM_IR *((volatile int32u *)0xE0000EFCu) 08239 #define ITM_IR_REG *((volatile int32u *)0xE0000EFCu) 08240 #define ITM_IR_ADDR (0xE0000EFCu) 08241 #define ITM_IR_RESET (0x00000000u) 08242 /* ATREADYM field */ 08243 #define ITM_IR_ATREADYM (0x00000001u) 08244 #define ITM_IR_ATREADYM_MASK (0x00000001u) 08245 #define ITM_IR_ATREADYM_BIT (0) 08246 #define ITM_IR_ATREADYM_BITS (1) 08247 08248 #define ITM_IMC *((volatile int32u *)0xE0000F00u) 08249 #define ITM_IMC_REG *((volatile int32u *)0xE0000F00u) 08250 #define ITM_IMC_ADDR (0xE0000F00u) 08251 #define ITM_IMC_RESET (0x00000000u) 08252 /* INTEGRATION field */ 08253 #define ITM_IMC_INTEGRATION (0x00000001u) 08254 #define ITM_IMC_INTEGRATION_MASK (0x00000001u) 08255 #define ITM_IMC_INTEGRATION_BIT (0) 08256 #define ITM_IMC_INTEGRATION_BITS (1) 08257 08258 #define ITM_LA *((volatile int32u *)0xE0000FB0u) 08259 #define ITM_LA_REG *((volatile int32u *)0xE0000FB0u) 08260 #define ITM_LA_ADDR (0xE0000FB0u) 08261 #define ITM_LA_RESET (0x00000000u) 08262 /* LOCKACC field */ 08263 #define ITM_LA_LOCKACC (0xFFFFFFFFu) 08264 #define ITM_LA_LOCKACC_MASK (0xFFFFFFFFu) 08265 #define ITM_LA_LOCKACC_BIT (0) 08266 #define ITM_LA_LOCKACC_BITS (32) 08267 08268 #define ITM_LS *((volatile int32u *)0xE0000FB4u) 08269 #define ITM_LS_REG *((volatile int32u *)0xE0000FB4u) 08270 #define ITM_LS_ADDR (0xE0000FB4u) 08271 #define ITM_LS_RESET (0x00000000u) 08272 /* BYTEACC field */ 08273 #define ITM_LS_BYTEACC (0x00000004u) 08274 #define ITM_LS_BYTEACC_MASK (0x00000004u) 08275 #define ITM_LS_BYTEACC_BIT (2) 08276 #define ITM_LS_BYTEACC_BITS (1) 08277 /* ACCESS field */ 08278 #define ITM_LS_ACCESS (0x00000002u) 08279 #define ITM_LS_ACCESS_MASK (0x00000002u) 08280 #define ITM_LS_ACCESS_BIT (1) 08281 #define ITM_LS_ACCESS_BITS (1) 08282 /* PRESENT field */ 08283 #define ITM_LS_PRESENT (0x00000001u) 08284 #define ITM_LS_PRESENT_MASK (0x00000001u) 08285 #define ITM_LS_PRESENT_BIT (0) 08286 #define ITM_LS_PRESENT_BITS (1) 08287 08288 #define ITM_PERIPHID4 *((volatile int32u *)0xE0000FD0u) 08289 #define ITM_PERIPHID4_REG *((volatile int32u *)0xE0000FD0u) 08290 #define ITM_PERIPHID4_ADDR (0xE0000FD0u) 08291 #define ITM_PERIPHID4_RESET (0x00000004u) 08292 /* PERIPHID field */ 08293 #define ITM_PERIPHID4_PERIPHID (0xFFFFFFFFu) 08294 #define ITM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) 08295 #define ITM_PERIPHID4_PERIPHID_BIT (0) 08296 #define ITM_PERIPHID4_PERIPHID_BITS (32) 08297 08298 #define ITM_PERIPHID5 *((volatile int32u *)0xE0000FD4u) 08299 #define ITM_PERIPHID5_REG *((volatile int32u *)0xE0000FD4u) 08300 #define ITM_PERIPHID5_ADDR (0xE0000FD4u) 08301 #define ITM_PERIPHID5_RESET (0x00000000u) 08302 /* PERIPHID field */ 08303 #define ITM_PERIPHID5_PERIPHID (0xFFFFFFFFu) 08304 #define ITM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) 08305 #define ITM_PERIPHID5_PERIPHID_BIT (0) 08306 #define ITM_PERIPHID5_PERIPHID_BITS (32) 08307 08308 #define ITM_PERIPHID6 *((volatile int32u *)0xE0000FD8u) 08309 #define ITM_PERIPHID6_REG *((volatile int32u *)0xE0000FD8u) 08310 #define ITM_PERIPHID6_ADDR (0xE0000FD8u) 08311 #define ITM_PERIPHID6_RESET (0x00000000u) 08312 /* PERIPHID field */ 08313 #define ITM_PERIPHID6_PERIPHID (0xFFFFFFFFu) 08314 #define ITM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) 08315 #define ITM_PERIPHID6_PERIPHID_BIT (0) 08316 #define ITM_PERIPHID6_PERIPHID_BITS (32) 08317 08318 #define ITM_PERIPHID7 *((volatile int32u *)0xE0000FDCu) 08319 #define ITM_PERIPHID7_REG *((volatile int32u *)0xE0000FDCu) 08320 #define ITM_PERIPHID7_ADDR (0xE0000FDCu) 08321 #define ITM_PERIPHID7_RESET (0x00000000u) 08322 /* PERIPHID field */ 08323 #define ITM_PERIPHID7_PERIPHID (0xFFFFFFFFu) 08324 #define ITM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) 08325 #define ITM_PERIPHID7_PERIPHID_BIT (0) 08326 #define ITM_PERIPHID7_PERIPHID_BITS (32) 08327 08328 #define ITM_PERIPHID0 *((volatile int32u *)0xE0000FE0u) 08329 #define ITM_PERIPHID0_REG *((volatile int32u *)0xE0000FE0u) 08330 #define ITM_PERIPHID0_ADDR (0xE0000FE0u) 08331 #define ITM_PERIPHID0_RESET (0x00000001u) 08332 /* PERIPHID field */ 08333 #define ITM_PERIPHID0_PERIPHID (0xFFFFFFFFu) 08334 #define ITM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) 08335 #define ITM_PERIPHID0_PERIPHID_BIT (0) 08336 #define ITM_PERIPHID0_PERIPHID_BITS (32) 08337 08338 #define ITM_PERIPHID1 *((volatile int32u *)0xE0000FE4u) 08339 #define ITM_PERIPHID1_REG *((volatile int32u *)0xE0000FE4u) 08340 #define ITM_PERIPHID1_ADDR (0xE0000FE4u) 08341 #define ITM_PERIPHID1_RESET (0x000000B0u) 08342 /* PERIPHID field */ 08343 #define ITM_PERIPHID1_PERIPHID (0xFFFFFFFFu) 08344 #define ITM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) 08345 #define ITM_PERIPHID1_PERIPHID_BIT (0) 08346 #define ITM_PERIPHID1_PERIPHID_BITS (32) 08347 08348 #define ITM_PERIPHID2 *((volatile int32u *)0xE0000FE8u) 08349 #define ITM_PERIPHID2_REG *((volatile int32u *)0xE0000FE8u) 08350 #define ITM_PERIPHID2_ADDR (0xE0000FE8u) 08351 #define ITM_PERIPHID2_RESET (0x0000001Bu) 08352 /* PERIPHID field */ 08353 #define ITM_PERIPHID2_PERIPHID (0xFFFFFFFFu) 08354 #define ITM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) 08355 #define ITM_PERIPHID2_PERIPHID_BIT (0) 08356 #define ITM_PERIPHID2_PERIPHID_BITS (32) 08357 08358 #define ITM_PERIPHID3 *((volatile int32u *)0xE0000FECu) 08359 #define ITM_PERIPHID3_REG *((volatile int32u *)0xE0000FECu) 08360 #define ITM_PERIPHID3_ADDR (0xE0000FECu) 08361 #define ITM_PERIPHID3_RESET (0x00000000u) 08362 /* PERIPHID field */ 08363 #define ITM_PERIPHID3_PERIPHID (0xFFFFFFFFu) 08364 #define ITM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) 08365 #define ITM_PERIPHID3_PERIPHID_BIT (0) 08366 #define ITM_PERIPHID3_PERIPHID_BITS (32) 08367 08368 #define ITM_CELLID0 *((volatile int32u *)0xE0000FF0u) 08369 #define ITM_CELLID0_REG *((volatile int32u *)0xE0000FF0u) 08370 #define ITM_CELLID0_ADDR (0xE0000FF0u) 08371 #define ITM_CELLID0_RESET (0x0000000Du) 08372 /* PERIPHID field */ 08373 #define ITM_CELLID0_PERIPHID (0xFFFFFFFFu) 08374 #define ITM_CELLID0_PERIPHID_MASK (0xFFFFFFFFu) 08375 #define ITM_CELLID0_PERIPHID_BIT (0) 08376 #define ITM_CELLID0_PERIPHID_BITS (32) 08377 08378 #define ITM_CELLID1 *((volatile int32u *)0xE0000FF4u) 08379 #define ITM_CELLID1_REG *((volatile int32u *)0xE0000FF4u) 08380 #define ITM_CELLID1_ADDR (0xE0000FF4u) 08381 #define ITM_CELLID1_RESET (0x000000E0u) 08382 /* PERIPHID field */ 08383 #define ITM_CELLID1_PERIPHID (0xFFFFFFFFu) 08384 #define ITM_CELLID1_PERIPHID_MASK (0xFFFFFFFFu) 08385 #define ITM_CELLID1_PERIPHID_BIT (0) 08386 #define ITM_CELLID1_PERIPHID_BITS (32) 08387 08388 #define ITM_CELLID2 *((volatile int32u *)0xE0000FF8u) 08389 #define ITM_CELLID2_REG *((volatile int32u *)0xE0000FF8u) 08390 #define ITM_CELLID2_ADDR (0xE0000FF8u) 08391 #define ITM_CELLID2_RESET (0x00000005u) 08392 /* PERIPHID field */ 08393 #define ITM_CELLID2_PERIPHID (0xFFFFFFFFu) 08394 #define ITM_CELLID2_PERIPHID_MASK (0xFFFFFFFFu) 08395 #define ITM_CELLID2_PERIPHID_BIT (0) 08396 #define ITM_CELLID2_PERIPHID_BITS (32) 08397 08398 #define ITM_CELLID3 *((volatile int32u *)0xE0000FFCu) 08399 #define ITM_CELLID3_REG *((volatile int32u *)0xE0000FFCu) 08400 #define ITM_CELLID3_ADDR (0xE0000FFCu) 08401 #define ITM_CELLID3_RESET (0x000000B1u) 08402 /* PERIPHID field */ 08403 #define ITM_CELLID3_PERIPHID (0xFFFFFFFFu) 08404 #define ITM_CELLID3_PERIPHID_MASK (0xFFFFFFFFu) 08405 #define ITM_CELLID3_PERIPHID_BIT (0) 08406 #define ITM_CELLID3_PERIPHID_BITS (32) 08407 08408 /* DWT block */ 08409 #define DATA_DWT_BASE (0xE0001000u) 08410 #define DATA_DWT_END (0xE0001FFFu) 08411 #define DATA_DWT_SIZE (DATA_DWT_END - DATA_DWT_BASE + 1) 08412 08413 #define DWT_CTRL *((volatile int32u *)0xE0001000u) 08414 #define DWT_CTRL_REG *((volatile int32u *)0xE0001000u) 08415 #define DWT_CTRL_ADDR (0xE0001000u) 08416 #define DWT_CTRL_RESET (0x40000000u) 08417 /* NUMCOMP field */ 08418 #define DWT_CTRL_NUMCOMP (0xF0000000u) 08419 #define DWT_CTRL_NUMCOMP_MASK (0xF0000000u) 08420 #define DWT_CTRL_NUMCOMP_BIT (28) 08421 #define DWT_CTRL_NUMCOMP_BITS (4) 08422 /* CYCEVTENA field */ 08423 #define DWT_CTRL_CYCEVTENA (0x00400000u) 08424 #define DWT_CTRL_CYCEVTENA_MASK (0x00400000u) 08425 #define DWT_CTRL_CYCEVTENA_BIT (22) 08426 #define DWT_CTRL_CYCEVTENA_BITS (1) 08427 /* FOLDEVTENA field */ 08428 #define DWT_CTRL_FOLDEVTENA (0x00200000u) 08429 #define DWT_CTRL_FOLDEVTENA_MASK (0x00200000u) 08430 #define DWT_CTRL_FOLDEVTENA_BIT (21) 08431 #define DWT_CTRL_FOLDEVTENA_BITS (1) 08432 /* LSUEVTENA field */ 08433 #define DWT_CTRL_LSUEVTENA (0x00100000u) 08434 #define DWT_CTRL_LSUEVTENA_MASK (0x00100000u) 08435 #define DWT_CTRL_LSUEVTENA_BIT (20) 08436 #define DWT_CTRL_LSUEVTENA_BITS (1) 08437 /* SLEEPEVTENA field */ 08438 #define DWT_CTRL_SLEEPEVTENA (0x00080000u) 08439 #define DWT_CTRL_SLEEPEVTENA_MASK (0x00080000u) 08440 #define DWT_CTRL_SLEEPEVTENA_BIT (19) 08441 #define DWT_CTRL_SLEEPEVTENA_BITS (1) 08442 /* EXCEVTENA field */ 08443 #define DWT_CTRL_EXCEVTENA (0x00040000u) 08444 #define DWT_CTRL_EXCEVTENA_MASK (0x00040000u) 08445 #define DWT_CTRL_EXCEVTENA_BIT (18) 08446 #define DWT_CTRL_EXCEVTENA_BITS (1) 08447 /* CPIEVTENA field */ 08448 #define DWT_CTRL_CPIEVTENA (0x00020000u) 08449 #define DWT_CTRL_CPIEVTENA_MASK (0x00020000u) 08450 #define DWT_CTRL_CPIEVTENA_BIT (17) 08451 #define DWT_CTRL_CPIEVTENA_BITS (1) 08452 /* EXCTRCENA field */ 08453 #define DWT_CTRL_EXCTRCENA (0x00010000u) 08454 #define DWT_CTRL_EXCTRCENA_MASK (0x00010000u) 08455 #define DWT_CTRL_EXCTRCENA_BIT (16) 08456 #define DWT_CTRL_EXCTRCENA_BITS (1) 08457 /* PCSAMPLEENA field */ 08458 #define DWT_CTRL_PCSAMPLEENA (0x00001000u) 08459 #define DWT_CTRL_PCSAMPLEENA_MASK (0x00001000u) 08460 #define DWT_CTRL_PCSAMPLEENA_BIT (12) 08461 #define DWT_CTRL_PCSAMPLEENA_BITS (1) 08462 /* SYNCTAP field */ 08463 #define DWT_CTRL_SYNCTAP (0x00000C00u) 08464 #define DWT_CTRL_SYNCTAP_MASK (0x00000C00u) 08465 #define DWT_CTRL_SYNCTAP_BIT (10) 08466 #define DWT_CTRL_SYNCTAP_BITS (2) 08467 /* CYCTAP field */ 08468 #define DWT_CTRL_CYCTAP (0x00000200u) 08469 #define DWT_CTRL_CYCTAP_MASK (0x00000200u) 08470 #define DWT_CTRL_CYCTAP_BIT (9) 08471 #define DWT_CTRL_CYCTAP_BITS (1) 08472 /* POSTCNT field */ 08473 #define DWT_CTRL_POSTCNT (0x000001E0u) 08474 #define DWT_CTRL_POSTCNT_MASK (0x000001E0u) 08475 #define DWT_CTRL_POSTCNT_BIT (5) 08476 #define DWT_CTRL_POSTCNT_BITS (4) 08477 /* POSTPRESET field */ 08478 #define DWT_CTRL_POSTPRESET (0x0000001Eu) 08479 #define DWT_CTRL_POSTPRESET_MASK (0x0000001Eu) 08480 #define DWT_CTRL_POSTPRESET_BIT (1) 08481 #define DWT_CTRL_POSTPRESET_BITS (4) 08482 /* CYCCNTENA field */ 08483 #define DWT_CTRL_CYCCNTENA (0x00000001u) 08484 #define DWT_CTRL_CYCCNTENA_MASK (0x00000001u) 08485 #define DWT_CTRL_CYCCNTENA_BIT (0) 08486 #define DWT_CTRL_CYCCNTENA_BITS (1) 08487 08488 #define DWT_CYCCNT *((volatile int32u *)0xE0001004u) 08489 #define DWT_CYCCNT_REG *((volatile int32u *)0xE0001004u) 08490 #define DWT_CYCCNT_ADDR (0xE0001004u) 08491 #define DWT_CYCCNT_RESET (0x00000000u) 08492 /* CYCCNT field */ 08493 #define DWT_CYCCNT_CYCCNT (0xFFFFFFFFu) 08494 #define DWT_CYCCNT_CYCCNT_MASK (0xFFFFFFFFu) 08495 #define DWT_CYCCNT_CYCCNT_BIT (0) 08496 #define DWT_CYCCNT_CYCCNT_BITS (32) 08497 08498 #define DWT_CPICNT *((volatile int32u *)0xE0001008u) 08499 #define DWT_CPICNT_REG *((volatile int32u *)0xE0001008u) 08500 #define DWT_CPICNT_ADDR (0xE0001008u) 08501 #define DWT_CPICNT_RESET (0x00000000u) 08502 /* CPICNT field */ 08503 #define DWT_CPICNT_CPICNT (0x000000FFu) 08504 #define DWT_CPICNT_CPICNT_MASK (0x000000FFu) 08505 #define DWT_CPICNT_CPICNT_BIT (0) 08506 #define DWT_CPICNT_CPICNT_BITS (8) 08507 08508 #define DWT_EXCCNT *((volatile int32u *)0xE000100Cu) 08509 #define DWT_EXCCNT_REG *((volatile int32u *)0xE000100Cu) 08510 #define DWT_EXCCNT_ADDR (0xE000100Cu) 08511 #define DWT_EXCCNT_RESET (0x00000000u) 08512 /* EXCCNT field */ 08513 #define DWT_EXCCNT_EXCCNT (0x000000FFu) 08514 #define DWT_EXCCNT_EXCCNT_MASK (0x000000FFu) 08515 #define DWT_EXCCNT_EXCCNT_BIT (0) 08516 #define DWT_EXCCNT_EXCCNT_BITS (8) 08517 08518 #define DWT_SLEEPCNT *((volatile int32u *)0xE0001010u) 08519 #define DWT_SLEEPCNT_REG *((volatile int32u *)0xE0001010u) 08520 #define DWT_SLEEPCNT_ADDR (0xE0001010u) 08521 #define DWT_SLEEPCNT_RESET (0x00000000u) 08522 /* SLEEPCNT field */ 08523 #define DWT_SLEEPCNT_SLEEPCNT (0x000000FFu) 08524 #define DWT_SLEEPCNT_SLEEPCNT_MASK (0x000000FFu) 08525 #define DWT_SLEEPCNT_SLEEPCNT_BIT (0) 08526 #define DWT_SLEEPCNT_SLEEPCNT_BITS (8) 08527 08528 #define DWT_LSUCNT *((volatile int32u *)0xE0001014u) 08529 #define DWT_LSUCNT_REG *((volatile int32u *)0xE0001014u) 08530 #define DWT_LSUCNT_ADDR (0xE0001014u) 08531 #define DWT_LSUCNT_RESET (0x00000000u) 08532 /* CPICNT field */ 08533 #define DWT_LSUCNT_CPICNT (0x000000FFu) 08534 #define DWT_LSUCNT_CPICNT_MASK (0x000000FFu) 08535 #define DWT_LSUCNT_CPICNT_BIT (0) 08536 #define DWT_LSUCNT_CPICNT_BITS (8) 08537 08538 #define DWT_FOLDCNT *((volatile int32u *)0xE0001018u) 08539 #define DWT_FOLDCNT_REG *((volatile int32u *)0xE0001018u) 08540 #define DWT_FOLDCNT_ADDR (0xE0001018u) 08541 #define DWT_FOLDCNT_RESET (0x00000000u) 08542 /* CPICNT field */ 08543 #define DWT_FOLDCNT_CPICNT (0x000000FFu) 08544 #define DWT_FOLDCNT_CPICNT_MASK (0x000000FFu) 08545 #define DWT_FOLDCNT_CPICNT_BIT (0) 08546 #define DWT_FOLDCNT_CPICNT_BITS (8) 08547 08548 #define DWT_PCSR *((volatile int32u *)0xE000101Cu) 08549 #define DWT_PCSR_REG *((volatile int32u *)0xE000101Cu) 08550 #define DWT_PCSR_ADDR (0xE000101Cu) 08551 #define DWT_PCSR_RESET (0x00000000u) 08552 /* EIASAMPLE field */ 08553 #define DWT_PCSR_EIASAMPLE (0xFFFFFFFFu) 08554 #define DWT_PCSR_EIASAMPLE_MASK (0xFFFFFFFFu) 08555 #define DWT_PCSR_EIASAMPLE_BIT (0) 08556 #define DWT_PCSR_EIASAMPLE_BITS (32) 08557 08558 #define DWT_COMP0 *((volatile int32u *)0xE0001020u) 08559 #define DWT_COMP0_REG *((volatile int32u *)0xE0001020u) 08560 #define DWT_COMP0_ADDR (0xE0001020u) 08561 #define DWT_COMP0_RESET (0x00000000u) 08562 /* COMP0 field */ 08563 #define DWT_COMP0_COMP0 (0xFFFFFFFFu) 08564 #define DWT_COMP0_COMP0_MASK (0xFFFFFFFFu) 08565 #define DWT_COMP0_COMP0_BIT (0) 08566 #define DWT_COMP0_COMP0_BITS (32) 08567 08568 #define DWT_MASK0 *((volatile int32u *)0xE0001024u) 08569 #define DWT_MASK0_REG *((volatile int32u *)0xE0001024u) 08570 #define DWT_MASK0_ADDR (0xE0001024u) 08571 #define DWT_MASK0_RESET (0x00000000u) 08572 /* MASK0 field */ 08573 #define DWT_MASK0_MASK0 (0x0000001Fu) 08574 #define DWT_MASK0_MASK0_MASK (0x0000001Fu) 08575 #define DWT_MASK0_MASK0_BIT (0) 08576 #define DWT_MASK0_MASK0_BITS (5) 08577 08578 #define DWT_FUNCTION0 *((volatile int32u *)0xE0001028u) 08579 #define DWT_FUNCTION0_REG *((volatile int32u *)0xE0001028u) 08580 #define DWT_FUNCTION0_ADDR (0xE0001028u) 08581 #define DWT_FUNCTION0_RESET (0x00000000u) 08582 /* MATCHED field */ 08583 #define DWT_FUNCTION0_MATCHED (0x01000000u) 08584 #define DWT_FUNCTION0_MATCHED_MASK (0x01000000u) 08585 #define DWT_FUNCTION0_MATCHED_BIT (24) 08586 #define DWT_FUNCTION0_MATCHED_BITS (1) 08587 /* CYCMATCH field */ 08588 #define DWT_FUNCTION0_CYCMATCH (0x00000080u) 08589 #define DWT_FUNCTION0_CYCMATCH_MASK (0x00000080u) 08590 #define DWT_FUNCTION0_CYCMATCH_BIT (7) 08591 #define DWT_FUNCTION0_CYCMATCH_BITS (1) 08592 /* EMITRANGE field */ 08593 #define DWT_FUNCTION0_EMITRANGE (0x00000020u) 08594 #define DWT_FUNCTION0_EMITRANGE_MASK (0x00000020u) 08595 #define DWT_FUNCTION0_EMITRANGE_BIT (5) 08596 #define DWT_FUNCTION0_EMITRANGE_BITS (1) 08597 /* FUNCTION field */ 08598 #define DWT_FUNCTION0_FUNCTION (0x0000000Fu) 08599 #define DWT_FUNCTION0_FUNCTION_MASK (0x0000000Fu) 08600 #define DWT_FUNCTION0_FUNCTION_BIT (0) 08601 #define DWT_FUNCTION0_FUNCTION_BITS (4) 08602 08603 #define DWT_COMP1 *((volatile int32u *)0xE0001030u) 08604 #define DWT_COMP1_REG *((volatile int32u *)0xE0001030u) 08605 #define DWT_COMP1_ADDR (0xE0001030u) 08606 #define DWT_COMP1_RESET (0x00000000u) 08607 /* COMP1 field */ 08608 #define DWT_COMP1_COMP1 (0xFFFFFFFFu) 08609 #define DWT_COMP1_COMP1_MASK (0xFFFFFFFFu) 08610 #define DWT_COMP1_COMP1_BIT (0) 08611 #define DWT_COMP1_COMP1_BITS (32) 08612 08613 #define DWT_MASK1 *((volatile int32u *)0xE0001034u) 08614 #define DWT_MASK1_REG *((volatile int32u *)0xE0001034u) 08615 #define DWT_MASK1_ADDR (0xE0001034u) 08616 #define DWT_MASK1_RESET (0x00000000u) 08617 /* MASK1 field */ 08618 #define DWT_MASK1_MASK1 (0x0000001Fu) 08619 #define DWT_MASK1_MASK1_MASK (0x0000001Fu) 08620 #define DWT_MASK1_MASK1_BIT (0) 08621 #define DWT_MASK1_MASK1_BITS (5) 08622 08623 #define DWT_FUNCTION1 *((volatile int32u *)0xE0001038u) 08624 #define DWT_FUNCTION1_REG *((volatile int32u *)0xE0001038u) 08625 #define DWT_FUNCTION1_ADDR (0xE0001038u) 08626 #define DWT_FUNCTION1_RESET (0x00000200u) 08627 /* MATCHED field */ 08628 #define DWT_FUNCTION1_MATCHED (0x01000000u) 08629 #define DWT_FUNCTION1_MATCHED_MASK (0x01000000u) 08630 #define DWT_FUNCTION1_MATCHED_BIT (24) 08631 #define DWT_FUNCTION1_MATCHED_BITS (1) 08632 /* DATAVADDR1 field */ 08633 #define DWT_FUNCTION1_DATAVADDR1 (0x000F0000u) 08634 #define DWT_FUNCTION1_DATAVADDR1_MASK (0x000F0000u) 08635 #define DWT_FUNCTION1_DATAVADDR1_BIT (16) 08636 #define DWT_FUNCTION1_DATAVADDR1_BITS (4) 08637 /* DATAVADDR0 field */ 08638 #define DWT_FUNCTION1_DATAVADDR0 (0x0000F000u) 08639 #define DWT_FUNCTION1_DATAVADDR0_MASK (0x0000F000u) 08640 #define DWT_FUNCTION1_DATAVADDR0_BIT (12) 08641 #define DWT_FUNCTION1_DATAVADDR0_BITS (4) 08642 /* DATAVSIZE field */ 08643 #define DWT_FUNCTION1_DATAVSIZE (0x00000C00u) 08644 #define DWT_FUNCTION1_DATAVSIZE_MASK (0x00000C00u) 08645 #define DWT_FUNCTION1_DATAVSIZE_BIT (10) 08646 #define DWT_FUNCTION1_DATAVSIZE_BITS (2) 08647 /* LNK1ENA field */ 08648 #define DWT_FUNCTION1_LNK1ENA (0x00000200u) 08649 #define DWT_FUNCTION1_LNK1ENA_MASK (0x00000200u) 08650 #define DWT_FUNCTION1_LNK1ENA_BIT (9) 08651 #define DWT_FUNCTION1_LNK1ENA_BITS (1) 08652 /* DATAVMATCH field */ 08653 #define DWT_FUNCTION1_DATAVMATCH (0x00000100u) 08654 #define DWT_FUNCTION1_DATAVMATCH_MASK (0x00000100u) 08655 #define DWT_FUNCTION1_DATAVMATCH_BIT (8) 08656 #define DWT_FUNCTION1_DATAVMATCH_BITS (1) 08657 /* EMITRANGE field */ 08658 #define DWT_FUNCTION1_EMITRANGE (0x00000020u) 08659 #define DWT_FUNCTION1_EMITRANGE_MASK (0x00000020u) 08660 #define DWT_FUNCTION1_EMITRANGE_BIT (5) 08661 #define DWT_FUNCTION1_EMITRANGE_BITS (1) 08662 /* FUNCTION field */ 08663 #define DWT_FUNCTION1_FUNCTION (0x0000000Fu) 08664 #define DWT_FUNCTION1_FUNCTION_MASK (0x0000000Fu) 08665 #define DWT_FUNCTION1_FUNCTION_BIT (0) 08666 #define DWT_FUNCTION1_FUNCTION_BITS (4) 08667 08668 #define DWT_COMP2 *((volatile int32u *)0xE0001040u) 08669 #define DWT_COMP2_REG *((volatile int32u *)0xE0001040u) 08670 #define DWT_COMP2_ADDR (0xE0001040u) 08671 #define DWT_COMP2_RESET (0x00000000u) 08672 /* COMP2 field */ 08673 #define DWT_COMP2_COMP2 (0xFFFFFFFFu) 08674 #define DWT_COMP2_COMP2_MASK (0xFFFFFFFFu) 08675 #define DWT_COMP2_COMP2_BIT (0) 08676 #define DWT_COMP2_COMP2_BITS (32) 08677 08678 #define DWT_MASK2 *((volatile int32u *)0xE0001044u) 08679 #define DWT_MASK2_REG *((volatile int32u *)0xE0001044u) 08680 #define DWT_MASK2_ADDR (0xE0001044u) 08681 #define DWT_MASK2_RESET (0x00000000u) 08682 /* MASK2 field */ 08683 #define DWT_MASK2_MASK2 (0x0000001Fu) 08684 #define DWT_MASK2_MASK2_MASK (0x0000001Fu) 08685 #define DWT_MASK2_MASK2_BIT (0) 08686 #define DWT_MASK2_MASK2_BITS (5) 08687 08688 #define DWT_FUNCTION2 *((volatile int32u *)0xE0001048u) 08689 #define DWT_FUNCTION2_REG *((volatile int32u *)0xE0001048u) 08690 #define DWT_FUNCTION2_ADDR (0xE0001048u) 08691 #define DWT_FUNCTION2_RESET (0x00000000u) 08692 /* MATCHED field */ 08693 #define DWT_FUNCTION2_MATCHED (0x01000000u) 08694 #define DWT_FUNCTION2_MATCHED_MASK (0x01000000u) 08695 #define DWT_FUNCTION2_MATCHED_BIT (24) 08696 #define DWT_FUNCTION2_MATCHED_BITS (1) 08697 /* EMITRANGE field */ 08698 #define DWT_FUNCTION2_EMITRANGE (0x00000020u) 08699 #define DWT_FUNCTION2_EMITRANGE_MASK (0x00000020u) 08700 #define DWT_FUNCTION2_EMITRANGE_BIT (5) 08701 #define DWT_FUNCTION2_EMITRANGE_BITS (1) 08702 /* FUNCTION field */ 08703 #define DWT_FUNCTION2_FUNCTION (0x0000000Fu) 08704 #define DWT_FUNCTION2_FUNCTION_MASK (0x0000000Fu) 08705 #define DWT_FUNCTION2_FUNCTION_BIT (0) 08706 #define DWT_FUNCTION2_FUNCTION_BITS (4) 08707 08708 #define DWT_COMP3 *((volatile int32u *)0xE0001050u) 08709 #define DWT_COMP3_REG *((volatile int32u *)0xE0001050u) 08710 #define DWT_COMP3_ADDR (0xE0001050u) 08711 #define DWT_COMP3_RESET (0x00000000u) 08712 /* COMP3 field */ 08713 #define DWT_COMP3_COMP3 (0xFFFFFFFFu) 08714 #define DWT_COMP3_COMP3_MASK (0xFFFFFFFFu) 08715 #define DWT_COMP3_COMP3_BIT (0) 08716 #define DWT_COMP3_COMP3_BITS (32) 08717 08718 #define DWT_MASK3 *((volatile int32u *)0xE0001054u) 08719 #define DWT_MASK3_REG *((volatile int32u *)0xE0001054u) 08720 #define DWT_MASK3_ADDR (0xE0001054u) 08721 #define DWT_MASK3_RESET (0x00000000u) 08722 /* MASK3 field */ 08723 #define DWT_MASK3_MASK3 (0x0000001Fu) 08724 #define DWT_MASK3_MASK3_MASK (0x0000001Fu) 08725 #define DWT_MASK3_MASK3_BIT (0) 08726 #define DWT_MASK3_MASK3_BITS (5) 08727 08728 #define DWT_FUNCTION3 *((volatile int32u *)0xE0001058u) 08729 #define DWT_FUNCTION3_REG *((volatile int32u *)0xE0001058u) 08730 #define DWT_FUNCTION3_ADDR (0xE0001058u) 08731 #define DWT_FUNCTION3_RESET (0x00000000u) 08732 /* MATCHED field */ 08733 #define DWT_FUNCTION3_MATCHED (0x01000000u) 08734 #define DWT_FUNCTION3_MATCHED_MASK (0x01000000u) 08735 #define DWT_FUNCTION3_MATCHED_BIT (24) 08736 #define DWT_FUNCTION3_MATCHED_BITS (1) 08737 /* EMITRANGE field */ 08738 #define DWT_FUNCTION3_EMITRANGE (0x00000020u) 08739 #define DWT_FUNCTION3_EMITRANGE_MASK (0x00000020u) 08740 #define DWT_FUNCTION3_EMITRANGE_BIT (5) 08741 #define DWT_FUNCTION3_EMITRANGE_BITS (1) 08742 /* FUNCTION field */ 08743 #define DWT_FUNCTION3_FUNCTION (0x0000000Fu) 08744 #define DWT_FUNCTION3_FUNCTION_MASK (0x0000000Fu) 08745 #define DWT_FUNCTION3_FUNCTION_BIT (0) 08746 #define DWT_FUNCTION3_FUNCTION_BITS (4) 08747 08748 #define DWT_PERIPHID4 *((volatile int32u *)0xE0001FD0u) 08749 #define DWT_PERIPHID4_REG *((volatile int32u *)0xE0001FD0u) 08750 #define DWT_PERIPHID4_ADDR (0xE0001FD0u) 08751 #define DWT_PERIPHID4_RESET (0x00000004u) 08752 /* PERIPHID field */ 08753 #define DWT_PERIPHID4_PERIPHID (0xFFFFFFFFu) 08754 #define DWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) 08755 #define DWT_PERIPHID4_PERIPHID_BIT (0) 08756 #define DWT_PERIPHID4_PERIPHID_BITS (32) 08757 08758 #define DWT_PERIPHID5 *((volatile int32u *)0xE0001FD4u) 08759 #define DWT_PERIPHID5_REG *((volatile int32u *)0xE0001FD4u) 08760 #define DWT_PERIPHID5_ADDR (0xE0001FD4u) 08761 #define DWT_PERIPHID5_RESET (0x00000000u) 08762 /* PERIPHID field */ 08763 #define DWT_PERIPHID5_PERIPHID (0xFFFFFFFFu) 08764 #define DWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) 08765 #define DWT_PERIPHID5_PERIPHID_BIT (0) 08766 #define DWT_PERIPHID5_PERIPHID_BITS (32) 08767 08768 #define DWT_PERIPHID6 *((volatile int32u *)0xE0001FD8u) 08769 #define DWT_PERIPHID6_REG *((volatile int32u *)0xE0001FD8u) 08770 #define DWT_PERIPHID6_ADDR (0xE0001FD8u) 08771 #define DWT_PERIPHID6_RESET (0x00000000u) 08772 /* PERIPHID field */ 08773 #define DWT_PERIPHID6_PERIPHID (0xFFFFFFFFu) 08774 #define DWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) 08775 #define DWT_PERIPHID6_PERIPHID_BIT (0) 08776 #define DWT_PERIPHID6_PERIPHID_BITS (32) 08777 08778 #define DWT_PERIPHID7 *((volatile int32u *)0xE0001FDCu) 08779 #define DWT_PERIPHID7_REG *((volatile int32u *)0xE0001FDCu) 08780 #define DWT_PERIPHID7_ADDR (0xE0001FDCu) 08781 #define DWT_PERIPHID7_RESET (0x00000000u) 08782 /* PERIPHID field */ 08783 #define DWT_PERIPHID7_PERIPHID (0xFFFFFFFFu) 08784 #define DWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) 08785 #define DWT_PERIPHID7_PERIPHID_BIT (0) 08786 #define DWT_PERIPHID7_PERIPHID_BITS (32) 08787 08788 #define DWT_PERIPHID0 *((volatile int32u *)0xE0001FE0u) 08789 #define DWT_PERIPHID0_REG *((volatile int32u *)0xE0001FE0u) 08790 #define DWT_PERIPHID0_ADDR (0xE0001FE0u) 08791 #define DWT_PERIPHID0_RESET (0x00000002u) 08792 /* PERIPHID field */ 08793 #define DWT_PERIPHID0_PERIPHID (0xFFFFFFFFu) 08794 #define DWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) 08795 #define DWT_PERIPHID0_PERIPHID_BIT (0) 08796 #define DWT_PERIPHID0_PERIPHID_BITS (32) 08797 08798 #define DWT_PERIPHID1 *((volatile int32u *)0xE0001FE4u) 08799 #define DWT_PERIPHID1_REG *((volatile int32u *)0xE0001FE4u) 08800 #define DWT_PERIPHID1_ADDR (0xE0001FE4u) 08801 #define DWT_PERIPHID1_RESET (0x00000000u) 08802 /* PERIPHID field */ 08803 #define DWT_PERIPHID1_PERIPHID (0xFFFFFFFFu) 08804 #define DWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) 08805 #define DWT_PERIPHID1_PERIPHID_BIT (0) 08806 #define DWT_PERIPHID1_PERIPHID_BITS (32) 08807 08808 #define DWT_PERIPHID2 *((volatile int32u *)0xE0001FE8u) 08809 #define DWT_PERIPHID2_REG *((volatile int32u *)0xE0001FE8u) 08810 #define DWT_PERIPHID2_ADDR (0xE0001FE8u) 08811 #define DWT_PERIPHID2_RESET (0x0000001Bu) 08812 /* PERIPHID field */ 08813 #define DWT_PERIPHID2_PERIPHID (0xFFFFFFFFu) 08814 #define DWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) 08815 #define DWT_PERIPHID2_PERIPHID_BIT (0) 08816 #define DWT_PERIPHID2_PERIPHID_BITS (32) 08817 08818 #define DWT_PERIPHID3 *((volatile int32u *)0xE0001FECu) 08819 #define DWT_PERIPHID3_REG *((volatile int32u *)0xE0001FECu) 08820 #define DWT_PERIPHID3_ADDR (0xE0001FECu) 08821 #define DWT_PERIPHID3_RESET (0x00000000u) 08822 /* PERIPHID field */ 08823 #define DWT_PERIPHID3_PERIPHID (0xFFFFFFFFu) 08824 #define DWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) 08825 #define DWT_PERIPHID3_PERIPHID_BIT (0) 08826 #define DWT_PERIPHID3_PERIPHID_BITS (32) 08827 08828 #define DWT_CELLID0 *((volatile int32u *)0xE0001FF0u) 08829 #define DWT_CELLID0_REG *((volatile int32u *)0xE0001FF0u) 08830 #define DWT_CELLID0_ADDR (0xE0001FF0u) 08831 #define DWT_CELLID0_RESET (0x0000000Du) 08832 /* CELLID field */ 08833 #define DWT_CELLID0_CELLID (0xFFFFFFFFu) 08834 #define DWT_CELLID0_CELLID_MASK (0xFFFFFFFFu) 08835 #define DWT_CELLID0_CELLID_BIT (0) 08836 #define DWT_CELLID0_CELLID_BITS (32) 08837 08838 #define DWT_CELLID1 *((volatile int32u *)0xE0001FF4u) 08839 #define DWT_CELLID1_REG *((volatile int32u *)0xE0001FF4u) 08840 #define DWT_CELLID1_ADDR (0xE0001FF4u) 08841 #define DWT_CELLID1_RESET (0x000000E0u) 08842 /* CELLID field */ 08843 #define DWT_CELLID1_CELLID (0xFFFFFFFFu) 08844 #define DWT_CELLID1_CELLID_MASK (0xFFFFFFFFu) 08845 #define DWT_CELLID1_CELLID_BIT (0) 08846 #define DWT_CELLID1_CELLID_BITS (32) 08847 08848 #define DWT_CELLID2 *((volatile int32u *)0xE0001FF8u) 08849 #define DWT_CELLID2_REG *((volatile int32u *)0xE0001FF8u) 08850 #define DWT_CELLID2_ADDR (0xE0001FF8u) 08851 #define DWT_CELLID2_RESET (0x00000005u) 08852 /* CELLID field */ 08853 #define DWT_CELLID2_CELLID (0xFFFFFFFFu) 08854 #define DWT_CELLID2_CELLID_MASK (0xFFFFFFFFu) 08855 #define DWT_CELLID2_CELLID_BIT (0) 08856 #define DWT_CELLID2_CELLID_BITS (32) 08857 08858 #define DWT_CELLID3 *((volatile int32u *)0xE0001FFCu) 08859 #define DWT_CELLID3_REG *((volatile int32u *)0xE0001FFCu) 08860 #define DWT_CELLID3_ADDR (0xE0001FFCu) 08861 #define DWT_CELLID3_RESET (0x000000B1u) 08862 /* CELLID field */ 08863 #define DWT_CELLID3_CELLID (0xFFFFFFFFu) 08864 #define DWT_CELLID3_CELLID_MASK (0xFFFFFFFFu) 08865 #define DWT_CELLID3_CELLID_BIT (0) 08866 #define DWT_CELLID3_CELLID_BITS (32) 08867 08868 /* FPB block */ 08869 #define DATA_FPB_BASE (0xE0002000u) 08870 #define DATA_FPB_END (0xE0002FFFu) 08871 #define DATA_FPB_SIZE (DATA_FPB_END - DATA_FPB_BASE + 1) 08872 08873 #define FPB_CTRL *((volatile int32u *)0xE0002000u) 08874 #define FPB_CTRL_REG *((volatile int32u *)0xE0002000u) 08875 #define FPB_CTRL_ADDR (0xE0002000u) 08876 #define FPB_CTRL_RESET (0x00000000u) 08877 /* NUM_LIT field */ 08878 #define FPB_CTRL_NUM_LIT (0x00000F00u) 08879 #define FPB_CTRL_NUM_LIT_MASK (0x00000F00u) 08880 #define FPB_CTRL_NUM_LIT_BIT (8) 08881 #define FPB_CTRL_NUM_LIT_BITS (4) 08882 /* NUM_CODE field */ 08883 #define FPB_CTRL_NUM_CODE (0x000000F0u) 08884 #define FPB_CTRL_NUM_CODE_MASK (0x000000F0u) 08885 #define FPB_CTRL_NUM_CODE_BIT (4) 08886 #define FPB_CTRL_NUM_CODE_BITS (4) 08887 /* KEY field */ 08888 #define FPB_CTRL_KEY (0x00000002u) 08889 #define FPB_CTRL_KEY_MASK (0x00000002u) 08890 #define FPB_CTRL_KEY_BIT (1) 08891 #define FPB_CTRL_KEY_BITS (1) 08892 /* enable field */ 08893 #define FPB_CTRL_enable (0x00000001u) 08894 #define FPB_CTRL_enable_MASK (0x00000001u) 08895 #define FPB_CTRL_enable_BIT (0) 08896 #define FPB_CTRL_enable_BITS (1) 08897 08898 #define FPB_REMAP *((volatile int32u *)0xE0002004u) 08899 #define FPB_REMAP_REG *((volatile int32u *)0xE0002004u) 08900 #define FPB_REMAP_ADDR (0xE0002004u) 08901 #define FPB_REMAP_RESET (0x20000000u) 08902 /* REMAP field */ 08903 #define FPB_REMAP_REMAP (0x1FFFFFE0u) 08904 #define FPB_REMAP_REMAP_MASK (0x1FFFFFE0u) 08905 #define FPB_REMAP_REMAP_BIT (5) 08906 #define FPB_REMAP_REMAP_BITS (24) 08907 08908 #define FPB_COMP0 *((volatile int32u *)0xE0002008u) 08909 #define FPB_COMP0_REG *((volatile int32u *)0xE0002008u) 08910 #define FPB_COMP0_ADDR (0xE0002008u) 08911 #define FPB_COMP0_RESET (0x00000000u) 08912 /* REPLACE field */ 08913 #define FPB_COMP0_REPLACE (0xC0000000u) 08914 #define FPB_COMP0_REPLACE_MASK (0xC0000000u) 08915 #define FPB_COMP0_REPLACE_BIT (30) 08916 #define FPB_COMP0_REPLACE_BITS (2) 08917 /* COMP field */ 08918 #define FPB_COMP0_COMP (0x1FFFFFFCu) 08919 #define FPB_COMP0_COMP_MASK (0x1FFFFFFCu) 08920 #define FPB_COMP0_COMP_BIT (2) 08921 #define FPB_COMP0_COMP_BITS (27) 08922 /* enable field */ 08923 #define FPB_COMP0_enable (0x00000001u) 08924 #define FPB_COMP0_enable_MASK (0x00000001u) 08925 #define FPB_COMP0_enable_BIT (0) 08926 #define FPB_COMP0_enable_BITS (1) 08927 08928 #define FPB_COMP1 *((volatile int32u *)0xE000200Cu) 08929 #define FPB_COMP1_REG *((volatile int32u *)0xE000200Cu) 08930 #define FPB_COMP1_ADDR (0xE000200Cu) 08931 #define FPB_COMP1_RESET (0x00000000u) 08932 /* REPLACE field */ 08933 #define FPB_COMP1_REPLACE (0xC0000000u) 08934 #define FPB_COMP1_REPLACE_MASK (0xC0000000u) 08935 #define FPB_COMP1_REPLACE_BIT (30) 08936 #define FPB_COMP1_REPLACE_BITS (2) 08937 /* COMP field */ 08938 #define FPB_COMP1_COMP (0x1FFFFFFCu) 08939 #define FPB_COMP1_COMP_MASK (0x1FFFFFFCu) 08940 #define FPB_COMP1_COMP_BIT (2) 08941 #define FPB_COMP1_COMP_BITS (27) 08942 /* enable field */ 08943 #define FPB_COMP1_enable (0x00000001u) 08944 #define FPB_COMP1_enable_MASK (0x00000001u) 08945 #define FPB_COMP1_enable_BIT (0) 08946 #define FPB_COMP1_enable_BITS (1) 08947 08948 #define FPB_COMP2 *((volatile int32u *)0xE0002010u) 08949 #define FPB_COMP2_REG *((volatile int32u *)0xE0002010u) 08950 #define FPB_COMP2_ADDR (0xE0002010u) 08951 #define FPB_COMP2_RESET (0x00000000u) 08952 /* REPLACE field */ 08953 #define FPB_COMP2_REPLACE (0xC0000000u) 08954 #define FPB_COMP2_REPLACE_MASK (0xC0000000u) 08955 #define FPB_COMP2_REPLACE_BIT (30) 08956 #define FPB_COMP2_REPLACE_BITS (2) 08957 /* COMP field */ 08958 #define FPB_COMP2_COMP (0x1FFFFFFCu) 08959 #define FPB_COMP2_COMP_MASK (0x1FFFFFFCu) 08960 #define FPB_COMP2_COMP_BIT (2) 08961 #define FPB_COMP2_COMP_BITS (27) 08962 /* enable field */ 08963 #define FPB_COMP2_enable (0x00000001u) 08964 #define FPB_COMP2_enable_MASK (0x00000001u) 08965 #define FPB_COMP2_enable_BIT (0) 08966 #define FPB_COMP2_enable_BITS (1) 08967 08968 #define FPB_COMP3 *((volatile int32u *)0xE0002014u) 08969 #define FPB_COMP3_REG *((volatile int32u *)0xE0002014u) 08970 #define FPB_COMP3_ADDR (0xE0002014u) 08971 #define FPB_COMP3_RESET (0x00000000u) 08972 /* REPLACE field */ 08973 #define FPB_COMP3_REPLACE (0xC0000000u) 08974 #define FPB_COMP3_REPLACE_MASK (0xC0000000u) 08975 #define FPB_COMP3_REPLACE_BIT (30) 08976 #define FPB_COMP3_REPLACE_BITS (2) 08977 /* COMP field */ 08978 #define FPB_COMP3_COMP (0x1FFFFFFCu) 08979 #define FPB_COMP3_COMP_MASK (0x1FFFFFFCu) 08980 #define FPB_COMP3_COMP_BIT (2) 08981 #define FPB_COMP3_COMP_BITS (27) 08982 /* enable field */ 08983 #define FPB_COMP3_enable (0x00000001u) 08984 #define FPB_COMP3_enable_MASK (0x00000001u) 08985 #define FPB_COMP3_enable_BIT (0) 08986 #define FPB_COMP3_enable_BITS (1) 08987 08988 #define FPB_COMP4 *((volatile int32u *)0xE0002018u) 08989 #define FPB_COMP4_REG *((volatile int32u *)0xE0002018u) 08990 #define FPB_COMP4_ADDR (0xE0002018u) 08991 #define FPB_COMP4_RESET (0x00000000u) 08992 /* REPLACE field */ 08993 #define FPB_COMP4_REPLACE (0xC0000000u) 08994 #define FPB_COMP4_REPLACE_MASK (0xC0000000u) 08995 #define FPB_COMP4_REPLACE_BIT (30) 08996 #define FPB_COMP4_REPLACE_BITS (2) 08997 /* COMP field */ 08998 #define FPB_COMP4_COMP (0x1FFFFFFCu) 08999 #define FPB_COMP4_COMP_MASK (0x1FFFFFFCu) 09000 #define FPB_COMP4_COMP_BIT (2) 09001 #define FPB_COMP4_COMP_BITS (27) 09002 /* enable field */ 09003 #define FPB_COMP4_enable (0x00000001u) 09004 #define FPB_COMP4_enable_MASK (0x00000001u) 09005 #define FPB_COMP4_enable_BIT (0) 09006 #define FPB_COMP4_enable_BITS (1) 09007 09008 #define FPB_COMP5 *((volatile int32u *)0xE000201Cu) 09009 #define FPB_COMP5_REG *((volatile int32u *)0xE000201Cu) 09010 #define FPB_COMP5_ADDR (0xE000201Cu) 09011 #define FPB_COMP5_RESET (0x00000000u) 09012 /* REPLACE field */ 09013 #define FPB_COMP5_REPLACE (0xC0000000u) 09014 #define FPB_COMP5_REPLACE_MASK (0xC0000000u) 09015 #define FPB_COMP5_REPLACE_BIT (30) 09016 #define FPB_COMP5_REPLACE_BITS (2) 09017 /* COMP field */ 09018 #define FPB_COMP5_COMP (0x1FFFFFFCu) 09019 #define FPB_COMP5_COMP_MASK (0x1FFFFFFCu) 09020 #define FPB_COMP5_COMP_BIT (2) 09021 #define FPB_COMP5_COMP_BITS (27) 09022 /* enable field */ 09023 #define FPB_COMP5_enable (0x00000001u) 09024 #define FPB_COMP5_enable_MASK (0x00000001u) 09025 #define FPB_COMP5_enable_BIT (0) 09026 #define FPB_COMP5_enable_BITS (1) 09027 09028 #define FPB_COMP6 *((volatile int32u *)0xE0002020u) 09029 #define FPB_COMP6_REG *((volatile int32u *)0xE0002020u) 09030 #define FPB_COMP6_ADDR (0xE0002020u) 09031 #define FPB_COMP6_RESET (0x00000000u) 09032 /* REPLACE field */ 09033 #define FPB_COMP6_REPLACE (0xC0000000u) 09034 #define FPB_COMP6_REPLACE_MASK (0xC0000000u) 09035 #define FPB_COMP6_REPLACE_BIT (30) 09036 #define FPB_COMP6_REPLACE_BITS (2) 09037 /* COMP field */ 09038 #define FPB_COMP6_COMP (0x1FFFFFFCu) 09039 #define FPB_COMP6_COMP_MASK (0x1FFFFFFCu) 09040 #define FPB_COMP6_COMP_BIT (2) 09041 #define FPB_COMP6_COMP_BITS (27) 09042 /* enable field */ 09043 #define FPB_COMP6_enable (0x00000001u) 09044 #define FPB_COMP6_enable_MASK (0x00000001u) 09045 #define FPB_COMP6_enable_BIT (0) 09046 #define FPB_COMP6_enable_BITS (1) 09047 09048 #define FPB_COMP7 *((volatile int32u *)0xE0002024u) 09049 #define FPB_COMP7_REG *((volatile int32u *)0xE0002024u) 09050 #define FPB_COMP7_ADDR (0xE0002024u) 09051 #define FPB_COMP7_RESET (0x00000000u) 09052 /* REPLACE field */ 09053 #define FPB_COMP7_REPLACE (0xC0000000u) 09054 #define FPB_COMP7_REPLACE_MASK (0xC0000000u) 09055 #define FPB_COMP7_REPLACE_BIT (30) 09056 #define FPB_COMP7_REPLACE_BITS (2) 09057 /* COMP field */ 09058 #define FPB_COMP7_COMP (0x1FFFFFFCu) 09059 #define FPB_COMP7_COMP_MASK (0x1FFFFFFCu) 09060 #define FPB_COMP7_COMP_BIT (2) 09061 #define FPB_COMP7_COMP_BITS (27) 09062 /* enable field */ 09063 #define FPB_COMP7_enable (0x00000001u) 09064 #define FPB_COMP7_enable_MASK (0x00000001u) 09065 #define FPB_COMP7_enable_BIT (0) 09066 #define FPB_COMP7_enable_BITS (1) 09067 09068 #define FPB_PERIPHID4 *((volatile int32u *)0xE0002FD0u) 09069 #define FPB_PERIPHID4_REG *((volatile int32u *)0xE0002FD0u) 09070 #define FPB_PERIPHID4_ADDR (0xE0002FD0u) 09071 #define FPB_PERIPHID4_RESET (0x00000004u) 09072 /* PERIPHID field */ 09073 #define FPB_PERIPHID4_PERIPHID (0xFFFFFFFFu) 09074 #define FPB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) 09075 #define FPB_PERIPHID4_PERIPHID_BIT (0) 09076 #define FPB_PERIPHID4_PERIPHID_BITS (32) 09077 09078 #define FPB_PERIPHID5 *((volatile int32u *)0xE0002FD4u) 09079 #define FPB_PERIPHID5_REG *((volatile int32u *)0xE0002FD4u) 09080 #define FPB_PERIPHID5_ADDR (0xE0002FD4u) 09081 #define FPB_PERIPHID5_RESET (0x00000000u) 09082 /* PERIPHID field */ 09083 #define FPB_PERIPHID5_PERIPHID (0xFFFFFFFFu) 09084 #define FPB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) 09085 #define FPB_PERIPHID5_PERIPHID_BIT (0) 09086 #define FPB_PERIPHID5_PERIPHID_BITS (32) 09087 09088 #define FPB_PERIPHID6 *((volatile int32u *)0xE0002FD8u) 09089 #define FPB_PERIPHID6_REG *((volatile int32u *)0xE0002FD8u) 09090 #define FPB_PERIPHID6_ADDR (0xE0002FD8u) 09091 #define FPB_PERIPHID6_RESET (0x00000000u) 09092 /* PERIPHID field */ 09093 #define FPB_PERIPHID6_PERIPHID (0xFFFFFFFFu) 09094 #define FPB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) 09095 #define FPB_PERIPHID6_PERIPHID_BIT (0) 09096 #define FPB_PERIPHID6_PERIPHID_BITS (32) 09097 09098 #define FPB_PERIPHID7 *((volatile int32u *)0xE0002FDCu) 09099 #define FPB_PERIPHID7_REG *((volatile int32u *)0xE0002FDCu) 09100 #define FPB_PERIPHID7_ADDR (0xE0002FDCu) 09101 #define FPB_PERIPHID7_RESET (0x00000000u) 09102 /* PERIPHID field */ 09103 #define FPB_PERIPHID7_PERIPHID (0xFFFFFFFFu) 09104 #define FPB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) 09105 #define FPB_PERIPHID7_PERIPHID_BIT (0) 09106 #define FPB_PERIPHID7_PERIPHID_BITS (32) 09107 09108 #define FPB_PERIPHID0 *((volatile int32u *)0xE0002FE0u) 09109 #define FPB_PERIPHID0_REG *((volatile int32u *)0xE0002FE0u) 09110 #define FPB_PERIPHID0_ADDR (0xE0002FE0u) 09111 #define FPB_PERIPHID0_RESET (0x00000003u) 09112 /* PERIPHID field */ 09113 #define FPB_PERIPHID0_PERIPHID (0xFFFFFFFFu) 09114 #define FPB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) 09115 #define FPB_PERIPHID0_PERIPHID_BIT (0) 09116 #define FPB_PERIPHID0_PERIPHID_BITS (32) 09117 09118 #define FPB_PERIPHID1 *((volatile int32u *)0xE0002FE4u) 09119 #define FPB_PERIPHID1_REG *((volatile int32u *)0xE0002FE4u) 09120 #define FPB_PERIPHID1_ADDR (0xE0002FE4u) 09121 #define FPB_PERIPHID1_RESET (0x000000B0u) 09122 /* PERIPHID field */ 09123 #define FPB_PERIPHID1_PERIPHID (0xFFFFFFFFu) 09124 #define FPB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) 09125 #define FPB_PERIPHID1_PERIPHID_BIT (0) 09126 #define FPB_PERIPHID1_PERIPHID_BITS (32) 09127 09128 #define FPB_PERIPHID2 *((volatile int32u *)0xE0002FE8u) 09129 #define FPB_PERIPHID2_REG *((volatile int32u *)0xE0002FE8u) 09130 #define FPB_PERIPHID2_ADDR (0xE0002FE8u) 09131 #define FPB_PERIPHID2_RESET (0x0000000Bu) 09132 /* PERIPHID field */ 09133 #define FPB_PERIPHID2_PERIPHID (0xFFFFFFFFu) 09134 #define FPB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) 09135 #define FPB_PERIPHID2_PERIPHID_BIT (0) 09136 #define FPB_PERIPHID2_PERIPHID_BITS (32) 09137 09138 #define FPB_PERIPHID3 *((volatile int32u *)0xE0002FECu) 09139 #define FPB_PERIPHID3_REG *((volatile int32u *)0xE0002FECu) 09140 #define FPB_PERIPHID3_ADDR (0xE0002FECu) 09141 #define FPB_PERIPHID3_RESET (0x00000000u) 09142 /* PERIPHID field */ 09143 #define FPB_PERIPHID3_PERIPHID (0xFFFFFFFFu) 09144 #define FPB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) 09145 #define FPB_PERIPHID3_PERIPHID_BIT (0) 09146 #define FPB_PERIPHID3_PERIPHID_BITS (32) 09147 09148 #define FPB_CELLID0 *((volatile int32u *)0xE0002FF0u) 09149 #define FPB_CELLID0_REG *((volatile int32u *)0xE0002FF0u) 09150 #define FPB_CELLID0_ADDR (0xE0002FF0u) 09151 #define FPB_CELLID0_RESET (0x0000000Du) 09152 /* CELLID field */ 09153 #define FPB_CELLID0_CELLID (0xFFFFFFFFu) 09154 #define FPB_CELLID0_CELLID_MASK (0xFFFFFFFFu) 09155 #define FPB_CELLID0_CELLID_BIT (0) 09156 #define FPB_CELLID0_CELLID_BITS (32) 09157 09158 #define FPB_CELLID1 *((volatile int32u *)0xE0002FF4u) 09159 #define FPB_CELLID1_REG *((volatile int32u *)0xE0002FF4u) 09160 #define FPB_CELLID1_ADDR (0xE0002FF4u) 09161 #define FPB_CELLID1_RESET (0x000000E0u) 09162 /* CELLID field */ 09163 #define FPB_CELLID1_CELLID (0xFFFFFFFFu) 09164 #define FPB_CELLID1_CELLID_MASK (0xFFFFFFFFu) 09165 #define FPB_CELLID1_CELLID_BIT (0) 09166 #define FPB_CELLID1_CELLID_BITS (32) 09167 09168 #define FPB_CELLID2 *((volatile int32u *)0xE0002FF8u) 09169 #define FPB_CELLID2_REG *((volatile int32u *)0xE0002FF8u) 09170 #define FPB_CELLID2_ADDR (0xE0002FF8u) 09171 #define FPB_CELLID2_RESET (0x00000005u) 09172 /* CELLID field */ 09173 #define FPB_CELLID2_CELLID (0xFFFFFFFFu) 09174 #define FPB_CELLID2_CELLID_MASK (0xFFFFFFFFu) 09175 #define FPB_CELLID2_CELLID_BIT (0) 09176 #define FPB_CELLID2_CELLID_BITS (32) 09177 09178 #define FPB_CELLID3 *((volatile int32u *)0xE0002FFCu) 09179 #define FPB_CELLID3_REG *((volatile int32u *)0xE0002FFCu) 09180 #define FPB_CELLID3_ADDR (0xE0002FFCu) 09181 #define FPB_CELLID3_RESET (0x000000B1u) 09182 /* CELLID field */ 09183 #define FPB_CELLID3_CELLID (0xFFFFFFFFu) 09184 #define FPB_CELLID3_CELLID_MASK (0xFFFFFFFFu) 09185 #define FPB_CELLID3_CELLID_BIT (0) 09186 #define FPB_CELLID3_CELLID_BITS (32) 09187 09188 /* NVIC block */ 09189 #define BLOCK_NVIC_BASE (0xE000E000u) 09190 #define BLOCK_NVIC_END (0xE000EFFFu) 09191 #define BLOCK_NVIC_SIZE (BLOCK_NVIC_END - BLOCK_NVIC_BASE + 1) 09192 09193 #define NVIC_MCR *((volatile int32u *)0xE000E000u) 09194 #define NVIC_MCR_REG *((volatile int32u *)0xE000E000u) 09195 #define NVIC_MCR_ADDR (0xE000E000u) 09196 #define NVIC_MCR_RESET (0x00000000u) 09197 09198 #define NVIC_ICTR *((volatile int32u *)0xE000E004u) 09199 #define NVIC_ICTR_REG *((volatile int32u *)0xE000E004u) 09200 #define NVIC_ICTR_ADDR (0xE000E004u) 09201 #define NVIC_ICTR_RESET (0x00000000u) 09202 /* INTLINESNUM field */ 09203 #define NVIC_ICTR_INTLINESNUM (0x0000001Fu) 09204 #define NVIC_ICTR_INTLINESNUM_MASK (0x0000001Fu) 09205 #define NVIC_ICTR_INTLINESNUM_BIT (0) 09206 #define NVIC_ICTR_INTLINESNUM_BITS (5) 09207 09208 #define ST_CSR *((volatile int32u *)0xE000E010u) 09209 #define ST_CSR_REG *((volatile int32u *)0xE000E010u) 09210 #define ST_CSR_ADDR (0xE000E010u) 09211 #define ST_CSR_RESET (0x00000000u) 09212 /* COUNTFLAG field */ 09213 #define ST_CSR_COUNTFLAG (0x00010000u) 09214 #define ST_CSR_COUNTFLAG_MASK (0x00010000u) 09215 #define ST_CSR_COUNTFLAG_BIT (16) 09216 #define ST_CSR_COUNTFLAG_BITS (1) 09217 /* CLKSOURCE field */ 09218 #define ST_CSR_CLKSOURCE (0x00000004u) 09219 #define ST_CSR_CLKSOURCE_MASK (0x00000004u) 09220 #define ST_CSR_CLKSOURCE_BIT (2) 09221 #define ST_CSR_CLKSOURCE_BITS (1) 09222 /* TICKINT field */ 09223 #define ST_CSR_TICKINT (0x00000002u) 09224 #define ST_CSR_TICKINT_MASK (0x00000002u) 09225 #define ST_CSR_TICKINT_BIT (1) 09226 #define ST_CSR_TICKINT_BITS (1) 09227 /* ENABLE field */ 09228 #define ST_CSR_ENABLE (0x00000001u) 09229 #define ST_CSR_ENABLE_MASK (0x00000001u) 09230 #define ST_CSR_ENABLE_BIT (0) 09231 #define ST_CSR_ENABLE_BITS (1) 09232 09233 #define ST_RVR *((volatile int32u *)0xE000E014u) 09234 #define ST_RVR_REG *((volatile int32u *)0xE000E014u) 09235 #define ST_RVR_ADDR (0xE000E014u) 09236 #define ST_RVR_RESET (0x00000000u) 09237 /* RELOAD field */ 09238 #define ST_RVR_RELOAD (0x00FFFFFFu) 09239 #define ST_RVR_RELOAD_MASK (0x00FFFFFFu) 09240 #define ST_RVR_RELOAD_BIT (0) 09241 #define ST_RVR_RELOAD_BITS (24) 09242 09243 #define ST_CVR *((volatile int32u *)0xE000E018u) 09244 #define ST_CVR_REG *((volatile int32u *)0xE000E018u) 09245 #define ST_CVR_ADDR (0xE000E018u) 09246 #define ST_CVR_RESET (0x00000000u) 09247 /* CURRENT field */ 09248 #define ST_CVR_CURRENT (0xFFFFFFFFu) 09249 #define ST_CVR_CURRENT_MASK (0xFFFFFFFFu) 09250 #define ST_CVR_CURRENT_BIT (0) 09251 #define ST_CVR_CURRENT_BITS (32) 09252 09253 #define ST_CALVR *((volatile int32u *)0xE000E01Cu) 09254 #define ST_CALVR_REG *((volatile int32u *)0xE000E01Cu) 09255 #define ST_CALVR_ADDR (0xE000E01Cu) 09256 #define ST_CALVR_RESET (0x00000000u) 09257 /* NOREF field */ 09258 #define ST_CALVR_NOREF (0x80000000u) 09259 #define ST_CALVR_NOREF_MASK (0x80000000u) 09260 #define ST_CALVR_NOREF_BIT (31) 09261 #define ST_CALVR_NOREF_BITS (1) 09262 /* SKEW field */ 09263 #define ST_CALVR_SKEW (0x40000000u) 09264 #define ST_CALVR_SKEW_MASK (0x40000000u) 09265 #define ST_CALVR_SKEW_BIT (30) 09266 #define ST_CALVR_SKEW_BITS (1) 09267 /* TENMS field */ 09268 #define ST_CALVR_TENMS (0x00FFFFFFu) 09269 #define ST_CALVR_TENMS_MASK (0x00FFFFFFu) 09270 #define ST_CALVR_TENMS_BIT (0) 09271 #define ST_CALVR_TENMS_BITS (24) 09272 09273 #define INT_CFGSET *((volatile int32u *)0xE000E100u) 09274 #define INT_CFGSET_REG *((volatile int32u *)0xE000E100u) 09275 #define INT_CFGSET_ADDR (0xE000E100u) 09276 #define INT_CFGSET_RESET (0x00000000u) 09277 /* INT_DEBUG field */ 09278 #define INT_DEBUG (0x00010000u) 09279 #define INT_DEBUG_MASK (0x00010000u) 09280 #define INT_DEBUG_BIT (16) 09281 #define INT_DEBUG_BITS (1) 09282 /* INT_IRQD field */ 09283 #define INT_IRQD (0x00008000u) 09284 #define INT_IRQD_MASK (0x00008000u) 09285 #define INT_IRQD_BIT (15) 09286 #define INT_IRQD_BITS (1) 09287 /* INT_IRQC field */ 09288 #define INT_IRQC (0x00004000u) 09289 #define INT_IRQC_MASK (0x00004000u) 09290 #define INT_IRQC_BIT (14) 09291 #define INT_IRQC_BITS (1) 09292 /* INT_IRQB field */ 09293 #define INT_IRQB (0x00002000u) 09294 #define INT_IRQB_MASK (0x00002000u) 09295 #define INT_IRQB_BIT (13) 09296 #define INT_IRQB_BITS (1) 09297 /* INT_IRQA field */ 09298 #define INT_IRQA (0x00001000u) 09299 #define INT_IRQA_MASK (0x00001000u) 09300 #define INT_IRQA_BIT (12) 09301 #define INT_IRQA_BITS (1) 09302 /* INT_ADC field */ 09303 #define INT_ADC (0x00000800u) 09304 #define INT_ADC_MASK (0x00000800u) 09305 #define INT_ADC_BIT (11) 09306 #define INT_ADC_BITS (1) 09307 /* INT_MACRX field */ 09308 #define INT_MACRX (0x00000400u) 09309 #define INT_MACRX_MASK (0x00000400u) 09310 #define INT_MACRX_BIT (10) 09311 #define INT_MACRX_BITS (1) 09312 /* INT_MACTX field */ 09313 #define INT_MACTX (0x00000200u) 09314 #define INT_MACTX_MASK (0x00000200u) 09315 #define INT_MACTX_BIT (9) 09316 #define INT_MACTX_BITS (1) 09317 /* INT_MACTMR field */ 09318 #define INT_MACTMR (0x00000100u) 09319 #define INT_MACTMR_MASK (0x00000100u) 09320 #define INT_MACTMR_BIT (8) 09321 #define INT_MACTMR_BITS (1) 09322 /* INT_SEC field */ 09323 #define INT_SEC (0x00000080u) 09324 #define INT_SEC_MASK (0x00000080u) 09325 #define INT_SEC_BIT (7) 09326 #define INT_SEC_BITS (1) 09327 /* INT_SC2 field */ 09328 #define INT_SC2 (0x00000040u) 09329 #define INT_SC2_MASK (0x00000040u) 09330 #define INT_SC2_BIT (6) 09331 #define INT_SC2_BITS (1) 09332 /* INT_SC1 field */ 09333 #define INT_SC1 (0x00000020u) 09334 #define INT_SC1_MASK (0x00000020u) 09335 #define INT_SC1_BIT (5) 09336 #define INT_SC1_BITS (1) 09337 /* INT_SLEEPTMR field */ 09338 #define INT_SLEEPTMR (0x00000010u) 09339 #define INT_SLEEPTMR_MASK (0x00000010u) 09340 #define INT_SLEEPTMR_BIT (4) 09341 #define INT_SLEEPTMR_BITS (1) 09342 /* INT_BB field */ 09343 #define INT_BB (0x00000008u) 09344 #define INT_BB_MASK (0x00000008u) 09345 #define INT_BB_BIT (3) 09346 #define INT_BB_BITS (1) 09347 /* INT_MGMT field */ 09348 #define INT_MGMT (0x00000004u) 09349 #define INT_MGMT_MASK (0x00000004u) 09350 #define INT_MGMT_BIT (2) 09351 #define INT_MGMT_BITS (1) 09352 /* INT_TIM2 field */ 09353 #define INT_TIM2 (0x00000002u) 09354 #define INT_TIM2_MASK (0x00000002u) 09355 #define INT_TIM2_BIT (1) 09356 #define INT_TIM2_BITS (1) 09357 /* INT_TIM1 field */ 09358 #define INT_TIM1 (0x00000001u) 09359 #define INT_TIM1_MASK (0x00000001u) 09360 #define INT_TIM1_BIT (0) 09361 #define INT_TIM1_BITS (1) 09362 09363 #define INT_CFGCLR *((volatile int32u *)0xE000E180u) 09364 #define INT_CFGCLR_REG *((volatile int32u *)0xE000E180u) 09365 #define INT_CFGCLR_ADDR (0xE000E180u) 09366 #define INT_CFGCLR_RESET (0x00000000u) 09367 /* INT_DEBUG field */ 09368 #define INT_DEBUG (0x00010000u) 09369 #define INT_DEBUG_MASK (0x00010000u) 09370 #define INT_DEBUG_BIT (16) 09371 #define INT_DEBUG_BITS (1) 09372 /* INT_IRQD field */ 09373 #define INT_IRQD (0x00008000u) 09374 #define INT_IRQD_MASK (0x00008000u) 09375 #define INT_IRQD_BIT (15) 09376 #define INT_IRQD_BITS (1) 09377 /* INT_IRQC field */ 09378 #define INT_IRQC (0x00004000u) 09379 #define INT_IRQC_MASK (0x00004000u) 09380 #define INT_IRQC_BIT (14) 09381 #define INT_IRQC_BITS (1) 09382 /* INT_IRQB field */ 09383 #define INT_IRQB (0x00002000u) 09384 #define INT_IRQB_MASK (0x00002000u) 09385 #define INT_IRQB_BIT (13) 09386 #define INT_IRQB_BITS (1) 09387 /* INT_IRQA field */ 09388 #define INT_IRQA (0x00001000u) 09389 #define INT_IRQA_MASK (0x00001000u) 09390 #define INT_IRQA_BIT (12) 09391 #define INT_IRQA_BITS (1) 09392 /* INT_ADC field */ 09393 #define INT_ADC (0x00000800u) 09394 #define INT_ADC_MASK (0x00000800u) 09395 #define INT_ADC_BIT (11) 09396 #define INT_ADC_BITS (1) 09397 /* INT_MACRX field */ 09398 #define INT_MACRX (0x00000400u) 09399 #define INT_MACRX_MASK (0x00000400u) 09400 #define INT_MACRX_BIT (10) 09401 #define INT_MACRX_BITS (1) 09402 /* INT_MACTX field */ 09403 #define INT_MACTX (0x00000200u) 09404 #define INT_MACTX_MASK (0x00000200u) 09405 #define INT_MACTX_BIT (9) 09406 #define INT_MACTX_BITS (1) 09407 /* INT_MACTMR field */ 09408 #define INT_MACTMR (0x00000100u) 09409 #define INT_MACTMR_MASK (0x00000100u) 09410 #define INT_MACTMR_BIT (8) 09411 #define INT_MACTMR_BITS (1) 09412 /* INT_SEC field */ 09413 #define INT_SEC (0x00000080u) 09414 #define INT_SEC_MASK (0x00000080u) 09415 #define INT_SEC_BIT (7) 09416 #define INT_SEC_BITS (1) 09417 /* INT_SC2 field */ 09418 #define INT_SC2 (0x00000040u) 09419 #define INT_SC2_MASK (0x00000040u) 09420 #define INT_SC2_BIT (6) 09421 #define INT_SC2_BITS (1) 09422 /* INT_SC1 field */ 09423 #define INT_SC1 (0x00000020u) 09424 #define INT_SC1_MASK (0x00000020u) 09425 #define INT_SC1_BIT (5) 09426 #define INT_SC1_BITS (1) 09427 /* INT_SLEEPTMR field */ 09428 #define INT_SLEEPTMR (0x00000010u) 09429 #define INT_SLEEPTMR_MASK (0x00000010u) 09430 #define INT_SLEEPTMR_BIT (4) 09431 #define INT_SLEEPTMR_BITS (1) 09432 /* INT_BB field */ 09433 #define INT_BB (0x00000008u) 09434 #define INT_BB_MASK (0x00000008u) 09435 #define INT_BB_BIT (3) 09436 #define INT_BB_BITS (1) 09437 /* INT_MGMT field */ 09438 #define INT_MGMT (0x00000004u) 09439 #define INT_MGMT_MASK (0x00000004u) 09440 #define INT_MGMT_BIT (2) 09441 #define INT_MGMT_BITS (1) 09442 /* INT_TIM2 field */ 09443 #define INT_TIM2 (0x00000002u) 09444 #define INT_TIM2_MASK (0x00000002u) 09445 #define INT_TIM2_BIT (1) 09446 #define INT_TIM2_BITS (1) 09447 /* INT_TIM1 field */ 09448 #define INT_TIM1 (0x00000001u) 09449 #define INT_TIM1_MASK (0x00000001u) 09450 #define INT_TIM1_BIT (0) 09451 #define INT_TIM1_BITS (1) 09452 09453 #define INT_PENDSET *((volatile int32u *)0xE000E200u) 09454 #define INT_PENDSET_REG *((volatile int32u *)0xE000E200u) 09455 #define INT_PENDSET_ADDR (0xE000E200u) 09456 #define INT_PENDSET_RESET (0x00000000u) 09457 /* INT_DEBUG field */ 09458 #define INT_DEBUG (0x00010000u) 09459 #define INT_DEBUG_MASK (0x00010000u) 09460 #define INT_DEBUG_BIT (16) 09461 #define INT_DEBUG_BITS (1) 09462 /* INT_IRQD field */ 09463 #define INT_IRQD (0x00008000u) 09464 #define INT_IRQD_MASK (0x00008000u) 09465 #define INT_IRQD_BIT (15) 09466 #define INT_IRQD_BITS (1) 09467 /* INT_IRQC field */ 09468 #define INT_IRQC (0x00004000u) 09469 #define INT_IRQC_MASK (0x00004000u) 09470 #define INT_IRQC_BIT (14) 09471 #define INT_IRQC_BITS (1) 09472 /* INT_IRQB field */ 09473 #define INT_IRQB (0x00002000u) 09474 #define INT_IRQB_MASK (0x00002000u) 09475 #define INT_IRQB_BIT (13) 09476 #define INT_IRQB_BITS (1) 09477 /* INT_IRQA field */ 09478 #define INT_IRQA (0x00001000u) 09479 #define INT_IRQA_MASK (0x00001000u) 09480 #define INT_IRQA_BIT (12) 09481 #define INT_IRQA_BITS (1) 09482 /* INT_ADC field */ 09483 #define INT_ADC (0x00000800u) 09484 #define INT_ADC_MASK (0x00000800u) 09485 #define INT_ADC_BIT (11) 09486 #define INT_ADC_BITS (1) 09487 /* INT_MACRX field */ 09488 #define INT_MACRX (0x00000400u) 09489 #define INT_MACRX_MASK (0x00000400u) 09490 #define INT_MACRX_BIT (10) 09491 #define INT_MACRX_BITS (1) 09492 /* INT_MACTX field */ 09493 #define INT_MACTX (0x00000200u) 09494 #define INT_MACTX_MASK (0x00000200u) 09495 #define INT_MACTX_BIT (9) 09496 #define INT_MACTX_BITS (1) 09497 /* INT_MACTMR field */ 09498 #define INT_MACTMR (0x00000100u) 09499 #define INT_MACTMR_MASK (0x00000100u) 09500 #define INT_MACTMR_BIT (8) 09501 #define INT_MACTMR_BITS (1) 09502 /* INT_SEC field */ 09503 #define INT_SEC (0x00000080u) 09504 #define INT_SEC_MASK (0x00000080u) 09505 #define INT_SEC_BIT (7) 09506 #define INT_SEC_BITS (1) 09507 /* INT_SC2 field */ 09508 #define INT_SC2 (0x00000040u) 09509 #define INT_SC2_MASK (0x00000040u) 09510 #define INT_SC2_BIT (6) 09511 #define INT_SC2_BITS (1) 09512 /* INT_SC1 field */ 09513 #define INT_SC1 (0x00000020u) 09514 #define INT_SC1_MASK (0x00000020u) 09515 #define INT_SC1_BIT (5) 09516 #define INT_SC1_BITS (1) 09517 /* INT_SLEEPTMR field */ 09518 #define INT_SLEEPTMR (0x00000010u) 09519 #define INT_SLEEPTMR_MASK (0x00000010u) 09520 #define INT_SLEEPTMR_BIT (4) 09521 #define INT_SLEEPTMR_BITS (1) 09522 /* INT_BB field */ 09523 #define INT_BB (0x00000008u) 09524 #define INT_BB_MASK (0x00000008u) 09525 #define INT_BB_BIT (3) 09526 #define INT_BB_BITS (1) 09527 /* INT_MGMT field */ 09528 #define INT_MGMT (0x00000004u) 09529 #define INT_MGMT_MASK (0x00000004u) 09530 #define INT_MGMT_BIT (2) 09531 #define INT_MGMT_BITS (1) 09532 /* INT_TIM2 field */ 09533 #define INT_TIM2 (0x00000002u) 09534 #define INT_TIM2_MASK (0x00000002u) 09535 #define INT_TIM2_BIT (1) 09536 #define INT_TIM2_BITS (1) 09537 /* INT_TIM1 field */ 09538 #define INT_TIM1 (0x00000001u) 09539 #define INT_TIM1_MASK (0x00000001u) 09540 #define INT_TIM1_BIT (0) 09541 #define INT_TIM1_BITS (1) 09542 09543 #define INT_PENDCLR *((volatile int32u *)0xE000E280u) 09544 #define INT_PENDCLR_REG *((volatile int32u *)0xE000E280u) 09545 #define INT_PENDCLR_ADDR (0xE000E280u) 09546 #define INT_PENDCLR_RESET (0x00000000u) 09547 /* INT_DEBUG field */ 09548 #define INT_DEBUG (0x00010000u) 09549 #define INT_DEBUG_MASK (0x00010000u) 09550 #define INT_DEBUG_BIT (16) 09551 #define INT_DEBUG_BITS (1) 09552 /* INT_IRQD field */ 09553 #define INT_IRQD (0x00008000u) 09554 #define INT_IRQD_MASK (0x00008000u) 09555 #define INT_IRQD_BIT (15) 09556 #define INT_IRQD_BITS (1) 09557 /* INT_IRQC field */ 09558 #define INT_IRQC (0x00004000u) 09559 #define INT_IRQC_MASK (0x00004000u) 09560 #define INT_IRQC_BIT (14) 09561 #define INT_IRQC_BITS (1) 09562 /* INT_IRQB field */ 09563 #define INT_IRQB (0x00002000u) 09564 #define INT_IRQB_MASK (0x00002000u) 09565 #define INT_IRQB_BIT (13) 09566 #define INT_IRQB_BITS (1) 09567 /* INT_IRQA field */ 09568 #define INT_IRQA (0x00001000u) 09569 #define INT_IRQA_MASK (0x00001000u) 09570 #define INT_IRQA_BIT (12) 09571 #define INT_IRQA_BITS (1) 09572 /* INT_ADC field */ 09573 #define INT_ADC (0x00000800u) 09574 #define INT_ADC_MASK (0x00000800u) 09575 #define INT_ADC_BIT (11) 09576 #define INT_ADC_BITS (1) 09577 /* INT_MACRX field */ 09578 #define INT_MACRX (0x00000400u) 09579 #define INT_MACRX_MASK (0x00000400u) 09580 #define INT_MACRX_BIT (10) 09581 #define INT_MACRX_BITS (1) 09582 /* INT_MACTX field */ 09583 #define INT_MACTX (0x00000200u) 09584 #define INT_MACTX_MASK (0x00000200u) 09585 #define INT_MACTX_BIT (9) 09586 #define INT_MACTX_BITS (1) 09587 /* INT_MACTMR field */ 09588 #define INT_MACTMR (0x00000100u) 09589 #define INT_MACTMR_MASK (0x00000100u) 09590 #define INT_MACTMR_BIT (8) 09591 #define INT_MACTMR_BITS (1) 09592 /* INT_SEC field */ 09593 #define INT_SEC (0x00000080u) 09594 #define INT_SEC_MASK (0x00000080u) 09595 #define INT_SEC_BIT (7) 09596 #define INT_SEC_BITS (1) 09597 /* INT_SC2 field */ 09598 #define INT_SC2 (0x00000040u) 09599 #define INT_SC2_MASK (0x00000040u) 09600 #define INT_SC2_BIT (6) 09601 #define INT_SC2_BITS (1) 09602 /* INT_SC1 field */ 09603 #define INT_SC1 (0x00000020u) 09604 #define INT_SC1_MASK (0x00000020u) 09605 #define INT_SC1_BIT (5) 09606 #define INT_SC1_BITS (1) 09607 /* INT_SLEEPTMR field */ 09608 #define INT_SLEEPTMR (0x00000010u) 09609 #define INT_SLEEPTMR_MASK (0x00000010u) 09610 #define INT_SLEEPTMR_BIT (4) 09611 #define INT_SLEEPTMR_BITS (1) 09612 /* INT_BB field */ 09613 #define INT_BB (0x00000008u) 09614 #define INT_BB_MASK (0x00000008u) 09615 #define INT_BB_BIT (3) 09616 #define INT_BB_BITS (1) 09617 /* INT_MGMT field */ 09618 #define INT_MGMT (0x00000004u) 09619 #define INT_MGMT_MASK (0x00000004u) 09620 #define INT_MGMT_BIT (2) 09621 #define INT_MGMT_BITS (1) 09622 /* INT_TIM2 field */ 09623 #define INT_TIM2 (0x00000002u) 09624 #define INT_TIM2_MASK (0x00000002u) 09625 #define INT_TIM2_BIT (1) 09626 #define INT_TIM2_BITS (1) 09627 /* INT_TIM1 field */ 09628 #define INT_TIM1 (0x00000001u) 09629 #define INT_TIM1_MASK (0x00000001u) 09630 #define INT_TIM1_BIT (0) 09631 #define INT_TIM1_BITS (1) 09632 09633 #define INT_ACTIVE *((volatile int32u *)0xE000E300u) 09634 #define INT_ACTIVE_REG *((volatile int32u *)0xE000E300u) 09635 #define INT_ACTIVE_ADDR (0xE000E300u) 09636 #define INT_ACTIVE_RESET (0x00000000u) 09637 /* INT_DEBUG field */ 09638 #define INT_DEBUG (0x00010000u) 09639 #define INT_DEBUG_MASK (0x00010000u) 09640 #define INT_DEBUG_BIT (16) 09641 #define INT_DEBUG_BITS (1) 09642 /* INT_IRQD field */ 09643 #define INT_IRQD (0x00008000u) 09644 #define INT_IRQD_MASK (0x00008000u) 09645 #define INT_IRQD_BIT (15) 09646 #define INT_IRQD_BITS (1) 09647 /* INT_IRQC field */ 09648 #define INT_IRQC (0x00004000u) 09649 #define INT_IRQC_MASK (0x00004000u) 09650 #define INT_IRQC_BIT (14) 09651 #define INT_IRQC_BITS (1) 09652 /* INT_IRQB field */ 09653 #define INT_IRQB (0x00002000u) 09654 #define INT_IRQB_MASK (0x00002000u) 09655 #define INT_IRQB_BIT (13) 09656 #define INT_IRQB_BITS (1) 09657 /* INT_IRQA field */ 09658 #define INT_IRQA (0x00001000u) 09659 #define INT_IRQA_MASK (0x00001000u) 09660 #define INT_IRQA_BIT (12) 09661 #define INT_IRQA_BITS (1) 09662 /* INT_ADC field */ 09663 #define INT_ADC (0x00000800u) 09664 #define INT_ADC_MASK (0x00000800u) 09665 #define INT_ADC_BIT (11) 09666 #define INT_ADC_BITS (1) 09667 /* INT_MACRX field */ 09668 #define INT_MACRX (0x00000400u) 09669 #define INT_MACRX_MASK (0x00000400u) 09670 #define INT_MACRX_BIT (10) 09671 #define INT_MACRX_BITS (1) 09672 /* INT_MACTX field */ 09673 #define INT_MACTX (0x00000200u) 09674 #define INT_MACTX_MASK (0x00000200u) 09675 #define INT_MACTX_BIT (9) 09676 #define INT_MACTX_BITS (1) 09677 /* INT_MACTMR field */ 09678 #define INT_MACTMR (0x00000100u) 09679 #define INT_MACTMR_MASK (0x00000100u) 09680 #define INT_MACTMR_BIT (8) 09681 #define INT_MACTMR_BITS (1) 09682 /* INT_SEC field */ 09683 #define INT_SEC (0x00000080u) 09684 #define INT_SEC_MASK (0x00000080u) 09685 #define INT_SEC_BIT (7) 09686 #define INT_SEC_BITS (1) 09687 /* INT_SC2 field */ 09688 #define INT_SC2 (0x00000040u) 09689 #define INT_SC2_MASK (0x00000040u) 09690 #define INT_SC2_BIT (6) 09691 #define INT_SC2_BITS (1) 09692 /* INT_SC1 field */ 09693 #define INT_SC1 (0x00000020u) 09694 #define INT_SC1_MASK (0x00000020u) 09695 #define INT_SC1_BIT (5) 09696 #define INT_SC1_BITS (1) 09697 /* INT_SLEEPTMR field */ 09698 #define INT_SLEEPTMR (0x00000010u) 09699 #define INT_SLEEPTMR_MASK (0x00000010u) 09700 #define INT_SLEEPTMR_BIT (4) 09701 #define INT_SLEEPTMR_BITS (1) 09702 /* INT_BB field */ 09703 #define INT_BB (0x00000008u) 09704 #define INT_BB_MASK (0x00000008u) 09705 #define INT_BB_BIT (3) 09706 #define INT_BB_BITS (1) 09707 /* INT_MGMT field */ 09708 #define INT_MGMT (0x00000004u) 09709 #define INT_MGMT_MASK (0x00000004u) 09710 #define INT_MGMT_BIT (2) 09711 #define INT_MGMT_BITS (1) 09712 /* INT_TIM2 field */ 09713 #define INT_TIM2 (0x00000002u) 09714 #define INT_TIM2_MASK (0x00000002u) 09715 #define INT_TIM2_BIT (1) 09716 #define INT_TIM2_BITS (1) 09717 /* INT_TIM1 field */ 09718 #define INT_TIM1 (0x00000001u) 09719 #define INT_TIM1_MASK (0x00000001u) 09720 #define INT_TIM1_BIT (0) 09721 #define INT_TIM1_BITS (1) 09722 09723 #define NVIC_IPR_3to0 *((volatile int32u *)0xE000E400u) 09724 #define NVIC_IPR_3to0_REG *((volatile int32u *)0xE000E400u) 09725 #define NVIC_IPR_3to0_ADDR (0xE000E400u) 09726 #define NVIC_IPR_3to0_RESET (0x00000000u) 09727 /* PRI_3 field */ 09728 #define NVIC_IPR_3to0_PRI_3 (0xFF000000u) 09729 #define NVIC_IPR_3to0_PRI_3_MASK (0xFF000000u) 09730 #define NVIC_IPR_3to0_PRI_3_BIT (24) 09731 #define NVIC_IPR_3to0_PRI_3_BITS (8) 09732 /* PRI_2 field */ 09733 #define NVIC_IPR_3to0_PRI_2 (0x00FF0000u) 09734 #define NVIC_IPR_3to0_PRI_2_MASK (0x00FF0000u) 09735 #define NVIC_IPR_3to0_PRI_2_BIT (16) 09736 #define NVIC_IPR_3to0_PRI_2_BITS (8) 09737 /* PRI_1 field */ 09738 #define NVIC_IPR_3to0_PRI_1 (0x0000FF00u) 09739 #define NVIC_IPR_3to0_PRI_1_MASK (0x0000FF00u) 09740 #define NVIC_IPR_3to0_PRI_1_BIT (8) 09741 #define NVIC_IPR_3to0_PRI_1_BITS (8) 09742 /* PRI_0 field */ 09743 #define NVIC_IPR_3to0_PRI_0 (0x000000FFu) 09744 #define NVIC_IPR_3to0_PRI_0_MASK (0x000000FFu) 09745 #define NVIC_IPR_3to0_PRI_0_BIT (0) 09746 #define NVIC_IPR_3to0_PRI_0_BITS (8) 09747 09748 #define NVIC_IPR_7to4 *((volatile int32u *)0xE000E404u) 09749 #define NVIC_IPR_7to4_REG *((volatile int32u *)0xE000E404u) 09750 #define NVIC_IPR_7to4_ADDR (0xE000E404u) 09751 #define NVIC_IPR_7to4_RESET (0x00000000u) 09752 /* PRI_7 field */ 09753 #define NVIC_IPR_7to4_PRI_7 (0xFF000000u) 09754 #define NVIC_IPR_7to4_PRI_7_MASK (0xFF000000u) 09755 #define NVIC_IPR_7to4_PRI_7_BIT (24) 09756 #define NVIC_IPR_7to4_PRI_7_BITS (8) 09757 /* PRI_6 field */ 09758 #define NVIC_IPR_7to4_PRI_6 (0x00FF0000u) 09759 #define NVIC_IPR_7to4_PRI_6_MASK (0x00FF0000u) 09760 #define NVIC_IPR_7to4_PRI_6_BIT (16) 09761 #define NVIC_IPR_7to4_PRI_6_BITS (8) 09762 /* PRI_5 field */ 09763 #define NVIC_IPR_7to4_PRI_5 (0x0000FF00u) 09764 #define NVIC_IPR_7to4_PRI_5_MASK (0x0000FF00u) 09765 #define NVIC_IPR_7to4_PRI_5_BIT (8) 09766 #define NVIC_IPR_7to4_PRI_5_BITS (8) 09767 /* PRI_4 field */ 09768 #define NVIC_IPR_7to4_PRI_4 (0x000000FFu) 09769 #define NVIC_IPR_7to4_PRI_4_MASK (0x000000FFu) 09770 #define NVIC_IPR_7to4_PRI_4_BIT (0) 09771 #define NVIC_IPR_7to4_PRI_4_BITS (8) 09772 09773 #define NVIC_IPR_11to8 *((volatile int32u *)0xE000E408u) 09774 #define NVIC_IPR_11to8_REG *((volatile int32u *)0xE000E408u) 09775 #define NVIC_IPR_11to8_ADDR (0xE000E408u) 09776 #define NVIC_IPR_11to8_RESET (0x00000000u) 09777 /* PRI_11 field */ 09778 #define NVIC_IPR_11to8_PRI_11 (0xFF000000u) 09779 #define NVIC_IPR_11to8_PRI_11_MASK (0xFF000000u) 09780 #define NVIC_IPR_11to8_PRI_11_BIT (24) 09781 #define NVIC_IPR_11to8_PRI_11_BITS (8) 09782 /* PRI_10 field */ 09783 #define NVIC_IPR_11to8_PRI_10 (0x00FF0000u) 09784 #define NVIC_IPR_11to8_PRI_10_MASK (0x00FF0000u) 09785 #define NVIC_IPR_11to8_PRI_10_BIT (16) 09786 #define NVIC_IPR_11to8_PRI_10_BITS (8) 09787 /* PRI_9 field */ 09788 #define NVIC_IPR_11to8_PRI_9 (0x0000FF00u) 09789 #define NVIC_IPR_11to8_PRI_9_MASK (0x0000FF00u) 09790 #define NVIC_IPR_11to8_PRI_9_BIT (8) 09791 #define NVIC_IPR_11to8_PRI_9_BITS (8) 09792 /* PRI_8 field */ 09793 #define NVIC_IPR_11to8_PRI_8 (0x000000FFu) 09794 #define NVIC_IPR_11to8_PRI_8_MASK (0x000000FFu) 09795 #define NVIC_IPR_11to8_PRI_8_BIT (0) 09796 #define NVIC_IPR_11to8_PRI_8_BITS (8) 09797 09798 #define NVIC_IPR_15to12 *((volatile int32u *)0xE000E40Cu) 09799 #define NVIC_IPR_15to12_REG *((volatile int32u *)0xE000E40Cu) 09800 #define NVIC_IPR_15to12_ADDR (0xE000E40Cu) 09801 #define NVIC_IPR_15to12_RESET (0x00000000u) 09802 /* PRI_15 field */ 09803 #define NVIC_IPR_15to12_PRI_15 (0xFF000000u) 09804 #define NVIC_IPR_15to12_PRI_15_MASK (0xFF000000u) 09805 #define NVIC_IPR_15to12_PRI_15_BIT (24) 09806 #define NVIC_IPR_15to12_PRI_15_BITS (8) 09807 /* PRI_14 field */ 09808 #define NVIC_IPR_15to12_PRI_14 (0x00FF0000u) 09809 #define NVIC_IPR_15to12_PRI_14_MASK (0x00FF0000u) 09810 #define NVIC_IPR_15to12_PRI_14_BIT (16) 09811 #define NVIC_IPR_15to12_PRI_14_BITS (8) 09812 /* PRI_13 field */ 09813 #define NVIC_IPR_15to12_PRI_13 (0x0000FF00u) 09814 #define NVIC_IPR_15to12_PRI_13_MASK (0x0000FF00u) 09815 #define NVIC_IPR_15to12_PRI_13_BIT (8) 09816 #define NVIC_IPR_15to12_PRI_13_BITS (8) 09817 /* PRI_12 field */ 09818 #define NVIC_IPR_15to12_PRI_12 (0x000000FFu) 09819 #define NVIC_IPR_15to12_PRI_12_MASK (0x000000FFu) 09820 #define NVIC_IPR_15to12_PRI_12_BIT (0) 09821 #define NVIC_IPR_15to12_PRI_12_BITS (8) 09822 09823 #define NVIC_IPR_19to16 *((volatile int32u *)0xE000E410u) 09824 #define NVIC_IPR_19to16_REG *((volatile int32u *)0xE000E410u) 09825 #define NVIC_IPR_19to16_ADDR (0xE000E410u) 09826 #define NVIC_IPR_19to16_RESET (0x00000000u) 09827 /* PRI_19 field */ 09828 #define NVIC_IPR_19to16_PRI_19 (0xFF000000u) 09829 #define NVIC_IPR_19to16_PRI_19_MASK (0xFF000000u) 09830 #define NVIC_IPR_19to16_PRI_19_BIT (24) 09831 #define NVIC_IPR_19to16_PRI_19_BITS (8) 09832 /* PRI_18 field */ 09833 #define NVIC_IPR_19to16_PRI_18 (0x00FF0000u) 09834 #define NVIC_IPR_19to16_PRI_18_MASK (0x00FF0000u) 09835 #define NVIC_IPR_19to16_PRI_18_BIT (16) 09836 #define NVIC_IPR_19to16_PRI_18_BITS (8) 09837 /* PRI_17 field */ 09838 #define NVIC_IPR_19to16_PRI_17 (0x0000FF00u) 09839 #define NVIC_IPR_19to16_PRI_17_MASK (0x0000FF00u) 09840 #define NVIC_IPR_19to16_PRI_17_BIT (8) 09841 #define NVIC_IPR_19to16_PRI_17_BITS (8) 09842 /* PRI_16 field */ 09843 #define NVIC_IPR_19to16_PRI_16 (0x000000FFu) 09844 #define NVIC_IPR_19to16_PRI_16_MASK (0x000000FFu) 09845 #define NVIC_IPR_19to16_PRI_16_BIT (0) 09846 #define NVIC_IPR_19to16_PRI_16_BITS (8) 09847 09848 #define SCS_CPUID *((volatile int32u *)0xE000ED00u) 09849 #define SCS_CPUID_REG *((volatile int32u *)0xE000ED00u) 09850 #define SCS_CPUID_ADDR (0xE000ED00u) 09851 #define SCS_CPUID_RESET (0x411FC231u) 09852 /* IMPLEMENTER field */ 09853 #define SCS_CPUID_IMPLEMENTER (0xFF000000u) 09854 #define SCS_CPUID_IMPLEMENTER_MASK (0xFF000000u) 09855 #define SCS_CPUID_IMPLEMENTER_BIT (24) 09856 #define SCS_CPUID_IMPLEMENTER_BITS (8) 09857 /* VARIANT field */ 09858 #define SCS_CPUID_VARIANT (0x00F00000u) 09859 #define SCS_CPUID_VARIANT_MASK (0x00F00000u) 09860 #define SCS_CPUID_VARIANT_BIT (20) 09861 #define SCS_CPUID_VARIANT_BITS (4) 09862 /* CONSTANT field */ 09863 #define SCS_CPUID_CONSTANT (0x000F0000u) 09864 #define SCS_CPUID_CONSTANT_MASK (0x000F0000u) 09865 #define SCS_CPUID_CONSTANT_BIT (16) 09866 #define SCS_CPUID_CONSTANT_BITS (4) 09867 /* PARTNO field */ 09868 #define SCS_CPUID_PARTNO (0x0000FFF0u) 09869 #define SCS_CPUID_PARTNO_MASK (0x0000FFF0u) 09870 #define SCS_CPUID_PARTNO_BIT (4) 09871 #define SCS_CPUID_PARTNO_BITS (12) 09872 /* REVISION field */ 09873 #define SCS_CPUID_REVISION (0x0000000Fu) 09874 #define SCS_CPUID_REVISION_MASK (0x0000000Fu) 09875 #define SCS_CPUID_REVISION_BIT (0) 09876 #define SCS_CPUID_REVISION_BITS (4) 09877 09878 #define SCS_ICSR *((volatile int32u *)0xE000ED04u) 09879 #define SCS_ICSR_REG *((volatile int32u *)0xE000ED04u) 09880 #define SCS_ICSR_ADDR (0xE000ED04u) 09881 #define SCS_ICSR_RESET (0x00000000u) 09882 /* NMIPENDSET field */ 09883 #define SCS_ICSR_NMIPENDSET (0x80000000u) 09884 #define SCS_ICSR_NMIPENDSET_MASK (0x80000000u) 09885 #define SCS_ICSR_NMIPENDSET_BIT (31) 09886 #define SCS_ICSR_NMIPENDSET_BITS (1) 09887 /* PENDSVSET field */ 09888 #define SCS_ICSR_PENDSVSET (0x10000000u) 09889 #define SCS_ICSR_PENDSVSET_MASK (0x10000000u) 09890 #define SCS_ICSR_PENDSVSET_BIT (28) 09891 #define SCS_ICSR_PENDSVSET_BITS (1) 09892 /* PENDSVCLR field */ 09893 #define SCS_ICSR_PENDSVCLR (0x08000000u) 09894 #define SCS_ICSR_PENDSVCLR_MASK (0x08000000u) 09895 #define SCS_ICSR_PENDSVCLR_BIT (27) 09896 #define SCS_ICSR_PENDSVCLR_BITS (1) 09897 /* PENDSTSET field */ 09898 #define SCS_ICSR_PENDSTSET (0x04000000u) 09899 #define SCS_ICSR_PENDSTSET_MASK (0x04000000u) 09900 #define SCS_ICSR_PENDSTSET_BIT (26) 09901 #define SCS_ICSR_PENDSTSET_BITS (1) 09902 /* PENDSTCLR field */ 09903 #define SCS_ICSR_PENDSTCLR (0x02000000u) 09904 #define SCS_ICSR_PENDSTCLR_MASK (0x02000000u) 09905 #define SCS_ICSR_PENDSTCLR_BIT (25) 09906 #define SCS_ICSR_PENDSTCLR_BITS (1) 09907 /* ISRPREEMPT field */ 09908 #define SCS_ICSR_ISRPREEMPT (0x00800000u) 09909 #define SCS_ICSR_ISRPREEMPT_MASK (0x00800000u) 09910 #define SCS_ICSR_ISRPREEMPT_BIT (23) 09911 #define SCS_ICSR_ISRPREEMPT_BITS (1) 09912 /* ISRPENDING field */ 09913 #define SCS_ICSR_ISRPENDING (0x00400000u) 09914 #define SCS_ICSR_ISRPENDING_MASK (0x00400000u) 09915 #define SCS_ICSR_ISRPENDING_BIT (22) 09916 #define SCS_ICSR_ISRPENDING_BITS (1) 09917 /* VECTPENDING field */ 09918 #define SCS_ICSR_VECTPENDING (0x001FF000u) 09919 #define SCS_ICSR_VECTPENDING_MASK (0x001FF000u) 09920 #define SCS_ICSR_VECTPENDING_BIT (12) 09921 #define SCS_ICSR_VECTPENDING_BITS (9) 09922 /* RETTOBASE field */ 09923 #define SCS_ICSR_RETTOBASE (0x00000800u) 09924 #define SCS_ICSR_RETTOBASE_MASK (0x00000800u) 09925 #define SCS_ICSR_RETTOBASE_BIT (11) 09926 #define SCS_ICSR_RETTOBASE_BITS (1) 09927 /* VECACTIVE field */ 09928 #define SCS_ICSR_VECACTIVE (0x000001FFu) 09929 #define SCS_ICSR_VECACTIVE_MASK (0x000001FFu) 09930 #define SCS_ICSR_VECACTIVE_BIT (0) 09931 #define SCS_ICSR_VECACTIVE_BITS (9) 09932 09933 #define SCS_VTOR *((volatile int32u *)0xE000ED08u) 09934 #define SCS_VTOR_REG *((volatile int32u *)0xE000ED08u) 09935 #define SCS_VTOR_ADDR (0xE000ED08u) 09936 #define SCS_VTOR_RESET (0x00000000u) 09937 /* TBLBASE field */ 09938 #define SCS_VTOR_TBLBASE (0x20000000u) 09939 #define SCS_VTOR_TBLBASE_MASK (0x20000000u) 09940 #define SCS_VTOR_TBLBASE_BIT (29) 09941 #define SCS_VTOR_TBLBASE_BITS (1) 09942 /* TBLOFF field */ 09943 #define SCS_VTOR_TBLOFF (0x1FFFFF00u) 09944 #define SCS_VTOR_TBLOFF_MASK (0x1FFFFF00u) 09945 #define SCS_VTOR_TBLOFF_BIT (8) 09946 #define SCS_VTOR_TBLOFF_BITS (21) 09947 09948 #define SCS_AIRCR *((volatile int32u *)0xE000ED0Cu) 09949 #define SCS_AIRCR_REG *((volatile int32u *)0xE000ED0Cu) 09950 #define SCS_AIRCR_ADDR (0xE000ED0Cu) 09951 #define SCS_AIRCR_RESET (0x00000000u) 09952 /* VECTKEYSTAT field */ 09953 #define SCS_AIRCR_VECTKEYSTAT (0xFFFF0000u) 09954 #define SCS_AIRCR_VECTKEYSTAT_MASK (0xFFFF0000u) 09955 #define SCS_AIRCR_VECTKEYSTAT_BIT (16) 09956 #define SCS_AIRCR_VECTKEYSTAT_BITS (16) 09957 /* VECTKEY field */ 09958 #define SCS_AIRCR_VECTKEY (0xFFFF0000u) 09959 #define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u) 09960 #define SCS_AIRCR_VECTKEY_BIT (16) 09961 #define SCS_AIRCR_VECTKEY_BITS (16) 09962 /* ENDIANESS field */ 09963 #define SCS_AIRCR_ENDIANESS (0x00008000u) 09964 #define SCS_AIRCR_ENDIANESS_MASK (0x00008000u) 09965 #define SCS_AIRCR_ENDIANESS_BIT (15) 09966 #define SCS_AIRCR_ENDIANESS_BITS (1) 09967 /* PRIGROUP field */ 09968 #define SCS_AIRCR_PRIGROUP (0x00000700u) 09969 #define SCS_AIRCR_PRIGROUP_MASK (0x00000700u) 09970 #define SCS_AIRCR_PRIGROUP_BIT (8) 09971 #define SCS_AIRCR_PRIGROUP_BITS (3) 09972 /* SYSRESETREQ field */ 09973 #define SCS_AIRCR_SYSRESETREQ (0x00000004u) 09974 #define SCS_AIRCR_SYSRESETREQ_MASK (0x00000004u) 09975 #define SCS_AIRCR_SYSRESETREQ_BIT (2) 09976 #define SCS_AIRCR_SYSRESETREQ_BITS (1) 09977 /* VECTCLRACTIVE field */ 09978 #define SCS_AIRCR_VECTCLRACTIVE (0x00000002u) 09979 #define SCS_AIRCR_VECTCLRACTIVE_MASK (0x00000002u) 09980 #define SCS_AIRCR_VECTCLRACTIVE_BIT (1) 09981 #define SCS_AIRCR_VECTCLRACTIVE_BITS (1) 09982 /* VECTRESET field */ 09983 #define SCS_AIRCR_VECTRESET (0x00000001u) 09984 #define SCS_AIRCR_VECTRESET_MASK (0x00000001u) 09985 #define SCS_AIRCR_VECTRESET_BIT (0) 09986 #define SCS_AIRCR_VECTRESET_BITS (1) 09987 09988 #define SCS_SCR *((volatile int32u *)0xE000ED10u) 09989 #define SCS_SCR_REG *((volatile int32u *)0xE000ED10u) 09990 #define SCS_SCR_ADDR (0xE000ED10u) 09991 #define SCS_SCR_RESET (0x00000000u) 09992 /* SEVONPEND field */ 09993 #define SCS_SCR_SEVONPEND (0x00000010u) 09994 #define SCS_SCR_SEVONPEND_MASK (0x00000010u) 09995 #define SCS_SCR_SEVONPEND_BIT (4) 09996 #define SCS_SCR_SEVONPEND_BITS (1) 09997 /* SLEEPDEEP field */ 09998 #define SCS_SCR_SLEEPDEEP (0x00000004u) 09999 #define SCS_SCR_SLEEPDEEP_MASK (0x00000004u) 10000 #define SCS_SCR_SLEEPDEEP_BIT (2) 10001 #define SCS_SCR_SLEEPDEEP_BITS (1) 10002 /* SLEEPONEXIT field */ 10003 #define SCS_SCR_SLEEPONEXIT (0x00000002u) 10004 #define SCS_SCR_SLEEPONEXIT_MASK (0x00000002u) 10005 #define SCS_SCR_SLEEPONEXIT_BIT (1) 10006 #define SCS_SCR_SLEEPONEXIT_BITS (1) 10007 10008 #define SCS_CCR *((volatile int32u *)0xE000ED14u) 10009 #define SCS_CCR_REG *((volatile int32u *)0xE000ED14u) 10010 #define SCS_CCR_ADDR (0xE000ED14u) 10011 #define SCS_CCR_RESET (0x00000000u) 10012 /* STKALIGN field */ 10013 #define SCS_CCR_STKALIGN (0x00000200u) 10014 #define SCS_CCR_STKALIGN_MASK (0x00000200u) 10015 #define SCS_CCR_STKALIGN_BIT (9) 10016 #define SCS_CCR_STKALIGN_BITS (1) 10017 /* BFHFNMIGN field */ 10018 #define SCS_CCR_BFHFNMIGN (0x00000100u) 10019 #define SCS_CCR_BFHFNMIGN_MASK (0x00000100u) 10020 #define SCS_CCR_BFHFNMIGN_BIT (8) 10021 #define SCS_CCR_BFHFNMIGN_BITS (1) 10022 /* DIV_0_TRP field */ 10023 #define SCS_CCR_DIV_0_TRP (0x00000010u) 10024 #define SCS_CCR_DIV_0_TRP_MASK (0x00000010u) 10025 #define SCS_CCR_DIV_0_TRP_BIT (4) 10026 #define SCS_CCR_DIV_0_TRP_BITS (1) 10027 /* UNALIGN_TRP field */ 10028 #define SCS_CCR_UNALIGN_TRP (0x00000008u) 10029 #define SCS_CCR_UNALIGN_TRP_MASK (0x00000008u) 10030 #define SCS_CCR_UNALIGN_TRP_BIT (3) 10031 #define SCS_CCR_UNALIGN_TRP_BITS (1) 10032 /* USERSETMPEND field */ 10033 #define SCS_CCR_USERSETMPEND (0x00000002u) 10034 #define SCS_CCR_USERSETMPEND_MASK (0x00000002u) 10035 #define SCS_CCR_USERSETMPEND_BIT (1) 10036 #define SCS_CCR_USERSETMPEND_BITS (1) 10037 /* NONBASETHRDENA field */ 10038 #define SCS_CCR_NONBASETHRDENA (0x00000001u) 10039 #define SCS_CCR_NONBASETHRDENA_MASK (0x00000001u) 10040 #define SCS_CCR_NONBASETHRDENA_BIT (0) 10041 #define SCS_CCR_NONBASETHRDENA_BITS (1) 10042 10043 #define SCS_SHPR_7to4 *((volatile int32u *)0xE000ED18u) 10044 #define SCS_SHPR_7to4_REG *((volatile int32u *)0xE000ED18u) 10045 #define SCS_SHPR_7to4_ADDR (0xE000ED18u) 10046 #define SCS_SHPR_7to4_RESET (0x00000000u) 10047 /* PRI_7 field */ 10048 #define SCS_SHPR_7to4_PRI_7 (0xFF000000u) 10049 #define SCS_SHPR_7to4_PRI_7_MASK (0xFF000000u) 10050 #define SCS_SHPR_7to4_PRI_7_BIT (24) 10051 #define SCS_SHPR_7to4_PRI_7_BITS (8) 10052 /* PRI_6 field */ 10053 #define SCS_SHPR_7to4_PRI_6 (0x00FF0000u) 10054 #define SCS_SHPR_7to4_PRI_6_MASK (0x00FF0000u) 10055 #define SCS_SHPR_7to4_PRI_6_BIT (16) 10056 #define SCS_SHPR_7to4_PRI_6_BITS (8) 10057 /* PRI_5 field */ 10058 #define SCS_SHPR_7to4_PRI_5 (0x0000FF00u) 10059 #define SCS_SHPR_7to4_PRI_5_MASK (0x0000FF00u) 10060 #define SCS_SHPR_7to4_PRI_5_BIT (8) 10061 #define SCS_SHPR_7to4_PRI_5_BITS (8) 10062 /* PRI_4 field */ 10063 #define SCS_SHPR_7to4_PRI_4 (0x000000FFu) 10064 #define SCS_SHPR_7to4_PRI_4_MASK (0x000000FFu) 10065 #define SCS_SHPR_7to4_PRI_4_BIT (0) 10066 #define SCS_SHPR_7to4_PRI_4_BITS (8) 10067 10068 #define SCS_SHPR_11to8 *((volatile int32u *)0xE000ED1Cu) 10069 #define SCS_SHPR_11to8_REG *((volatile int32u *)0xE000ED1Cu) 10070 #define SCS_SHPR_11to8_ADDR (0xE000ED1Cu) 10071 #define SCS_SHPR_11to8_RESET (0x00000000u) 10072 /* PRI_11 field */ 10073 #define SCS_SHPR_11to8_PRI_11 (0xFF000000u) 10074 #define SCS_SHPR_11to8_PRI_11_MASK (0xFF000000u) 10075 #define SCS_SHPR_11to8_PRI_11_BIT (24) 10076 #define SCS_SHPR_11to8_PRI_11_BITS (8) 10077 /* PRI_10 field */ 10078 #define SCS_SHPR_11to8_PRI_10 (0x00FF0000u) 10079 #define SCS_SHPR_11to8_PRI_10_MASK (0x00FF0000u) 10080 #define SCS_SHPR_11to8_PRI_10_BIT (16) 10081 #define SCS_SHPR_11to8_PRI_10_BITS (8) 10082 /* PRI_9 field */ 10083 #define SCS_SHPR_11to8_PRI_9 (0x0000FF00u) 10084 #define SCS_SHPR_11to8_PRI_9_MASK (0x0000FF00u) 10085 #define SCS_SHPR_11to8_PRI_9_BIT (8) 10086 #define SCS_SHPR_11to8_PRI_9_BITS (8) 10087 /* PRI_8 field */ 10088 #define SCS_SHPR_11to8_PRI_8 (0x000000FFu) 10089 #define SCS_SHPR_11to8_PRI_8_MASK (0x000000FFu) 10090 #define SCS_SHPR_11to8_PRI_8_BIT (0) 10091 #define SCS_SHPR_11to8_PRI_8_BITS (8) 10092 10093 #define SCS_SHPR_15to12 *((volatile int32u *)0xE000ED20u) 10094 #define SCS_SHPR_15to12_REG *((volatile int32u *)0xE000ED20u) 10095 #define SCS_SHPR_15to12_ADDR (0xE000ED20u) 10096 #define SCS_SHPR_15to12_RESET (0x00000000u) 10097 /* PRI_15 field */ 10098 #define SCS_SHPR_15to12_PRI_15 (0xFF000000u) 10099 #define SCS_SHPR_15to12_PRI_15_MASK (0xFF000000u) 10100 #define SCS_SHPR_15to12_PRI_15_BIT (24) 10101 #define SCS_SHPR_15to12_PRI_15_BITS (8) 10102 /* PRI_14 field */ 10103 #define SCS_SHPR_15to12_PRI_14 (0x00FF0000u) 10104 #define SCS_SHPR_15to12_PRI_14_MASK (0x00FF0000u) 10105 #define SCS_SHPR_15to12_PRI_14_BIT (16) 10106 #define SCS_SHPR_15to12_PRI_14_BITS (8) 10107 /* PRI_13 field */ 10108 #define SCS_SHPR_15to12_PRI_13 (0x0000FF00u) 10109 #define SCS_SHPR_15to12_PRI_13_MASK (0x0000FF00u) 10110 #define SCS_SHPR_15to12_PRI_13_BIT (8) 10111 #define SCS_SHPR_15to12_PRI_13_BITS (8) 10112 /* PRI_12 field */ 10113 #define SCS_SHPR_15to12_PRI_12 (0x000000FFu) 10114 #define SCS_SHPR_15to12_PRI_12_MASK (0x000000FFu) 10115 #define SCS_SHPR_15to12_PRI_12_BIT (0) 10116 #define SCS_SHPR_15to12_PRI_12_BITS (8) 10117 10118 #define SCS_SHCSR *((volatile int32u *)0xE000ED24u) 10119 #define SCS_SHCSR_REG *((volatile int32u *)0xE000ED24u) 10120 #define SCS_SHCSR_ADDR (0xE000ED24u) 10121 #define SCS_SHCSR_RESET (0x00000000u) 10122 /* USGFAULTENA field */ 10123 #define SCS_SHCSR_USGFAULTENA (0x00040000u) 10124 #define SCS_SHCSR_USGFAULTENA_MASK (0x00040000u) 10125 #define SCS_SHCSR_USGFAULTENA_BIT (18) 10126 #define SCS_SHCSR_USGFAULTENA_BITS (1) 10127 /* BUSFAULTENA field */ 10128 #define SCS_SHCSR_BUSFAULTENA (0x00020000u) 10129 #define SCS_SHCSR_BUSFAULTENA_MASK (0x00020000u) 10130 #define SCS_SHCSR_BUSFAULTENA_BIT (17) 10131 #define SCS_SHCSR_BUSFAULTENA_BITS (1) 10132 /* MEMFAULTENA field */ 10133 #define SCS_SHCSR_MEMFAULTENA (0x00010000u) 10134 #define SCS_SHCSR_MEMFAULTENA_MASK (0x00010000u) 10135 #define SCS_SHCSR_MEMFAULTENA_BIT (16) 10136 #define SCS_SHCSR_MEMFAULTENA_BITS (1) 10137 /* SVCALLPENDED field */ 10138 #define SCS_SHCSR_SVCALLPENDED (0x00008000u) 10139 #define SCS_SHCSR_SVCALLPENDED_MASK (0x00008000u) 10140 #define SCS_SHCSR_SVCALLPENDED_BIT (15) 10141 #define SCS_SHCSR_SVCALLPENDED_BITS (1) 10142 /* BUSFAULTPENDED field */ 10143 #define SCS_SHCSR_BUSFAULTPENDED (0x00004000u) 10144 #define SCS_SHCSR_BUSFAULTPENDED_MASK (0x00004000u) 10145 #define SCS_SHCSR_BUSFAULTPENDED_BIT (14) 10146 #define SCS_SHCSR_BUSFAULTPENDED_BITS (1) 10147 /* MEMFAULTPENDED field */ 10148 #define SCS_SHCSR_MEMFAULTPENDED (0x00002000u) 10149 #define SCS_SHCSR_MEMFAULTPENDED_MASK (0x00002000u) 10150 #define SCS_SHCSR_MEMFAULTPENDED_BIT (13) 10151 #define SCS_SHCSR_MEMFAULTPENDED_BITS (1) 10152 /* USGFAULTPENDED field */ 10153 #define SCS_SHCSR_USGFAULTPENDED (0x00001000u) 10154 #define SCS_SHCSR_USGFAULTPENDED_MASK (0x00001000u) 10155 #define SCS_SHCSR_USGFAULTPENDED_BIT (12) 10156 #define SCS_SHCSR_USGFAULTPENDED_BITS (1) 10157 /* SYSTICKACT field */ 10158 #define SCS_SHCSR_SYSTICKACT (0x00000800u) 10159 #define SCS_SHCSR_SYSTICKACT_MASK (0x00000800u) 10160 #define SCS_SHCSR_SYSTICKACT_BIT (11) 10161 #define SCS_SHCSR_SYSTICKACT_BITS (1) 10162 /* PENDSVACT field */ 10163 #define SCS_SHCSR_PENDSVACT (0x00000400u) 10164 #define SCS_SHCSR_PENDSVACT_MASK (0x00000400u) 10165 #define SCS_SHCSR_PENDSVACT_BIT (10) 10166 #define SCS_SHCSR_PENDSVACT_BITS (1) 10167 /* MONITORACT field */ 10168 #define SCS_SHCSR_MONITORACT (0x00000100u) 10169 #define SCS_SHCSR_MONITORACT_MASK (0x00000100u) 10170 #define SCS_SHCSR_MONITORACT_BIT (8) 10171 #define SCS_SHCSR_MONITORACT_BITS (1) 10172 /* SVCALLACT field */ 10173 #define SCS_SHCSR_SVCALLACT (0x00000080u) 10174 #define SCS_SHCSR_SVCALLACT_MASK (0x00000080u) 10175 #define SCS_SHCSR_SVCALLACT_BIT (7) 10176 #define SCS_SHCSR_SVCALLACT_BITS (1) 10177 /* USGFAULTACT field */ 10178 #define SCS_SHCSR_USGFAULTACT (0x00000008u) 10179 #define SCS_SHCSR_USGFAULTACT_MASK (0x00000008u) 10180 #define SCS_SHCSR_USGFAULTACT_BIT (3) 10181 #define SCS_SHCSR_USGFAULTACT_BITS (1) 10182 /* BUSFAULTACT field */ 10183 #define SCS_SHCSR_BUSFAULTACT (0x00000002u) 10184 #define SCS_SHCSR_BUSFAULTACT_MASK (0x00000002u) 10185 #define SCS_SHCSR_BUSFAULTACT_BIT (1) 10186 #define SCS_SHCSR_BUSFAULTACT_BITS (1) 10187 /* MEMFAULTACT field */ 10188 #define SCS_SHCSR_MEMFAULTACT (0x00000001u) 10189 #define SCS_SHCSR_MEMFAULTACT_MASK (0x00000001u) 10190 #define SCS_SHCSR_MEMFAULTACT_BIT (0) 10191 #define SCS_SHCSR_MEMFAULTACT_BITS (1) 10192 10193 #define SCS_CFSR *((volatile int32u *)0xE000ED28u) 10194 #define SCS_CFSR_REG *((volatile int32u *)0xE000ED28u) 10195 #define SCS_CFSR_ADDR (0xE000ED28u) 10196 #define SCS_CFSR_RESET (0x00000000u) 10197 /* DIVBYZERO field */ 10198 #define SCS_CFSR_DIVBYZERO (0x02000000u) 10199 #define SCS_CFSR_DIVBYZERO_MASK (0x02000000u) 10200 #define SCS_CFSR_DIVBYZERO_BIT (25) 10201 #define SCS_CFSR_DIVBYZERO_BITS (1) 10202 /* UNALIGNED field */ 10203 #define SCS_CFSR_UNALIGNED (0x01000000u) 10204 #define SCS_CFSR_UNALIGNED_MASK (0x01000000u) 10205 #define SCS_CFSR_UNALIGNED_BIT (24) 10206 #define SCS_CFSR_UNALIGNED_BITS (1) 10207 /* NOCP field */ 10208 #define SCS_CFSR_NOCP (0x00080000u) 10209 #define SCS_CFSR_NOCP_MASK (0x00080000u) 10210 #define SCS_CFSR_NOCP_BIT (19) 10211 #define SCS_CFSR_NOCP_BITS (1) 10212 /* INVPC field */ 10213 #define SCS_CFSR_INVPC (0x00040000u) 10214 #define SCS_CFSR_INVPC_MASK (0x00040000u) 10215 #define SCS_CFSR_INVPC_BIT (18) 10216 #define SCS_CFSR_INVPC_BITS (1) 10217 /* INVSTATE field */ 10218 #define SCS_CFSR_INVSTATE (0x00020000u) 10219 #define SCS_CFSR_INVSTATE_MASK (0x00020000u) 10220 #define SCS_CFSR_INVSTATE_BIT (17) 10221 #define SCS_CFSR_INVSTATE_BITS (1) 10222 /* UNDEFINSTR field */ 10223 #define SCS_CFSR_UNDEFINSTR (0x00010000u) 10224 #define SCS_CFSR_UNDEFINSTR_MASK (0x00010000u) 10225 #define SCS_CFSR_UNDEFINSTR_BIT (16) 10226 #define SCS_CFSR_UNDEFINSTR_BITS (1) 10227 /* BFARVALID field */ 10228 #define SCS_CFSR_BFARVALID (0x00008000u) 10229 #define SCS_CFSR_BFARVALID_MASK (0x00008000u) 10230 #define SCS_CFSR_BFARVALID_BIT (15) 10231 #define SCS_CFSR_BFARVALID_BITS (1) 10232 /* STKERR field */ 10233 #define SCS_CFSR_STKERR (0x00001000u) 10234 #define SCS_CFSR_STKERR_MASK (0x00001000u) 10235 #define SCS_CFSR_STKERR_BIT (12) 10236 #define SCS_CFSR_STKERR_BITS (1) 10237 /* UNSTKERR field */ 10238 #define SCS_CFSR_UNSTKERR (0x00000800u) 10239 #define SCS_CFSR_UNSTKERR_MASK (0x00000800u) 10240 #define SCS_CFSR_UNSTKERR_BIT (11) 10241 #define SCS_CFSR_UNSTKERR_BITS (1) 10242 /* IMPRECISERR field */ 10243 #define SCS_CFSR_IMPRECISERR (0x00000400u) 10244 #define SCS_CFSR_IMPRECISERR_MASK (0x00000400u) 10245 #define SCS_CFSR_IMPRECISERR_BIT (10) 10246 #define SCS_CFSR_IMPRECISERR_BITS (1) 10247 /* PRECISERR field */ 10248 #define SCS_CFSR_PRECISERR (0x00000200u) 10249 #define SCS_CFSR_PRECISERR_MASK (0x00000200u) 10250 #define SCS_CFSR_PRECISERR_BIT (9) 10251 #define SCS_CFSR_PRECISERR_BITS (1) 10252 /* IBUSERR field */ 10253 #define SCS_CFSR_IBUSERR (0x00000100u) 10254 #define SCS_CFSR_IBUSERR_MASK (0x00000100u) 10255 #define SCS_CFSR_IBUSERR_BIT (8) 10256 #define SCS_CFSR_IBUSERR_BITS (1) 10257 /* MMARVALID field */ 10258 #define SCS_CFSR_MMARVALID (0x00000080u) 10259 #define SCS_CFSR_MMARVALID_MASK (0x00000080u) 10260 #define SCS_CFSR_MMARVALID_BIT (7) 10261 #define SCS_CFSR_MMARVALID_BITS (1) 10262 /* MSTKERR field */ 10263 #define SCS_CFSR_MSTKERR (0x00000010u) 10264 #define SCS_CFSR_MSTKERR_MASK (0x00000010u) 10265 #define SCS_CFSR_MSTKERR_BIT (4) 10266 #define SCS_CFSR_MSTKERR_BITS (1) 10267 /* MUNSTKERR field */ 10268 #define SCS_CFSR_MUNSTKERR (0x00000008u) 10269 #define SCS_CFSR_MUNSTKERR_MASK (0x00000008u) 10270 #define SCS_CFSR_MUNSTKERR_BIT (3) 10271 #define SCS_CFSR_MUNSTKERR_BITS (1) 10272 /* DACCVIOL field */ 10273 #define SCS_CFSR_DACCVIOL (0x00000002u) 10274 #define SCS_CFSR_DACCVIOL_MASK (0x00000002u) 10275 #define SCS_CFSR_DACCVIOL_BIT (1) 10276 #define SCS_CFSR_DACCVIOL_BITS (1) 10277 /* IACCVIOL field */ 10278 #define SCS_CFSR_IACCVIOL (0x00000001u) 10279 #define SCS_CFSR_IACCVIOL_MASK (0x00000001u) 10280 #define SCS_CFSR_IACCVIOL_BIT (0) 10281 #define SCS_CFSR_IACCVIOL_BITS (1) 10282 10283 #define SCS_HFSR *((volatile int32u *)0xE000ED2Cu) 10284 #define SCS_HFSR_REG *((volatile int32u *)0xE000ED2Cu) 10285 #define SCS_HFSR_ADDR (0xE000ED2Cu) 10286 #define SCS_HFSR_RESET (0x00000000u) 10287 /* DEBUGEVT field */ 10288 #define SCS_HFSR_DEBUGEVT (0x80000000u) 10289 #define SCS_HFSR_DEBUGEVT_MASK (0x80000000u) 10290 #define SCS_HFSR_DEBUGEVT_BIT (31) 10291 #define SCS_HFSR_DEBUGEVT_BITS (1) 10292 /* FORCED field */ 10293 #define SCS_HFSR_FORCED (0x40000000u) 10294 #define SCS_HFSR_FORCED_MASK (0x40000000u) 10295 #define SCS_HFSR_FORCED_BIT (30) 10296 #define SCS_HFSR_FORCED_BITS (1) 10297 /* VECTTBL field */ 10298 #define SCS_HFSR_VECTTBL (0x00000002u) 10299 #define SCS_HFSR_VECTTBL_MASK (0x00000002u) 10300 #define SCS_HFSR_VECTTBL_BIT (1) 10301 #define SCS_HFSR_VECTTBL_BITS (1) 10302 10303 #define SCS_DFSR *((volatile int32u *)0xE000ED30u) 10304 #define SCS_DFSR_REG *((volatile int32u *)0xE000ED30u) 10305 #define SCS_DFSR_ADDR (0xE000ED30u) 10306 #define SCS_DFSR_RESET (0x00000000u) 10307 /* EXTERNAL field */ 10308 #define SCS_DFSR_EXTERNAL (0x00000010u) 10309 #define SCS_DFSR_EXTERNAL_MASK (0x00000010u) 10310 #define SCS_DFSR_EXTERNAL_BIT (4) 10311 #define SCS_DFSR_EXTERNAL_BITS (1) 10312 /* VCATCH field */ 10313 #define SCS_DFSR_VCATCH (0x00000008u) 10314 #define SCS_DFSR_VCATCH_MASK (0x00000008u) 10315 #define SCS_DFSR_VCATCH_BIT (3) 10316 #define SCS_DFSR_VCATCH_BITS (1) 10317 /* DWTTRAP field */ 10318 #define SCS_DFSR_DWTTRAP (0x00000004u) 10319 #define SCS_DFSR_DWTTRAP_MASK (0x00000004u) 10320 #define SCS_DFSR_DWTTRAP_BIT (2) 10321 #define SCS_DFSR_DWTTRAP_BITS (1) 10322 /* BKPT field */ 10323 #define SCS_DFSR_BKPT (0x00000002u) 10324 #define SCS_DFSR_BKPT_MASK (0x00000002u) 10325 #define SCS_DFSR_BKPT_BIT (1) 10326 #define SCS_DFSR_BKPT_BITS (1) 10327 /* HALTED field */ 10328 #define SCS_DFSR_HALTED (0x00000001u) 10329 #define SCS_DFSR_HALTED_MASK (0x00000001u) 10330 #define SCS_DFSR_HALTED_BIT (0) 10331 #define SCS_DFSR_HALTED_BITS (1) 10332 10333 #define SCS_MMAR *((volatile int32u *)0xE000ED34u) 10334 #define SCS_MMAR_REG *((volatile int32u *)0xE000ED34u) 10335 #define SCS_MMAR_ADDR (0xE000ED34u) 10336 #define SCS_MMAR_RESET (0x00000000u) 10337 /* ADDRESS field */ 10338 #define SCS_MMAR_ADDRESS (0xFFFFFFFFu) 10339 #define SCS_MMAR_ADDRESS_MASK (0xFFFFFFFFu) 10340 #define SCS_MMAR_ADDRESS_BIT (0) 10341 #define SCS_MMAR_ADDRESS_BITS (32) 10342 10343 #define SCS_BFAR *((volatile int32u *)0xE000ED38u) 10344 #define SCS_BFAR_REG *((volatile int32u *)0xE000ED38u) 10345 #define SCS_BFAR_ADDR (0xE000ED38u) 10346 #define SCS_BFAR_RESET (0x00000000u) 10347 /* ADDRESS field */ 10348 #define SCS_BFAR_ADDRESS (0xFFFFFFFFu) 10349 #define SCS_BFAR_ADDRESS_MASK (0xFFFFFFFFu) 10350 #define SCS_BFAR_ADDRESS_BIT (0) 10351 #define SCS_BFAR_ADDRESS_BITS (32) 10352 10353 #define SCS_AFSR *((volatile int32u *)0xE000ED3Cu) 10354 #define SCS_AFSR_REG *((volatile int32u *)0xE000ED3Cu) 10355 #define SCS_AFSR_ADDR (0xE000ED3Cu) 10356 #define SCS_AFSR_RESET (0x00000000u) 10357 /* WRONGSIZE field */ 10358 #define SCS_AFSR_WRONGSIZE (0x00000008u) 10359 #define SCS_AFSR_WRONGSIZE_MASK (0x00000008u) 10360 #define SCS_AFSR_WRONGSIZE_BIT (3) 10361 #define SCS_AFSR_WRONGSIZE_BITS (1) 10362 /* PROTECTED field */ 10363 #define SCS_AFSR_PROTECTED (0x00000004u) 10364 #define SCS_AFSR_PROTECTED_MASK (0x00000004u) 10365 #define SCS_AFSR_PROTECTED_BIT (2) 10366 #define SCS_AFSR_PROTECTED_BITS (1) 10367 /* RESERVED field */ 10368 #define SCS_AFSR_RESERVED (0x00000002u) 10369 #define SCS_AFSR_RESERVED_MASK (0x00000002u) 10370 #define SCS_AFSR_RESERVED_BIT (1) 10371 #define SCS_AFSR_RESERVED_BITS (1) 10372 /* MISSED field */ 10373 #define SCS_AFSR_MISSED (0x00000001u) 10374 #define SCS_AFSR_MISSED_MASK (0x00000001u) 10375 #define SCS_AFSR_MISSED_BIT (0) 10376 #define SCS_AFSR_MISSED_BITS (1) 10377 10378 #define SCS_PFR0 *((volatile int32u *)0xE000ED40u) 10379 #define SCS_PFR0_REG *((volatile int32u *)0xE000ED40u) 10380 #define SCS_PFR0_ADDR (0xE000ED40u) 10381 #define SCS_PFR0_RESET (0x00000030u) 10382 /* FEATURE field */ 10383 #define SCS_PFR0_FEATURE (0xFFFFFFFFu) 10384 #define SCS_PFR0_FEATURE_MASK (0xFFFFFFFFu) 10385 #define SCS_PFR0_FEATURE_BIT (0) 10386 #define SCS_PFR0_FEATURE_BITS (32) 10387 10388 #define SCS_PFR1 *((volatile int32u *)0xE000ED44u) 10389 #define SCS_PFR1_REG *((volatile int32u *)0xE000ED44u) 10390 #define SCS_PFR1_ADDR (0xE000ED44u) 10391 #define SCS_PFR1_RESET (0x00000200u) 10392 /* FEATURE field */ 10393 #define SCS_PFR1_FEATURE (0xFFFFFFFFu) 10394 #define SCS_PFR1_FEATURE_MASK (0xFFFFFFFFu) 10395 #define SCS_PFR1_FEATURE_BIT (0) 10396 #define SCS_PFR1_FEATURE_BITS (32) 10397 10398 #define SCS_DFR0 *((volatile int32u *)0xE000ED48u) 10399 #define SCS_DFR0_REG *((volatile int32u *)0xE000ED48u) 10400 #define SCS_DFR0_ADDR (0xE000ED48u) 10401 #define SCS_DFR0_RESET (0x00100000u) 10402 /* FEATURE field */ 10403 #define SCS_DFR0_FEATURE (0xFFFFFFFFu) 10404 #define SCS_DFR0_FEATURE_MASK (0xFFFFFFFFu) 10405 #define SCS_DFR0_FEATURE_BIT (0) 10406 #define SCS_DFR0_FEATURE_BITS (32) 10407 10408 #define SCS_AFR0 *((volatile int32u *)0xE000ED4Cu) 10409 #define SCS_AFR0_REG *((volatile int32u *)0xE000ED4Cu) 10410 #define SCS_AFR0_ADDR (0xE000ED4Cu) 10411 #define SCS_AFR0_RESET (0x00000000u) 10412 /* FEATURE field */ 10413 #define SCS_AFR0_FEATURE (0xFFFFFFFFu) 10414 #define SCS_AFR0_FEATURE_MASK (0xFFFFFFFFu) 10415 #define SCS_AFR0_FEATURE_BIT (0) 10416 #define SCS_AFR0_FEATURE_BITS (32) 10417 10418 #define SCS_MMFR0 *((volatile int32u *)0xE000ED50u) 10419 #define SCS_MMFR0_REG *((volatile int32u *)0xE000ED50u) 10420 #define SCS_MMFR0_ADDR (0xE000ED50u) 10421 #define SCS_MMFR0_RESET (0x00000030u) 10422 /* FEATURE field */ 10423 #define SCS_MMFR0_FEATURE (0xFFFFFFFFu) 10424 #define SCS_MMFR0_FEATURE_MASK (0xFFFFFFFFu) 10425 #define SCS_MMFR0_FEATURE_BIT (0) 10426 #define SCS_MMFR0_FEATURE_BITS (32) 10427 10428 #define SCS_MMFR1 *((volatile int32u *)0xE000ED54u) 10429 #define SCS_MMFR1_REG *((volatile int32u *)0xE000ED54u) 10430 #define SCS_MMFR1_ADDR (0xE000ED54u) 10431 #define SCS_MMFR1_RESET (0x00000000u) 10432 /* FEATURE field */ 10433 #define SCS_MMFR1_FEATURE (0xFFFFFFFFu) 10434 #define SCS_MMFR1_FEATURE_MASK (0xFFFFFFFFu) 10435 #define SCS_MMFR1_FEATURE_BIT (0) 10436 #define SCS_MMFR1_FEATURE_BITS (32) 10437 10438 #define SCS_MMFR2 *((volatile int32u *)0xE000ED58u) 10439 #define SCS_MMFR2_REG *((volatile int32u *)0xE000ED58u) 10440 #define SCS_MMFR2_ADDR (0xE000ED58u) 10441 #define SCS_MMFR2_RESET (0x00000000u) 10442 /* FEATURE field */ 10443 #define SCS_MMFR2_FEATURE (0xFFFFFFFFu) 10444 #define SCS_MMFR2_FEATURE_MASK (0xFFFFFFFFu) 10445 #define SCS_MMFR2_FEATURE_BIT (0) 10446 #define SCS_MMFR2_FEATURE_BITS (32) 10447 10448 #define SCS_MMFR3 *((volatile int32u *)0xE000ED5Cu) 10449 #define SCS_MMFR3_REG *((volatile int32u *)0xE000ED5Cu) 10450 #define SCS_MMFR3_ADDR (0xE000ED5Cu) 10451 #define SCS_MMFR3_RESET (0x00000000u) 10452 /* FEATURE field */ 10453 #define SCS_MMFR3_FEATURE (0xFFFFFFFFu) 10454 #define SCS_MMFR3_FEATURE_MASK (0xFFFFFFFFu) 10455 #define SCS_MMFR3_FEATURE_BIT (0) 10456 #define SCS_MMFR3_FEATURE_BITS (32) 10457 10458 #define SCS_ISAFR0 *((volatile int32u *)0xE000ED60u) 10459 #define SCS_ISAFR0_REG *((volatile int32u *)0xE000ED60u) 10460 #define SCS_ISAFR0_ADDR (0xE000ED60u) 10461 #define SCS_ISAFR0_RESET (0x01141110u) 10462 /* FEATURE field */ 10463 #define SCS_ISAFR0_FEATURE (0xFFFFFFFFu) 10464 #define SCS_ISAFR0_FEATURE_MASK (0xFFFFFFFFu) 10465 #define SCS_ISAFR0_FEATURE_BIT (0) 10466 #define SCS_ISAFR0_FEATURE_BITS (32) 10467 10468 #define SCS_ISAFR1 *((volatile int32u *)0xE000ED64u) 10469 #define SCS_ISAFR1_REG *((volatile int32u *)0xE000ED64u) 10470 #define SCS_ISAFR1_ADDR (0xE000ED64u) 10471 #define SCS_ISAFR1_RESET (0x02111000u) 10472 /* FEATURE field */ 10473 #define SCS_ISAFR1_FEATURE (0xFFFFFFFFu) 10474 #define SCS_ISAFR1_FEATURE_MASK (0xFFFFFFFFu) 10475 #define SCS_ISAFR1_FEATURE_BIT (0) 10476 #define SCS_ISAFR1_FEATURE_BITS (32) 10477 10478 #define SCS_ISAFR2 *((volatile int32u *)0xE000ED68u) 10479 #define SCS_ISAFR2_REG *((volatile int32u *)0xE000ED68u) 10480 #define SCS_ISAFR2_ADDR (0xE000ED68u) 10481 #define SCS_ISAFR2_RESET (0x21112231u) 10482 /* FEATURE field */ 10483 #define SCS_ISAFR2_FEATURE (0xFFFFFFFFu) 10484 #define SCS_ISAFR2_FEATURE_MASK (0xFFFFFFFFu) 10485 #define SCS_ISAFR2_FEATURE_BIT (0) 10486 #define SCS_ISAFR2_FEATURE_BITS (32) 10487 10488 #define SCS_ISAFR3 *((volatile int32u *)0xE000ED6Cu) 10489 #define SCS_ISAFR3_REG *((volatile int32u *)0xE000ED6Cu) 10490 #define SCS_ISAFR3_ADDR (0xE000ED6Cu) 10491 #define SCS_ISAFR3_RESET (0x11111110u) 10492 /* FEATURE field */ 10493 #define SCS_ISAFR3_FEATURE (0xFFFFFFFFu) 10494 #define SCS_ISAFR3_FEATURE_MASK (0xFFFFFFFFu) 10495 #define SCS_ISAFR3_FEATURE_BIT (0) 10496 #define SCS_ISAFR3_FEATURE_BITS (32) 10497 10498 #define SCS_ISAFR4 *((volatile int32u *)0xE000ED70u) 10499 #define SCS_ISAFR4_REG *((volatile int32u *)0xE000ED70u) 10500 #define SCS_ISAFR4_ADDR (0xE000ED70u) 10501 #define SCS_ISAFR4_RESET (0x01310102u) 10502 /* FEATURE field */ 10503 #define SCS_ISAFR4_FEATURE (0xFFFFFFFFu) 10504 #define SCS_ISAFR4_FEATURE_MASK (0xFFFFFFFFu) 10505 #define SCS_ISAFR4_FEATURE_BIT (0) 10506 #define SCS_ISAFR4_FEATURE_BITS (32) 10507 10508 #define MPU_TYPE *((volatile int32u *)0xE000ED90u) 10509 #define MPU_TYPE_REG *((volatile int32u *)0xE000ED90u) 10510 #define MPU_TYPE_ADDR (0xE000ED90u) 10511 #define MPU_TYPE_RESET (0x00000800u) 10512 /* IREGION field */ 10513 #define MPU_TYPE_IREGION (0x00FF0000u) 10514 #define MPU_TYPE_IREGION_MASK (0x00FF0000u) 10515 #define MPU_TYPE_IREGION_BIT (16) 10516 #define MPU_TYPE_IREGION_BITS (8) 10517 /* DREGION field */ 10518 #define MPU_TYPE_DREGION (0x0000FF00u) 10519 #define MPU_TYPE_DREGION_MASK (0x0000FF00u) 10520 #define MPU_TYPE_DREGION_BIT (8) 10521 #define MPU_TYPE_DREGION_BITS (8) 10522 10523 #define MPU_CTRL *((volatile int32u *)0xE000ED94u) 10524 #define MPU_CTRL_REG *((volatile int32u *)0xE000ED94u) 10525 #define MPU_CTRL_ADDR (0xE000ED94u) 10526 #define MPU_CTRL_RESET (0x00000000u) 10527 /* PRIVDEFENA field */ 10528 #define MPU_CTRL_PRIVDEFENA (0x00000004u) 10529 #define MPU_CTRL_PRIVDEFENA_MASK (0x00000004u) 10530 #define MPU_CTRL_PRIVDEFENA_BIT (2) 10531 #define MPU_CTRL_PRIVDEFENA_BITS (1) 10532 /* HFNMIENA field */ 10533 #define MPU_CTRL_HFNMIENA (0x00000002u) 10534 #define MPU_CTRL_HFNMIENA_MASK (0x00000002u) 10535 #define MPU_CTRL_HFNMIENA_BIT (1) 10536 #define MPU_CTRL_HFNMIENA_BITS (1) 10537 /* ENABLE field */ 10538 #define MPU_CTRL_ENABLE (0x00000001u) 10539 #define MPU_CTRL_ENABLE_MASK (0x00000001u) 10540 #define MPU_CTRL_ENABLE_BIT (0) 10541 #define MPU_CTRL_ENABLE_BITS (1) 10542 10543 #define MPU_REGION *((volatile int32u *)0xE000ED98u) 10544 #define MPU_REGION_REG *((volatile int32u *)0xE000ED98u) 10545 #define MPU_REGION_ADDR (0xE000ED98u) 10546 #define MPU_REGION_RESET (0x00000000u) 10547 /* REGION field */ 10548 #define MPU_REGION_REGION (0x000000FFu) 10549 #define MPU_REGION_REGION_MASK (0x000000FFu) 10550 #define MPU_REGION_REGION_BIT (0) 10551 #define MPU_REGION_REGION_BITS (8) 10552 10553 #define MPU_BASE *((volatile int32u *)0xE000ED9Cu) 10554 #define MPU_BASE_REG *((volatile int32u *)0xE000ED9Cu) 10555 #define MPU_BASE_ADDR (0xE000ED9Cu) 10556 #define MPU_BASE_RESET (0x00000000u) 10557 /* ADDRESS field */ 10558 #define MPU_BASE_ADDRESS (0xFFFFFFE0u) 10559 #define MPU_BASE_ADDRESS_MASK (0xFFFFFFE0u) 10560 #define MPU_BASE_ADDRESS_BIT (5) 10561 #define MPU_BASE_ADDRESS_BITS (27) 10562 /* VALID field */ 10563 #define MPU_BASE_VALID (0x00000010u) 10564 #define MPU_BASE_VALID_MASK (0x00000010u) 10565 #define MPU_BASE_VALID_BIT (4) 10566 #define MPU_BASE_VALID_BITS (1) 10567 /* REGION field */ 10568 #define MPU_BASE_REGION (0x0000000Fu) 10569 #define MPU_BASE_REGION_MASK (0x0000000Fu) 10570 #define MPU_BASE_REGION_BIT (0) 10571 #define MPU_BASE_REGION_BITS (4) 10572 10573 #define MPU_ATTR *((volatile int32u *)0xE000EDA0u) 10574 #define MPU_ATTR_REG *((volatile int32u *)0xE000EDA0u) 10575 #define MPU_ATTR_ADDR (0xE000EDA0u) 10576 #define MPU_ATTR_RESET (0x00000000u) 10577 /* XN field */ 10578 #define MPU_ATTR_XN (0x10000000u) 10579 #define MPU_ATTR_XN_MASK (0x10000000u) 10580 #define MPU_ATTR_XN_BIT (28) 10581 #define MPU_ATTR_XN_BITS (1) 10582 /* AP field */ 10583 #define MPU_ATTR_AP (0x07000000u) 10584 #define MPU_ATTR_AP_MASK (0x07000000u) 10585 #define MPU_ATTR_AP_BIT (24) 10586 #define MPU_ATTR_AP_BITS (3) 10587 /* TEX field */ 10588 #define MPU_ATTR_TEX (0x00380000u) 10589 #define MPU_ATTR_TEX_MASK (0x00380000u) 10590 #define MPU_ATTR_TEX_BIT (19) 10591 #define MPU_ATTR_TEX_BITS (3) 10592 /* S field */ 10593 #define MPU_ATTR_S (0x00040000u) 10594 #define MPU_ATTR_S_MASK (0x00040000u) 10595 #define MPU_ATTR_S_BIT (18) 10596 #define MPU_ATTR_S_BITS (1) 10597 /* C field */ 10598 #define MPU_ATTR_C (0x00020000u) 10599 #define MPU_ATTR_C_MASK (0x00020000u) 10600 #define MPU_ATTR_C_BIT (17) 10601 #define MPU_ATTR_C_BITS (1) 10602 /* B field */ 10603 #define MPU_ATTR_B (0x00010000u) 10604 #define MPU_ATTR_B_MASK (0x00010000u) 10605 #define MPU_ATTR_B_BIT (16) 10606 #define MPU_ATTR_B_BITS (1) 10607 /* SRD field */ 10608 #define MPU_ATTR_SRD (0x0000FF00u) 10609 #define MPU_ATTR_SRD_MASK (0x0000FF00u) 10610 #define MPU_ATTR_SRD_BIT (8) 10611 #define MPU_ATTR_SRD_BITS (8) 10612 /* SIZE field */ 10613 #define MPU_ATTR_SIZE (0x0000003Eu) 10614 #define MPU_ATTR_SIZE_MASK (0x0000003Eu) 10615 #define MPU_ATTR_SIZE_BIT (1) 10616 #define MPU_ATTR_SIZE_BITS (5) 10617 /* ENABLE field */ 10618 #define MPU_ATTR_ENABLE (0x00000001u) 10619 #define MPU_ATTR_ENABLE_MASK (0x00000001u) 10620 #define MPU_ATTR_ENABLE_BIT (0) 10621 #define MPU_ATTR_ENABLE_BITS (1) 10622 10623 #define MPU_BASE1 *((volatile int32u *)0xE000EDA4u) 10624 #define MPU_BASE1_REG *((volatile int32u *)0xE000EDA4u) 10625 #define MPU_BASE1_ADDR (0xE000EDA4u) 10626 #define MPU_BASE1_RESET (0x00000000u) 10627 /* ADDRESS field */ 10628 #define MPU_BASE1_ADDRESS (0xFFFFFFE0u) 10629 #define MPU_BASE1_ADDRESS_MASK (0xFFFFFFE0u) 10630 #define MPU_BASE1_ADDRESS_BIT (5) 10631 #define MPU_BASE1_ADDRESS_BITS (27) 10632 /* VALID field */ 10633 #define MPU_BASE1_VALID (0x00000010u) 10634 #define MPU_BASE1_VALID_MASK (0x00000010u) 10635 #define MPU_BASE1_VALID_BIT (4) 10636 #define MPU_BASE1_VALID_BITS (1) 10637 /* REGION field */ 10638 #define MPU_BASE1_REGION (0x0000000Fu) 10639 #define MPU_BASE1_REGION_MASK (0x0000000Fu) 10640 #define MPU_BASE1_REGION_BIT (0) 10641 #define MPU_BASE1_REGION_BITS (4) 10642 10643 #define MPU_ATTR1 *((volatile int32u *)0xE000EDA8u) 10644 #define MPU_ATTR1_REG *((volatile int32u *)0xE000EDA8u) 10645 #define MPU_ATTR1_ADDR (0xE000EDA8u) 10646 #define MPU_ATTR1_RESET (0x00000000u) 10647 /* XN field */ 10648 #define MPU_ATTR1_XN (0x10000000u) 10649 #define MPU_ATTR1_XN_MASK (0x10000000u) 10650 #define MPU_ATTR1_XN_BIT (28) 10651 #define MPU_ATTR1_XN_BITS (1) 10652 /* AP field */ 10653 #define MPU_ATTR1_AP (0x07000000u) 10654 #define MPU_ATTR1_AP_MASK (0x07000000u) 10655 #define MPU_ATTR1_AP_BIT (24) 10656 #define MPU_ATTR1_AP_BITS (3) 10657 /* TEX field */ 10658 #define MPU_ATTR1_TEX (0x00380000u) 10659 #define MPU_ATTR1_TEX_MASK (0x00380000u) 10660 #define MPU_ATTR1_TEX_BIT (19) 10661 #define MPU_ATTR1_TEX_BITS (3) 10662 /* S field */ 10663 #define MPU_ATTR1_S (0x00040000u) 10664 #define MPU_ATTR1_S_MASK (0x00040000u) 10665 #define MPU_ATTR1_S_BIT (18) 10666 #define MPU_ATTR1_S_BITS (1) 10667 /* C field */ 10668 #define MPU_ATTR1_C (0x00020000u) 10669 #define MPU_ATTR1_C_MASK (0x00020000u) 10670 #define MPU_ATTR1_C_BIT (17) 10671 #define MPU_ATTR1_C_BITS (1) 10672 /* B field */ 10673 #define MPU_ATTR1_B (0x00010000u) 10674 #define MPU_ATTR1_B_MASK (0x00010000u) 10675 #define MPU_ATTR1_B_BIT (16) 10676 #define MPU_ATTR1_B_BITS (1) 10677 /* SRD field */ 10678 #define MPU_ATTR1_SRD (0x0000FF00u) 10679 #define MPU_ATTR1_SRD_MASK (0x0000FF00u) 10680 #define MPU_ATTR1_SRD_BIT (8) 10681 #define MPU_ATTR1_SRD_BITS (8) 10682 /* SIZE field */ 10683 #define MPU_ATTR1_SIZE (0x0000003Eu) 10684 #define MPU_ATTR1_SIZE_MASK (0x0000003Eu) 10685 #define MPU_ATTR1_SIZE_BIT (1) 10686 #define MPU_ATTR1_SIZE_BITS (5) 10687 /* ENABLE field */ 10688 #define MPU_ATTR1_ENABLE (0x00000001u) 10689 #define MPU_ATTR1_ENABLE_MASK (0x00000001u) 10690 #define MPU_ATTR1_ENABLE_BIT (0) 10691 #define MPU_ATTR1_ENABLE_BITS (1) 10692 10693 #define MPU_BASE2 *((volatile int32u *)0xE000EDACu) 10694 #define MPU_BASE2_REG *((volatile int32u *)0xE000EDACu) 10695 #define MPU_BASE2_ADDR (0xE000EDACu) 10696 #define MPU_BASE2_RESET (0x00000000u) 10697 /* ADDRESS field */ 10698 #define MPU_BASE2_ADDRESS (0xFFFFFFE0u) 10699 #define MPU_BASE2_ADDRESS_MASK (0xFFFFFFE0u) 10700 #define MPU_BASE2_ADDRESS_BIT (5) 10701 #define MPU_BASE2_ADDRESS_BITS (27) 10702 /* VALID field */ 10703 #define MPU_BASE2_VALID (0x00000010u) 10704 #define MPU_BASE2_VALID_MASK (0x00000010u) 10705 #define MPU_BASE2_VALID_BIT (4) 10706 #define MPU_BASE2_VALID_BITS (1) 10707 /* REGION field */ 10708 #define MPU_BASE2_REGION (0x0000000Fu) 10709 #define MPU_BASE2_REGION_MASK (0x0000000Fu) 10710 #define MPU_BASE2_REGION_BIT (0) 10711 #define MPU_BASE2_REGION_BITS (4) 10712 10713 #define MPU_ATTR2 *((volatile int32u *)0xE000EDB0u) 10714 #define MPU_ATTR2_REG *((volatile int32u *)0xE000EDB0u) 10715 #define MPU_ATTR2_ADDR (0xE000EDB0u) 10716 #define MPU_ATTR2_RESET (0x00000000u) 10717 /* XN field */ 10718 #define MPU_ATTR2_XN (0x10000000u) 10719 #define MPU_ATTR2_XN_MASK (0x10000000u) 10720 #define MPU_ATTR2_XN_BIT (28) 10721 #define MPU_ATTR2_XN_BITS (1) 10722 /* AP field */ 10723 #define MPU_ATTR2_AP (0x1F000000u) 10724 #define MPU_ATTR2_AP_MASK (0x1F000000u) 10725 #define MPU_ATTR2_AP_BIT (24) 10726 #define MPU_ATTR2_AP_BITS (5) 10727 /* TEX field */ 10728 #define MPU_ATTR2_TEX (0x00380000u) 10729 #define MPU_ATTR2_TEX_MASK (0x00380000u) 10730 #define MPU_ATTR2_TEX_BIT (19) 10731 #define MPU_ATTR2_TEX_BITS (3) 10732 /* S field */ 10733 #define MPU_ATTR2_S (0x00040000u) 10734 #define MPU_ATTR2_S_MASK (0x00040000u) 10735 #define MPU_ATTR2_S_BIT (18) 10736 #define MPU_ATTR2_S_BITS (1) 10737 /* C field */ 10738 #define MPU_ATTR2_C (0x00020000u) 10739 #define MPU_ATTR2_C_MASK (0x00020000u) 10740 #define MPU_ATTR2_C_BIT (17) 10741 #define MPU_ATTR2_C_BITS (1) 10742 /* B field */ 10743 #define MPU_ATTR2_B (0x00010000u) 10744 #define MPU_ATTR2_B_MASK (0x00010000u) 10745 #define MPU_ATTR2_B_BIT (16) 10746 #define MPU_ATTR2_B_BITS (1) 10747 /* SRD field */ 10748 #define MPU_ATTR2_SRD (0x0000FF00u) 10749 #define MPU_ATTR2_SRD_MASK (0x0000FF00u) 10750 #define MPU_ATTR2_SRD_BIT (8) 10751 #define MPU_ATTR2_SRD_BITS (8) 10752 /* SIZE field */ 10753 #define MPU_ATTR2_SIZE (0x0000003Eu) 10754 #define MPU_ATTR2_SIZE_MASK (0x0000003Eu) 10755 #define MPU_ATTR2_SIZE_BIT (1) 10756 #define MPU_ATTR2_SIZE_BITS (5) 10757 /* ENABLE field */ 10758 #define MPU_ATTR2_ENABLE (0x00000003u) 10759 #define MPU_ATTR2_ENABLE_MASK (0x00000003u) 10760 #define MPU_ATTR2_ENABLE_BIT (0) 10761 #define MPU_ATTR2_ENABLE_BITS (2) 10762 10763 #define MPU_BASE3 *((volatile int32u *)0xE000EDB4u) 10764 #define MPU_BASE3_REG *((volatile int32u *)0xE000EDB4u) 10765 #define MPU_BASE3_ADDR (0xE000EDB4u) 10766 #define MPU_BASE3_RESET (0x00000000u) 10767 /* ADDRESS field */ 10768 #define MPU_BASE3_ADDRESS (0xFFFFFFE0u) 10769 #define MPU_BASE3_ADDRESS_MASK (0xFFFFFFE0u) 10770 #define MPU_BASE3_ADDRESS_BIT (5) 10771 #define MPU_BASE3_ADDRESS_BITS (27) 10772 /* VALID field */ 10773 #define MPU_BASE3_VALID (0x00000010u) 10774 #define MPU_BASE3_VALID_MASK (0x00000010u) 10775 #define MPU_BASE3_VALID_BIT (4) 10776 #define MPU_BASE3_VALID_BITS (1) 10777 /* REGION field */ 10778 #define MPU_BASE3_REGION (0x0000000Fu) 10779 #define MPU_BASE3_REGION_MASK (0x0000000Fu) 10780 #define MPU_BASE3_REGION_BIT (0) 10781 #define MPU_BASE3_REGION_BITS (4) 10782 10783 #define MPU_ATTR3 *((volatile int32u *)0xE000EDBCu) 10784 #define MPU_ATTR3_REG *((volatile int32u *)0xE000EDBCu) 10785 #define MPU_ATTR3_ADDR (0xE000EDBCu) 10786 #define MPU_ATTR3_RESET (0x00000000u) 10787 /* XN field */ 10788 #define MPU_ATTR3_XN (0x10000000u) 10789 #define MPU_ATTR3_XN_MASK (0x10000000u) 10790 #define MPU_ATTR3_XN_BIT (28) 10791 #define MPU_ATTR3_XN_BITS (1) 10792 /* AP field */ 10793 #define MPU_ATTR3_AP (0x1F000000u) 10794 #define MPU_ATTR3_AP_MASK (0x1F000000u) 10795 #define MPU_ATTR3_AP_BIT (24) 10796 #define MPU_ATTR3_AP_BITS (5) 10797 /* TEX field */ 10798 #define MPU_ATTR3_TEX (0x00380000u) 10799 #define MPU_ATTR3_TEX_MASK (0x00380000u) 10800 #define MPU_ATTR3_TEX_BIT (19) 10801 #define MPU_ATTR3_TEX_BITS (3) 10802 /* S field */ 10803 #define MPU_ATTR3_S (0x00040000u) 10804 #define MPU_ATTR3_S_MASK (0x00040000u) 10805 #define MPU_ATTR3_S_BIT (18) 10806 #define MPU_ATTR3_S_BITS (1) 10807 /* C field */ 10808 #define MPU_ATTR3_C (0x00020000u) 10809 #define MPU_ATTR3_C_MASK (0x00020000u) 10810 #define MPU_ATTR3_C_BIT (17) 10811 #define MPU_ATTR3_C_BITS (1) 10812 /* B field */ 10813 #define MPU_ATTR3_B (0x00010000u) 10814 #define MPU_ATTR3_B_MASK (0x00010000u) 10815 #define MPU_ATTR3_B_BIT (16) 10816 #define MPU_ATTR3_B_BITS (1) 10817 /* SRD field */ 10818 #define MPU_ATTR3_SRD (0x0000FF00u) 10819 #define MPU_ATTR3_SRD_MASK (0x0000FF00u) 10820 #define MPU_ATTR3_SRD_BIT (8) 10821 #define MPU_ATTR3_SRD_BITS (8) 10822 /* SIZE field */ 10823 #define MPU_ATTR3_SIZE (0x0000003Eu) 10824 #define MPU_ATTR3_SIZE_MASK (0x0000003Eu) 10825 #define MPU_ATTR3_SIZE_BIT (1) 10826 #define MPU_ATTR3_SIZE_BITS (5) 10827 /* ENABLE field */ 10828 #define MPU_ATTR3_ENABLE (0x00000003u) 10829 #define MPU_ATTR3_ENABLE_MASK (0x00000003u) 10830 #define MPU_ATTR3_ENABLE_BIT (0) 10831 #define MPU_ATTR3_ENABLE_BITS (2) 10832 10833 #define DEBUG_HCSR *((volatile int32u *)0xE000EDF0u) 10834 #define DEBUG_HCSR_REG *((volatile int32u *)0xE000EDF0u) 10835 #define DEBUG_HCSR_ADDR (0xE000EDF0u) 10836 #define DEBUG_HCSR_RESET (0x00000000u) 10837 /* S_RESET_ST field */ 10838 #define DEBUG_HCSR_S_RESET_ST (0x02000000u) 10839 #define DEBUG_HCSR_S_RESET_ST_MASK (0x02000000u) 10840 #define DEBUG_HCSR_S_RESET_ST_BIT (25) 10841 #define DEBUG_HCSR_S_RESET_ST_BITS (1) 10842 /* S_RETIRE_ST field */ 10843 #define DEBUG_HCSR_S_RETIRE_ST (0x01000000u) 10844 #define DEBUG_HCSR_S_RETIRE_ST_MASK (0x01000000u) 10845 #define DEBUG_HCSR_S_RETIRE_ST_BIT (24) 10846 #define DEBUG_HCSR_S_RETIRE_ST_BITS (1) 10847 /* S_LOCKUP field */ 10848 #define DEBUG_HCSR_S_LOCKUP (0x00080000u) 10849 #define DEBUG_HCSR_S_LOCKUP_MASK (0x00080000u) 10850 #define DEBUG_HCSR_S_LOCKUP_BIT (19) 10851 #define DEBUG_HCSR_S_LOCKUP_BITS (1) 10852 /* S_SLEEP field */ 10853 #define DEBUG_HCSR_S_SLEEP (0x00040000u) 10854 #define DEBUG_HCSR_S_SLEEP_MASK (0x00040000u) 10855 #define DEBUG_HCSR_S_SLEEP_BIT (18) 10856 #define DEBUG_HCSR_S_SLEEP_BITS (1) 10857 /* S_HALT field */ 10858 #define DEBUG_HCSR_S_HALT (0x00020000u) 10859 #define DEBUG_HCSR_S_HALT_MASK (0x00020000u) 10860 #define DEBUG_HCSR_S_HALT_BIT (17) 10861 #define DEBUG_HCSR_S_HALT_BITS (1) 10862 /* S_REGRDY field */ 10863 #define DEBUG_HCSR_S_REGRDY (0x00010000u) 10864 #define DEBUG_HCSR_S_REGRDY_MASK (0x00010000u) 10865 #define DEBUG_HCSR_S_REGRDY_BIT (16) 10866 #define DEBUG_HCSR_S_REGRDY_BITS (1) 10867 /* DBGKEY field */ 10868 #define DEBUG_HCSR_DBGKEY (0xFFFF0000u) 10869 #define DEBUG_HCSR_DBGKEY_MASK (0xFFFF0000u) 10870 #define DEBUG_HCSR_DBGKEY_BIT (16) 10871 #define DEBUG_HCSR_DBGKEY_BITS (16) 10872 /* C_SNAPSTALL field */ 10873 #define DEBUG_HCSR_C_SNAPSTALL (0x00000020u) 10874 #define DEBUG_HCSR_C_SNAPSTALL_MASK (0x00000020u) 10875 #define DEBUG_HCSR_C_SNAPSTALL_BIT (5) 10876 #define DEBUG_HCSR_C_SNAPSTALL_BITS (1) 10877 /* C_MASKINTS field */ 10878 #define DEBUG_HCSR_C_MASKINTS (0x00000008u) 10879 #define DEBUG_HCSR_C_MASKINTS_MASK (0x00000008u) 10880 #define DEBUG_HCSR_C_MASKINTS_BIT (3) 10881 #define DEBUG_HCSR_C_MASKINTS_BITS (1) 10882 /* C_STEP field */ 10883 #define DEBUG_HCSR_C_STEP (0x00000004u) 10884 #define DEBUG_HCSR_C_STEP_MASK (0x00000004u) 10885 #define DEBUG_HCSR_C_STEP_BIT (2) 10886 #define DEBUG_HCSR_C_STEP_BITS (1) 10887 /* C_HALT field */ 10888 #define DEBUG_HCSR_C_HALT (0x00000002u) 10889 #define DEBUG_HCSR_C_HALT_MASK (0x00000002u) 10890 #define DEBUG_HCSR_C_HALT_BIT (1) 10891 #define DEBUG_HCSR_C_HALT_BITS (1) 10892 /* C_DEBUGEN field */ 10893 #define DEBUG_HCSR_C_DEBUGEN (0x00000001u) 10894 #define DEBUG_HCSR_C_DEBUGEN_MASK (0x00000001u) 10895 #define DEBUG_HCSR_C_DEBUGEN_BIT (0) 10896 #define DEBUG_HCSR_C_DEBUGEN_BITS (1) 10897 10898 #define DEBUG_CRSR *((volatile int32u *)0xE000EDF4u) 10899 #define DEBUG_CRSR_REG *((volatile int32u *)0xE000EDF4u) 10900 #define DEBUG_CRSR_ADDR (0xE000EDF4u) 10901 #define DEBUG_CRSR_RESET (0x00000000u) 10902 /* REGWnR field */ 10903 #define DEBUG_CRSR_REGWnR (0x00010000u) 10904 #define DEBUG_CRSR_REGWnR_MASK (0x00010000u) 10905 #define DEBUG_CRSR_REGWnR_BIT (16) 10906 #define DEBUG_CRSR_REGWnR_BITS (1) 10907 /* REGSEL field */ 10908 #define DEBUG_CRSR_REGSEL (0x0000001Fu) 10909 #define DEBUG_CRSR_REGSEL_MASK (0x0000001Fu) 10910 #define DEBUG_CRSR_REGSEL_BIT (0) 10911 #define DEBUG_CRSR_REGSEL_BITS (5) 10912 10913 #define DEBUG_CRDR *((volatile int32u *)0xE000EDF8u) 10914 #define DEBUG_CRDR_REG *((volatile int32u *)0xE000EDF8u) 10915 #define DEBUG_CRDR_ADDR (0xE000EDF8u) 10916 #define DEBUG_CRDR_RESET (0x00000000u) 10917 /* DBGTMP field */ 10918 #define DEBUG_CRDR_DBGTMP (0xFFFFFFFFu) 10919 #define DEBUG_CRDR_DBGTMP_MASK (0xFFFFFFFFu) 10920 #define DEBUG_CRDR_DBGTMP_BIT (0) 10921 #define DEBUG_CRDR_DBGTMP_BITS (32) 10922 10923 #define DEBUG_EMCR *((volatile int32u *)0xE000EDFCu) 10924 #define DEBUG_EMCR_REG *((volatile int32u *)0xE000EDFCu) 10925 #define DEBUG_EMCR_ADDR (0xE000EDFCu) 10926 #define DEBUG_EMCR_RESET (0x00000000u) 10927 /* TRCENA field */ 10928 #define DEBUG_EMCR_TRCENA (0x01000000u) 10929 #define DEBUG_EMCR_TRCENA_MASK (0x01000000u) 10930 #define DEBUG_EMCR_TRCENA_BIT (24) 10931 #define DEBUG_EMCR_TRCENA_BITS (1) 10932 /* MON_REQ field */ 10933 #define DEBUG_EMCR_MON_REQ (0x00080000u) 10934 #define DEBUG_EMCR_MON_REQ_MASK (0x00080000u) 10935 #define DEBUG_EMCR_MON_REQ_BIT (19) 10936 #define DEBUG_EMCR_MON_REQ_BITS (1) 10937 /* MON_STEP field */ 10938 #define DEBUG_EMCR_MON_STEP (0x00040000u) 10939 #define DEBUG_EMCR_MON_STEP_MASK (0x00040000u) 10940 #define DEBUG_EMCR_MON_STEP_BIT (18) 10941 #define DEBUG_EMCR_MON_STEP_BITS (1) 10942 /* MON_PEND field */ 10943 #define DEBUG_EMCR_MON_PEND (0x00020000u) 10944 #define DEBUG_EMCR_MON_PEND_MASK (0x00020000u) 10945 #define DEBUG_EMCR_MON_PEND_BIT (17) 10946 #define DEBUG_EMCR_MON_PEND_BITS (1) 10947 /* MON_EN field */ 10948 #define DEBUG_EMCR_MON_EN (0x00010000u) 10949 #define DEBUG_EMCR_MON_EN_MASK (0x00010000u) 10950 #define DEBUG_EMCR_MON_EN_BIT (16) 10951 #define DEBUG_EMCR_MON_EN_BITS (1) 10952 /* VC_HARDERR field */ 10953 #define DEBUG_EMCR_VC_HARDERR (0x00000400u) 10954 #define DEBUG_EMCR_VC_HARDERR_MASK (0x00000400u) 10955 #define DEBUG_EMCR_VC_HARDERR_BIT (10) 10956 #define DEBUG_EMCR_VC_HARDERR_BITS (1) 10957 /* VC_INTERR field */ 10958 #define DEBUG_EMCR_VC_INTERR (0x00000200u) 10959 #define DEBUG_EMCR_VC_INTERR_MASK (0x00000200u) 10960 #define DEBUG_EMCR_VC_INTERR_BIT (9) 10961 #define DEBUG_EMCR_VC_INTERR_BITS (1) 10962 /* VC_BUSERR field */ 10963 #define DEBUG_EMCR_VC_BUSERR (0x00000100u) 10964 #define DEBUG_EMCR_VC_BUSERR_MASK (0x00000100u) 10965 #define DEBUG_EMCR_VC_BUSERR_BIT (8) 10966 #define DEBUG_EMCR_VC_BUSERR_BITS (1) 10967 /* VC_STATERR field */ 10968 #define DEBUG_EMCR_VC_STATERR (0x00000080u) 10969 #define DEBUG_EMCR_VC_STATERR_MASK (0x00000080u) 10970 #define DEBUG_EMCR_VC_STATERR_BIT (7) 10971 #define DEBUG_EMCR_VC_STATERR_BITS (1) 10972 /* VC_CHKERR field */ 10973 #define DEBUG_EMCR_VC_CHKERR (0x00000040u) 10974 #define DEBUG_EMCR_VC_CHKERR_MASK (0x00000040u) 10975 #define DEBUG_EMCR_VC_CHKERR_BIT (6) 10976 #define DEBUG_EMCR_VC_CHKERR_BITS (1) 10977 /* VC_NOCPERR field */ 10978 #define DEBUG_EMCR_VC_NOCPERR (0x00000020u) 10979 #define DEBUG_EMCR_VC_NOCPERR_MASK (0x00000020u) 10980 #define DEBUG_EMCR_VC_NOCPERR_BIT (5) 10981 #define DEBUG_EMCR_VC_NOCPERR_BITS (1) 10982 /* VC_MMERR field */ 10983 #define DEBUG_EMCR_VC_MMERR (0x00000010u) 10984 #define DEBUG_EMCR_VC_MMERR_MASK (0x00000010u) 10985 #define DEBUG_EMCR_VC_MMERR_BIT (4) 10986 #define DEBUG_EMCR_VC_MMERR_BITS (1) 10987 /* VC_CORERESET field */ 10988 #define DEBUG_EMCR_VC_CORERESET (0x00000001u) 10989 #define DEBUG_EMCR_VC_CORERESET_MASK (0x00000001u) 10990 #define DEBUG_EMCR_VC_CORERESET_BIT (0) 10991 #define DEBUG_EMCR_VC_CORERESET_BITS (1) 10992 10993 #define NVIC_STIR *((volatile int32u *)0xE000EF00u) 10994 #define NVIC_STIR_REG *((volatile int32u *)0xE000EF00u) 10995 #define NVIC_STIR_ADDR (0xE000EF00u) 10996 #define NVIC_STIR_RESET (0x00000000u) 10997 /* INTID field */ 10998 #define NVIC_STIR_INTID (0x000003FFu) 10999 #define NVIC_STIR_INTID_MASK (0x000003FFu) 11000 #define NVIC_STIR_INTID_BIT (0) 11001 #define NVIC_STIR_INTID_BITS (10) 11002 11003 #define NVIC_PERIPHID4 *((volatile int32u *)0xE000EFD0u) 11004 #define NVIC_PERIPHID4_REG *((volatile int32u *)0xE000EFD0u) 11005 #define NVIC_PERIPHID4_ADDR (0xE000EFD0u) 11006 #define NVIC_PERIPHID4_RESET (0x00000004u) 11007 /* PERIPHID field */ 11008 #define NVIC_PERIPHID4_PERIPHID (0xFFFFFFFFu) 11009 #define NVIC_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) 11010 #define NVIC_PERIPHID4_PERIPHID_BIT (0) 11011 #define NVIC_PERIPHID4_PERIPHID_BITS (32) 11012 11013 #define NVIC_PERIPHID5 *((volatile int32u *)0xE000EFD4u) 11014 #define NVIC_PERIPHID5_REG *((volatile int32u *)0xE000EFD4u) 11015 #define NVIC_PERIPHID5_ADDR (0xE000EFD4u) 11016 #define NVIC_PERIPHID5_RESET (0x00000000u) 11017 /* PERIPHID field */ 11018 #define NVIC_PERIPHID5_PERIPHID (0xFFFFFFFFu) 11019 #define NVIC_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) 11020 #define NVIC_PERIPHID5_PERIPHID_BIT (0) 11021 #define NVIC_PERIPHID5_PERIPHID_BITS (32) 11022 11023 #define NVIC_PERIPHID6 *((volatile int32u *)0xE000EFD8u) 11024 #define NVIC_PERIPHID6_REG *((volatile int32u *)0xE000EFD8u) 11025 #define NVIC_PERIPHID6_ADDR (0xE000EFD8u) 11026 #define NVIC_PERIPHID6_RESET (0x00000000u) 11027 /* PERIPHID field */ 11028 #define NVIC_PERIPHID6_PERIPHID (0xFFFFFFFFu) 11029 #define NVIC_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) 11030 #define NVIC_PERIPHID6_PERIPHID_BIT (0) 11031 #define NVIC_PERIPHID6_PERIPHID_BITS (32) 11032 11033 #define NVIC_PERIPHID7 *((volatile int32u *)0xE000EFDCu) 11034 #define NVIC_PERIPHID7_REG *((volatile int32u *)0xE000EFDCu) 11035 #define NVIC_PERIPHID7_ADDR (0xE000EFDCu) 11036 #define NVIC_PERIPHID7_RESET (0x00000000u) 11037 /* PERIPHID field */ 11038 #define NVIC_PERIPHID7_PERIPHID (0xFFFFFFFFu) 11039 #define NVIC_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) 11040 #define NVIC_PERIPHID7_PERIPHID_BIT (0) 11041 #define NVIC_PERIPHID7_PERIPHID_BITS (32) 11042 11043 #define NVIC_PERIPHID0 *((volatile int32u *)0xE000EFE0u) 11044 #define NVIC_PERIPHID0_REG *((volatile int32u *)0xE000EFE0u) 11045 #define NVIC_PERIPHID0_ADDR (0xE000EFE0u) 11046 #define NVIC_PERIPHID0_RESET (0x00000000u) 11047 /* PERIPHID field */ 11048 #define NVIC_PERIPHID0_PERIPHID (0xFFFFFFFFu) 11049 #define NVIC_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) 11050 #define NVIC_PERIPHID0_PERIPHID_BIT (0) 11051 #define NVIC_PERIPHID0_PERIPHID_BITS (32) 11052 11053 #define NVIC_PERIPHID1 *((volatile int32u *)0xE000EFE4u) 11054 #define NVIC_PERIPHID1_REG *((volatile int32u *)0xE000EFE4u) 11055 #define NVIC_PERIPHID1_ADDR (0xE000EFE4u) 11056 #define NVIC_PERIPHID1_RESET (0x000000B0u) 11057 /* PERIPHID field */ 11058 #define NVIC_PERIPHID1_PERIPHID (0xFFFFFFFFu) 11059 #define NVIC_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) 11060 #define NVIC_PERIPHID1_PERIPHID_BIT (0) 11061 #define NVIC_PERIPHID1_PERIPHID_BITS (32) 11062 11063 #define NVIC_PERIPHID2 *((volatile int32u *)0xE000EFE8u) 11064 #define NVIC_PERIPHID2_REG *((volatile int32u *)0xE000EFE8u) 11065 #define NVIC_PERIPHID2_ADDR (0xE000EFE8u) 11066 #define NVIC_PERIPHID2_RESET (0x0000001Bu) 11067 /* PERIPHID field */ 11068 #define NVIC_PERIPHID2_PERIPHID (0xFFFFFFFFu) 11069 #define NVIC_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) 11070 #define NVIC_PERIPHID2_PERIPHID_BIT (0) 11071 #define NVIC_PERIPHID2_PERIPHID_BITS (32) 11072 11073 #define NVIC_PERIPHID3 *((volatile int32u *)0xE000EFECu) 11074 #define NVIC_PERIPHID3_REG *((volatile int32u *)0xE000EFECu) 11075 #define NVIC_PERIPHID3_ADDR (0xE000EFECu) 11076 #define NVIC_PERIPHID3_RESET (0x00000000u) 11077 /* PERIPHID field */ 11078 #define NVIC_PERIPHID3_PERIPHID (0xFFFFFFFFu) 11079 #define NVIC_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) 11080 #define NVIC_PERIPHID3_PERIPHID_BIT (0) 11081 #define NVIC_PERIPHID3_PERIPHID_BITS (32) 11082 11083 #define NVIC_PCELLID0 *((volatile int32u *)0xE000EFF0u) 11084 #define NVIC_PCELLID0_REG *((volatile int32u *)0xE000EFF0u) 11085 #define NVIC_PCELLID0_ADDR (0xE000EFF0u) 11086 #define NVIC_PCELLID0_RESET (0x0000000Du) 11087 /* PCELLID field */ 11088 #define NVIC_PCELLID0_PCELLID (0xFFFFFFFFu) 11089 #define NVIC_PCELLID0_PCELLID_MASK (0xFFFFFFFFu) 11090 #define NVIC_PCELLID0_PCELLID_BIT (0) 11091 #define NVIC_PCELLID0_PCELLID_BITS (32) 11092 11093 #define NVIC_PCELLID1 *((volatile int32u *)0xE000EFF4u) 11094 #define NVIC_PCELLID1_REG *((volatile int32u *)0xE000EFF4u) 11095 #define NVIC_PCELLID1_ADDR (0xE000EFF4u) 11096 #define NVIC_PCELLID1_RESET (0x000000E0u) 11097 /* PCELLID field */ 11098 #define NVIC_PCELLID1_PCELLID (0xFFFFFFFFu) 11099 #define NVIC_PCELLID1_PCELLID_MASK (0xFFFFFFFFu) 11100 #define NVIC_PCELLID1_PCELLID_BIT (0) 11101 #define NVIC_PCELLID1_PCELLID_BITS (32) 11102 11103 #define NVIC_PCELLID2 *((volatile int32u *)0xE000EFF8u) 11104 #define NVIC_PCELLID2_REG *((volatile int32u *)0xE000EFF8u) 11105 #define NVIC_PCELLID2_ADDR (0xE000EFF8u) 11106 #define NVIC_PCELLID2_RESET (0x00000005u) 11107 /* PCELLID field */ 11108 #define NVIC_PCELLID2_PCELLID (0xFFFFFFFFu) 11109 #define NVIC_PCELLID2_PCELLID_MASK (0xFFFFFFFFu) 11110 #define NVIC_PCELLID2_PCELLID_BIT (0) 11111 #define NVIC_PCELLID2_PCELLID_BITS (32) 11112 11113 #define NVIC_PCELLID3 *((volatile int32u *)0xE000EFFCu) 11114 #define NVIC_PCELLID3_REG *((volatile int32u *)0xE000EFFCu) 11115 #define NVIC_PCELLID3_ADDR (0xE000EFFCu) 11116 #define NVIC_PCELLID3_RESET (0x000000B1u) 11117 /* PCELLID field */ 11118 #define NVIC_PCELLID3_PCELLID (0xFFFFFFFFu) 11119 #define NVIC_PCELLID3_PCELLID_MASK (0xFFFFFFFFu) 11120 #define NVIC_PCELLID3_PCELLID_BIT (0) 11121 #define NVIC_PCELLID3_PCELLID_BITS (32) 11122 11123 /* TPIU block */ 11124 #define DATA_TPIU_BASE (0xE0040000u) 11125 #define DATA_TPIU_END (0xE0040EF8u) 11126 #define DATA_TPIU_SIZE (DATA_TPIU_END - DATA_TPIU_BASE + 1) 11127 11128 #define TPIU_SPS *((volatile int32u *)0xE0040000u) 11129 #define TPIU_SPS_REG *((volatile int32u *)0xE0040000u) 11130 #define TPIU_SPS_ADDR (0xE0040000u) 11131 #define TPIU_SPS_RESET (0x00000000u) 11132 /* SPS_04 field */ 11133 #define TPIU_SPS_SPS_04 (0x00000008u) 11134 #define TPIU_SPS_SPS_04_MASK (0x00000008u) 11135 #define TPIU_SPS_SPS_04_BIT (3) 11136 #define TPIU_SPS_SPS_04_BITS (1) 11137 /* SPS_03 field */ 11138 #define TPIU_SPS_SPS_03 (0x00000004u) 11139 #define TPIU_SPS_SPS_03_MASK (0x00000004u) 11140 #define TPIU_SPS_SPS_03_BIT (2) 11141 #define TPIU_SPS_SPS_03_BITS (1) 11142 /* SPS_02 field */ 11143 #define TPIU_SPS_SPS_02 (0x00000002u) 11144 #define TPIU_SPS_SPS_02_MASK (0x00000002u) 11145 #define TPIU_SPS_SPS_02_BIT (1) 11146 #define TPIU_SPS_SPS_02_BITS (1) 11147 /* SPS_01 field */ 11148 #define TPIU_SPS_SPS_01 (0x00000001u) 11149 #define TPIU_SPS_SPS_01_MASK (0x00000001u) 11150 #define TPIU_SPS_SPS_01_BIT (0) 11151 #define TPIU_SPS_SPS_01_BITS (1) 11152 11153 #define TPIU_CPS *((volatile int32u *)0xE0040004u) 11154 #define TPIU_CPS_REG *((volatile int32u *)0xE0040004u) 11155 #define TPIU_CPS_ADDR (0xE0040004u) 11156 #define TPIU_CPS_RESET (0x00000001u) 11157 /* CPS_04 field */ 11158 #define TPIU_CPS_CPS_04 (0x00000008u) 11159 #define TPIU_CPS_CPS_04_MASK (0x00000008u) 11160 #define TPIU_CPS_CPS_04_BIT (3) 11161 #define TPIU_CPS_CPS_04_BITS (1) 11162 /* CPS_03 field */ 11163 #define TPIU_CPS_CPS_03 (0x00000004u) 11164 #define TPIU_CPS_CPS_03_MASK (0x00000004u) 11165 #define TPIU_CPS_CPS_03_BIT (2) 11166 #define TPIU_CPS_CPS_03_BITS (1) 11167 /* CPS_02 field */ 11168 #define TPIU_CPS_CPS_02 (0x00000002u) 11169 #define TPIU_CPS_CPS_02_MASK (0x00000002u) 11170 #define TPIU_CPS_CPS_02_BIT (1) 11171 #define TPIU_CPS_CPS_02_BITS (1) 11172 /* CPS_01 field */ 11173 #define TPIU_CPS_CPS_01 (0x00000001u) 11174 #define TPIU_CPS_CPS_01_MASK (0x00000001u) 11175 #define TPIU_CPS_CPS_01_BIT (0) 11176 #define TPIU_CPS_CPS_01_BITS (1) 11177 11178 #define TPIU_COSD *((volatile int32u *)0xE0040010u) 11179 #define TPIU_COSD_REG *((volatile int32u *)0xE0040010u) 11180 #define TPIU_COSD_ADDR (0xE0040010u) 11181 #define TPIU_COSD_RESET (0x00000000u) 11182 /* PRESCALER field */ 11183 #define TPIU_COSD_PRESCALER (0x00001FFFu) 11184 #define TPIU_COSD_PRESCALER_MASK (0x00001FFFu) 11185 #define TPIU_COSD_PRESCALER_BIT (0) 11186 #define TPIU_COSD_PRESCALER_BITS (13) 11187 11188 #define TPIU_SPP *((volatile int32u *)0xE00400F0u) 11189 #define TPIU_SPP_REG *((volatile int32u *)0xE00400F0u) 11190 #define TPIU_SPP_ADDR (0xE00400F0u) 11191 #define TPIU_SPP_RESET (0x00000001u) 11192 /* PROTOCOL field */ 11193 #define TPIU_SPP_PROTOCOL (0x00000003u) 11194 #define TPIU_SPP_PROTOCOL_MASK (0x00000003u) 11195 #define TPIU_SPP_PROTOCOL_BIT (0) 11196 #define TPIU_SPP_PROTOCOL_BITS (2) 11197 11198 #define TPIU_FFS *((volatile int32u *)0xE0040300u) 11199 #define TPIU_FFS_REG *((volatile int32u *)0xE0040300u) 11200 #define TPIU_FFS_ADDR (0xE0040300u) 11201 #define TPIU_FFS_RESET (0x00000008u) 11202 /* FTNONSTOP field */ 11203 #define TPIU_FFS_FTNONSTOP (0x00000008u) 11204 #define TPIU_FFS_FTNONSTOP_MASK (0x00000008u) 11205 #define TPIU_FFS_FTNONSTOP_BIT (3) 11206 #define TPIU_FFS_FTNONSTOP_BITS (1) 11207 /* TCPRESENT field */ 11208 #define TPIU_FFS_TCPRESENT (0x00000004u) 11209 #define TPIU_FFS_TCPRESENT_MASK (0x00000004u) 11210 #define TPIU_FFS_TCPRESENT_BIT (2) 11211 #define TPIU_FFS_TCPRESENT_BITS (1) 11212 /* FTSTOPPED field */ 11213 #define TPIU_FFS_FTSTOPPED (0x00000002u) 11214 #define TPIU_FFS_FTSTOPPED_MASK (0x00000002u) 11215 #define TPIU_FFS_FTSTOPPED_BIT (1) 11216 #define TPIU_FFS_FTSTOPPED_BITS (1) 11217 /* FLINPROG field */ 11218 #define TPIU_FFS_FLINPROG (0x00000001u) 11219 #define TPIU_FFS_FLINPROG_MASK (0x00000001u) 11220 #define TPIU_FFS_FLINPROG_BIT (0) 11221 #define TPIU_FFS_FLINPROG_BITS (1) 11222 11223 #define TPIU_FFC *((volatile int32u *)0xE0040304u) 11224 #define TPIU_FFC_REG *((volatile int32u *)0xE0040304u) 11225 #define TPIU_FFC_ADDR (0xE0040304u) 11226 #define TPIU_FFC_RESET (0x00000102u) 11227 /* TRIGIN field */ 11228 #define TPIU_FFC_TRIGIN (0x00000100u) 11229 #define TPIU_FFC_TRIGIN_MASK (0x00000100u) 11230 #define TPIU_FFC_TRIGIN_BIT (8) 11231 #define TPIU_FFC_TRIGIN_BITS (1) 11232 /* ENFCONT field */ 11233 #define TPIU_FFC_ENFCONT (0x00000002u) 11234 #define TPIU_FFC_ENFCONT_MASK (0x00000002u) 11235 #define TPIU_FFC_ENFCONT_BIT (1) 11236 #define TPIU_FFC_ENFCONT_BITS (1) 11237 11238 #define TPIU_FSC *((volatile int32u *)0xE0040308u) 11239 #define TPIU_FSC_REG *((volatile int32u *)0xE0040308u) 11240 #define TPIU_FSC_ADDR (0xE0040308u) 11241 #define TPIU_FSC_RESET (0x00000000u) 11242 /* FSC field */ 11243 #define TPIU_FSC_FSC (0xFFFFFFFFu) 11244 #define TPIU_FSC_FSC_MASK (0xFFFFFFFFu) 11245 #define TPIU_FSC_FSC_BIT (0) 11246 #define TPIU_FSC_FSC_BITS (32) 11247 11248 #define TPIU_ITATBCTR2 *((volatile int32u *)0xE0040EF0u) 11249 #define TPIU_ITATBCTR2_REG *((volatile int32u *)0xE0040EF0u) 11250 #define TPIU_ITATBCTR2_ADDR (0xE0040EF0u) 11251 #define TPIU_ITATBCTR2_RESET (0x00000000u) 11252 /* ATREADY1 field */ 11253 #define TPIU_ITATBCTR2_ATREADY1 (0x00000001u) 11254 #define TPIU_ITATBCTR2_ATREADY1_MASK (0x00000001u) 11255 #define TPIU_ITATBCTR2_ATREADY1_BIT (0) 11256 #define TPIU_ITATBCTR2_ATREADY1_BITS (1) 11257 11258 #define TPIU_ITATBCTR0 *((volatile int32u *)0xE0040EF8u) 11259 #define TPIU_ITATBCTR0_REG *((volatile int32u *)0xE0040EF8u) 11260 #define TPIU_ITATBCTR0_ADDR (0xE0040EF8u) 11261 #define TPIU_ITATBCTR0_RESET (0x00000000u) 11262 /* ATREADY1 field */ 11263 #define TPIU_ITATBCTR0_ATREADY1 (0x00000001u) 11264 #define TPIU_ITATBCTR0_ATREADY1_MASK (0x00000001u) 11265 #define TPIU_ITATBCTR0_ATREADY1_BIT (0) 11266 #define TPIU_ITATBCTR0_ATREADY1_BITS (1) 11267 11268 /* ETM block */ 11269 #define DATA_ETM_BASE (0xE0041000u) 11270 #define DATA_ETM_END (0xE0041FFFu) 11271 #define DATA_ETM_SIZE (DATA_ETM_END - DATA_ETM_BASE + 1) 11272 11273 /* ROM_TAB block */ 11274 #define DATA_ROM_TAB_BASE (0xE00FF000u) 11275 #define DATA_ROM_TAB_END (0xE00FFFFFu) 11276 #define DATA_ROM_TAB_SIZE (DATA_ROM_TAB_END - DATA_ROM_TAB_BASE + 1) 11277 11278 #define ROM_SCS *((volatile int32u *)0xE00FF000u) 11279 #define ROM_SCS_REG *((volatile int32u *)0xE00FF000u) 11280 #define ROM_SCS_ADDR (0xE00FF000u) 11281 #define ROM_SCS_RESET (0xFFF0F003u) 11282 /* ADDR_OFF field */ 11283 #define ROM_SCS_ADDR_OFF (0xFFFFF000u) 11284 #define ROM_SCS_ADDR_OFF_MASK (0xFFFFF000u) 11285 #define ROM_SCS_ADDR_OFF_BIT (12) 11286 #define ROM_SCS_ADDR_OFF_BITS (20) 11287 /* FORMAT field */ 11288 #define ROM_SCS_FORMAT (0x00000002u) 11289 #define ROM_SCS_FORMAT_MASK (0x00000002u) 11290 #define ROM_SCS_FORMAT_BIT (1) 11291 #define ROM_SCS_FORMAT_BITS (1) 11292 /* ENTRY_PRES field */ 11293 #define ROM_SCS_ENTRY_PRES (0x00000001u) 11294 #define ROM_SCS_ENTRY_PRES_MASK (0x00000001u) 11295 #define ROM_SCS_ENTRY_PRES_BIT (0) 11296 #define ROM_SCS_ENTRY_PRES_BITS (1) 11297 11298 #define ROM_DWT *((volatile int32u *)0xE00FF004u) 11299 #define ROM_DWT_REG *((volatile int32u *)0xE00FF004u) 11300 #define ROM_DWT_ADDR (0xE00FF004u) 11301 #define ROM_DWT_RESET (0xFFF02003u) 11302 /* ADDR_OFF field */ 11303 #define ROM_DWT_ADDR_OFF (0xFFFFF000u) 11304 #define ROM_DWT_ADDR_OFF_MASK (0xFFFFF000u) 11305 #define ROM_DWT_ADDR_OFF_BIT (12) 11306 #define ROM_DWT_ADDR_OFF_BITS (20) 11307 /* FORMAT field */ 11308 #define ROM_DWT_FORMAT (0x00000002u) 11309 #define ROM_DWT_FORMAT_MASK (0x00000002u) 11310 #define ROM_DWT_FORMAT_BIT (1) 11311 #define ROM_DWT_FORMAT_BITS (1) 11312 /* ENTRY_PRES field */ 11313 #define ROM_DWT_ENTRY_PRES (0x00000001u) 11314 #define ROM_DWT_ENTRY_PRES_MASK (0x00000001u) 11315 #define ROM_DWT_ENTRY_PRES_BIT (0) 11316 #define ROM_DWT_ENTRY_PRES_BITS (1) 11317 11318 #define ROM_FPB *((volatile int32u *)0xE00FF008u) 11319 #define ROM_FPB_REG *((volatile int32u *)0xE00FF008u) 11320 #define ROM_FPB_ADDR (0xE00FF008u) 11321 #define ROM_FPB_RESET (0xFFF03003u) 11322 /* ADDR_OFF field */ 11323 #define ROM_FPB_ADDR_OFF (0xFFFFF000u) 11324 #define ROM_FPB_ADDR_OFF_MASK (0xFFFFF000u) 11325 #define ROM_FPB_ADDR_OFF_BIT (12) 11326 #define ROM_FPB_ADDR_OFF_BITS (20) 11327 /* FORMAT field */ 11328 #define ROM_FPB_FORMAT (0x00000002u) 11329 #define ROM_FPB_FORMAT_MASK (0x00000002u) 11330 #define ROM_FPB_FORMAT_BIT (1) 11331 #define ROM_FPB_FORMAT_BITS (1) 11332 /* ENTRY_PRES field */ 11333 #define ROM_FPB_ENTRY_PRES (0x00000001u) 11334 #define ROM_FPB_ENTRY_PRES_MASK (0x00000001u) 11335 #define ROM_FPB_ENTRY_PRES_BIT (0) 11336 #define ROM_FPB_ENTRY_PRES_BITS (1) 11337 11338 #define ROM_ITM *((volatile int32u *)0xE00FF00Cu) 11339 #define ROM_ITM_REG *((volatile int32u *)0xE00FF00Cu) 11340 #define ROM_ITM_ADDR (0xE00FF00Cu) 11341 #define ROM_ITM_RESET (0xFFF01003u) 11342 /* ADDR_OFF field */ 11343 #define ROM_ITM_ADDR_OFF (0xFFFFF000u) 11344 #define ROM_ITM_ADDR_OFF_MASK (0xFFFFF000u) 11345 #define ROM_ITM_ADDR_OFF_BIT (12) 11346 #define ROM_ITM_ADDR_OFF_BITS (20) 11347 /* FORMAT field */ 11348 #define ROM_ITM_FORMAT (0x00000002u) 11349 #define ROM_ITM_FORMAT_MASK (0x00000002u) 11350 #define ROM_ITM_FORMAT_BIT (1) 11351 #define ROM_ITM_FORMAT_BITS (1) 11352 /* ENTRY_PRES field */ 11353 #define ROM_ITM_ENTRY_PRES (0x00000001u) 11354 #define ROM_ITM_ENTRY_PRES_MASK (0x00000001u) 11355 #define ROM_ITM_ENTRY_PRES_BIT (0) 11356 #define ROM_ITM_ENTRY_PRES_BITS (1) 11357 11358 #define ROM_TPIU *((volatile int32u *)0xE00FF010u) 11359 #define ROM_TPIU_REG *((volatile int32u *)0xE00FF010u) 11360 #define ROM_TPIU_ADDR (0xE00FF010u) 11361 #define ROM_TPIU_RESET (0xFFF0F003u) 11362 /* ADDR_OFF field */ 11363 #define ROM_TPIU_ADDR_OFF (0xFFFFF000u) 11364 #define ROM_TPIU_ADDR_OFF_MASK (0xFFFFF000u) 11365 #define ROM_TPIU_ADDR_OFF_BIT (12) 11366 #define ROM_TPIU_ADDR_OFF_BITS (20) 11367 /* FORMAT field */ 11368 #define ROM_TPIU_FORMAT (0x00000002u) 11369 #define ROM_TPIU_FORMAT_MASK (0x00000002u) 11370 #define ROM_TPIU_FORMAT_BIT (1) 11371 #define ROM_TPIU_FORMAT_BITS (1) 11372 /* ENTRY_PRES field */ 11373 #define ROM_TPIU_ENTRY_PRES (0x00000001u) 11374 #define ROM_TPIU_ENTRY_PRES_MASK (0x00000001u) 11375 #define ROM_TPIU_ENTRY_PRES_BIT (0) 11376 #define ROM_TPIU_ENTRY_PRES_BITS (1) 11377 11378 #define ROM_ETM *((volatile int32u *)0xE00FF014u) 11379 #define ROM_ETM_REG *((volatile int32u *)0xE00FF014u) 11380 #define ROM_ETM_ADDR (0xE00FF014u) 11381 #define ROM_ETM_RESET (0xFFF0F002u) 11382 /* ADDR_OFF field */ 11383 #define ROM_ETM_ADDR_OFF (0xFFFFF000u) 11384 #define ROM_ETM_ADDR_OFF_MASK (0xFFFFF000u) 11385 #define ROM_ETM_ADDR_OFF_BIT (12) 11386 #define ROM_ETM_ADDR_OFF_BITS (20) 11387 /* FORMAT field */ 11388 #define ROM_ETM_FORMAT (0x00000002u) 11389 #define ROM_ETM_FORMAT_MASK (0x00000002u) 11390 #define ROM_ETM_FORMAT_BIT (1) 11391 #define ROM_ETM_FORMAT_BITS (1) 11392 /* ENTRY_PRES field */ 11393 #define ROM_ETM_ENTRY_PRES (0x00000001u) 11394 #define ROM_ETM_ENTRY_PRES_MASK (0x00000001u) 11395 #define ROM_ETM_ENTRY_PRES_BIT (0) 11396 #define ROM_ETM_ENTRY_PRES_BITS (1) 11397 11398 #define ROM_END *((volatile int32u *)0xE00FF018u) 11399 #define ROM_END_REG *((volatile int32u *)0xE00FF018u) 11400 #define ROM_END_ADDR (0xE00FF018u) 11401 #define ROM_END_RESET (0x00000000u) 11402 /* END field */ 11403 #define ROM_END_END (0xFFFFFFFFu) 11404 #define ROM_END_END_MASK (0xFFFFFFFFu) 11405 #define ROM_END_END_BIT (0) 11406 #define ROM_END_END_BITS (32) 11407 11408 #define ROM_MEMTYPE *((volatile int32u *)0xE00FFFCCu) 11409 #define ROM_MEMTYPE_REG *((volatile int32u *)0xE00FFFCCu) 11410 #define ROM_MEMTYPE_ADDR (0xE00FFFCCu) 11411 #define ROM_MEMTYPE_RESET (0x00000001u) 11412 /* MEMTYPE field */ 11413 #define ROM_MEMTYPE_MEMTYPE (0x00000001u) 11414 #define ROM_MEMTYPE_MEMTYPE_MASK (0x00000001u) 11415 #define ROM_MEMTYPE_MEMTYPE_BIT (0) 11416 #define ROM_MEMTYPE_MEMTYPE_BITS (1) 11417 11418 #define ROM_PID4 *((volatile int32u *)0xE00FFFD0u) 11419 #define ROM_PID4_REG *((volatile int32u *)0xE00FFFD0u) 11420 #define ROM_PID4_ADDR (0xE00FFFD0u) 11421 #define ROM_PID4_RESET (0x00000000u) 11422 /* PID field */ 11423 #define ROM_PID4_PID (0x0000000Fu) 11424 #define ROM_PID4_PID_MASK (0x0000000Fu) 11425 #define ROM_PID4_PID_BIT (0) 11426 #define ROM_PID4_PID_BITS (4) 11427 11428 #define ROM_PID5 *((volatile int32u *)0xE00FFFD4u) 11429 #define ROM_PID5_REG *((volatile int32u *)0xE00FFFD4u) 11430 #define ROM_PID5_ADDR (0xE00FFFD4u) 11431 #define ROM_PID5_RESET (0x00000000u) 11432 /* PID field */ 11433 #define ROM_PID5_PID (0x0000000Fu) 11434 #define ROM_PID5_PID_MASK (0x0000000Fu) 11435 #define ROM_PID5_PID_BIT (0) 11436 #define ROM_PID5_PID_BITS (4) 11437 11438 #define ROM_PID6 *((volatile int32u *)0xE00FFFD8u) 11439 #define ROM_PID6_REG *((volatile int32u *)0xE00FFFD8u) 11440 #define ROM_PID6_ADDR (0xE00FFFD8u) 11441 #define ROM_PID6_RESET (0x00000000u) 11442 /* PID field */ 11443 #define ROM_PID6_PID (0x0000000Fu) 11444 #define ROM_PID6_PID_MASK (0x0000000Fu) 11445 #define ROM_PID6_PID_BIT (0) 11446 #define ROM_PID6_PID_BITS (4) 11447 11448 #define ROM_PID7 *((volatile int32u *)0xE00FFFDCu) 11449 #define ROM_PID7_REG *((volatile int32u *)0xE00FFFDCu) 11450 #define ROM_PID7_ADDR (0xE00FFFDCu) 11451 #define ROM_PID7_RESET (0x00000000u) 11452 /* PID field */ 11453 #define ROM_PID7_PID (0x0000000Fu) 11454 #define ROM_PID7_PID_MASK (0x0000000Fu) 11455 #define ROM_PID7_PID_BIT (0) 11456 #define ROM_PID7_PID_BITS (4) 11457 11458 #define ROM_PID0 *((volatile int32u *)0xE00FFFE0u) 11459 #define ROM_PID0_REG *((volatile int32u *)0xE00FFFE0u) 11460 #define ROM_PID0_ADDR (0xE00FFFE0u) 11461 #define ROM_PID0_RESET (0x00000000u) 11462 /* PID field */ 11463 #define ROM_PID0_PID (0x0000000Fu) 11464 #define ROM_PID0_PID_MASK (0x0000000Fu) 11465 #define ROM_PID0_PID_BIT (0) 11466 #define ROM_PID0_PID_BITS (4) 11467 11468 #define ROM_PID1 *((volatile int32u *)0xE00FFFE4u) 11469 #define ROM_PID1_REG *((volatile int32u *)0xE00FFFE4u) 11470 #define ROM_PID1_ADDR (0xE00FFFE4u) 11471 #define ROM_PID1_RESET (0x00000000u) 11472 /* PID field */ 11473 #define ROM_PID1_PID (0x0000000Fu) 11474 #define ROM_PID1_PID_MASK (0x0000000Fu) 11475 #define ROM_PID1_PID_BIT (0) 11476 #define ROM_PID1_PID_BITS (4) 11477 11478 #define ROM_PID2 *((volatile int32u *)0xE00FFFE8u) 11479 #define ROM_PID2_REG *((volatile int32u *)0xE00FFFE8u) 11480 #define ROM_PID2_ADDR (0xE00FFFE8u) 11481 #define ROM_PID2_RESET (0x00000000u) 11482 /* PID field */ 11483 #define ROM_PID2_PID (0x0000000Fu) 11484 #define ROM_PID2_PID_MASK (0x0000000Fu) 11485 #define ROM_PID2_PID_BIT (0) 11486 #define ROM_PID2_PID_BITS (4) 11487 11488 #define ROM_PID3 *((volatile int32u *)0xE00FFFECu) 11489 #define ROM_PID3_REG *((volatile int32u *)0xE00FFFECu) 11490 #define ROM_PID3_ADDR (0xE00FFFECu) 11491 #define ROM_PID3_RESET (0x00000000u) 11492 /* PID field */ 11493 #define ROM_PID3_PID (0x0000000Fu) 11494 #define ROM_PID3_PID_MASK (0x0000000Fu) 11495 #define ROM_PID3_PID_BIT (0) 11496 #define ROM_PID3_PID_BITS (4) 11497 11498 #define ROM_CID0 *((volatile int32u *)0xE00FFFF0u) 11499 #define ROM_CID0_REG *((volatile int32u *)0xE00FFFF0u) 11500 #define ROM_CID0_ADDR (0xE00FFFF0u) 11501 #define ROM_CID0_RESET (0x0000000Du) 11502 /* CID field */ 11503 #define ROM_CID0_CID (0x000000FFu) 11504 #define ROM_CID0_CID_MASK (0x000000FFu) 11505 #define ROM_CID0_CID_BIT (0) 11506 #define ROM_CID0_CID_BITS (8) 11507 11508 #define ROM_CID1 *((volatile int32u *)0xE00FFFF4u) 11509 #define ROM_CID1_REG *((volatile int32u *)0xE00FFFF4u) 11510 #define ROM_CID1_ADDR (0xE00FFFF4u) 11511 #define ROM_CID1_RESET (0x00000010u) 11512 /* CID field */ 11513 #define ROM_CID1_CID (0x000000FFu) 11514 #define ROM_CID1_CID_MASK (0x000000FFu) 11515 #define ROM_CID1_CID_BIT (0) 11516 #define ROM_CID1_CID_BITS (8) 11517 11518 #define ROM_CID2 *((volatile int32u *)0xE00FFFF8u) 11519 #define ROM_CID2_REG *((volatile int32u *)0xE00FFFF8u) 11520 #define ROM_CID2_ADDR (0xE00FFFF8u) 11521 #define ROM_CID2_RESET (0x00000005u) 11522 /* CID field */ 11523 #define ROM_CID2_CID (0x000000FFu) 11524 #define ROM_CID2_CID_MASK (0x000000FFu) 11525 #define ROM_CID2_CID_BIT (0) 11526 #define ROM_CID2_CID_BITS (8) 11527 11528 #define ROM_CID3 *((volatile int32u *)0xE00FFFFCu) 11529 #define ROM_CID3_REG *((volatile int32u *)0xE00FFFFCu) 11530 #define ROM_CID3_ADDR (0xE00FFFFCu) 11531 #define ROM_CID3_RESET (0x000000B1u) 11532 /* CID field */ 11533 #define ROM_CID3_CID (0x000000FFu) 11534 #define ROM_CID3_CID_MASK (0x000000FFu) 11535 #define ROM_CID3_CID_BIT (0) 11536 #define ROM_CID3_CID_BITS (8) 11537 11538 /* VENDOR block */ 11539 #define DATA_VENDOR_BASE (0xE0100000u) 11540 #define DATA_VENDOR_END (0xFFFFFFFFu) 11541 #define DATA_VENDOR_SIZE (DATA_VENDOR_END - DATA_VENDOR_BASE + 1) 11542 11543 11544 #endif /*__REGS_H__*/