Contiki 2.6

platform-conf.h

Go to the documentation of this file.
00001 /*
00002  * Copyright (c) 2010, Swedish Institute of Computer Science.
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the Institute nor the names of its contributors
00014  *    may be used to endorse or promote products derived from this software
00015  *    without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
00018  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00020  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
00021  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00022  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00023  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00024  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00027  * SUCH DAMAGE.
00028  *
00029  * $Id: platform-conf.h,v 1.2 2010/12/16 22:52:27 adamdunkels Exp $
00030  */
00031 
00032 /**
00033  * \file
00034  *         A brief description of what this file is
00035  * \author
00036  *         Niclas Finne <nfi@sics.se>
00037  *         Joakim Eriksson <joakime@sics.se>
00038  */
00039 
00040 #ifndef __PLATFORM_CONF_H__
00041 #define __PLATFORM_CONF_H__
00042 
00043 /*
00044  * Definitions below are dictated by the hardware and not really
00045  * changeable!
00046  */
00047 /* Platform TMOTE_SKY */
00048 #define TMOTE_SKY 1
00049 
00050 #define PLATFORM_HAS_LEDS    1
00051 #define PLATFORM_HAS_BUTTON  1
00052 #define PLATFORM_HAS_LIGHT   1
00053 #define PLATFORM_HAS_BATTERY 1
00054 #define PLATFORM_HAS_SHT11   1
00055 
00056 /* CPU target speed in Hz */
00057 #define F_CPU 3900000uL /*2457600uL*/
00058 
00059 /* Our clock resolution, this is the same as Unix HZ. */
00060 #define CLOCK_CONF_SECOND 128UL
00061 
00062 #define BAUD2UBR(baud) ((F_CPU/baud))
00063 
00064 #define CCIF
00065 #define CLIF
00066 
00067 #define HAVE_STDINT_H
00068 #include "msp430def.h"
00069 
00070 
00071 /* Types for clocks and uip_stats */
00072 typedef unsigned short uip_stats_t;
00073 typedef unsigned long clock_time_t;
00074 typedef unsigned long off_t;
00075 
00076 /* the low-level radio driver */
00077 #define NETSTACK_CONF_RADIO   cc2420_driver
00078 
00079 /* LED ports */
00080 #define LEDS_PxDIR P5DIR
00081 #define LEDS_PxOUT P5OUT
00082 #define LEDS_CONF_RED    0x10
00083 #define LEDS_CONF_GREEN  0x20
00084 #define LEDS_CONF_YELLOW 0x40
00085 
00086 /* DCO speed resynchronization for more robust UART, etc. */
00087 #ifndef DCOSYNCH_CONF_ENABLED
00088 #define DCOSYNCH_CONF_ENABLED 1
00089 #endif /* DCOSYNCH_CONF_ENABLED */
00090 #ifndef DCOSYNCH_CONF_PERIOD
00091 #define DCOSYNCH_CONF_PERIOD 30
00092 #endif /* DCOSYNCH_CONF_PERIOD */
00093 
00094 #define ROM_ERASE_UNIT_SIZE  512
00095 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
00096 
00097 
00098 #define CFS_CONF_OFFSET_TYPE    long
00099 
00100 
00101 /* Use the first 64k of external flash for node configuration */
00102 #define NODE_ID_XMEM_OFFSET     (0 * XMEM_ERASE_UNIT_SIZE)
00103 
00104 /* Use the second 64k of external flash for codeprop. */
00105 #define EEPROMFS_ADDR_CODEPROP  (1 * XMEM_ERASE_UNIT_SIZE)
00106 
00107 #define CFS_XMEM_CONF_OFFSET    (2 * XMEM_ERASE_UNIT_SIZE)
00108 #define CFS_XMEM_CONF_SIZE      (1 * XMEM_ERASE_UNIT_SIZE)
00109 
00110 #define CFS_RAM_CONF_SIZE 4096
00111 
00112 /*
00113  * SPI bus configuration for the TMote Sky.
00114  */
00115 
00116 /* SPI input/output registers. */
00117 #define SPI_TXBUF U0TXBUF
00118 #define SPI_RXBUF U0RXBUF
00119 
00120                                 /* USART0 Tx ready? */
00121 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
00122                                 /* USART0 Rx ready? */
00123 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
00124                                 /* USART0 Tx buffer ready? */
00125 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
00126 
00127 #define SCK            1  /* P3.1 - Output: SPI Serial Clock (SCLK) */
00128 #define MOSI           2  /* P3.2 - Output: SPI Master out - slave in (MOSI) */
00129 #define MISO           3  /* P3.3 - Input:  SPI Master in - slave out (MISO) */
00130 
00131 /*
00132  * SPI bus - M25P80 external flash configuration.
00133  */
00134 
00135 #define FLASH_PWR       3       /* P4.3 Output */
00136 #define FLASH_CS        4       /* P4.4 Output */
00137 #define FLASH_HOLD      7       /* P4.7 Output */
00138 
00139 /* Enable/disable flash access to the SPI bus (active low). */
00140 
00141 #define SPI_FLASH_ENABLE()  ( P4OUT &= ~BV(FLASH_CS) )
00142 #define SPI_FLASH_DISABLE() ( P4OUT |=  BV(FLASH_CS) )
00143 
00144 #define SPI_FLASH_HOLD()                ( P4OUT &= ~BV(FLASH_HOLD) )
00145 #define SPI_FLASH_UNHOLD()              ( P4OUT |=  BV(FLASH_HOLD) )
00146 
00147 /*
00148  * SPI bus - CC2420 pin configuration.
00149  */
00150 
00151 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800
00152 
00153 /* P1.0 - Input: FIFOP from CC2420 */
00154 #define CC2420_FIFOP_PORT(type)   P1##type
00155 #define CC2420_FIFOP_PIN          0
00156 /* P1.3 - Input: FIFO from CC2420 */
00157 #define CC2420_FIFO_PORT(type)     P1##type
00158 #define CC2420_FIFO_PIN            3
00159 /* P1.4 - Input: CCA from CC2420 */
00160 #define CC2420_CCA_PORT(type)      P1##type
00161 #define CC2420_CCA_PIN             4
00162 /* P4.1 - Input:  SFD from CC2420 */
00163 #define CC2420_SFD_PORT(type)      P4##type
00164 #define CC2420_SFD_PIN             1
00165 /* P4.2 - Output: SPI Chip Select (CS_N) */
00166 #define CC2420_CSN_PORT(type)      P4##type
00167 #define CC2420_CSN_PIN             2
00168 /* P4.5 - Output: VREG_EN to CC2420 */
00169 #define CC2420_VREG_PORT(type)     P4##type
00170 #define CC2420_VREG_PIN            5
00171 /* P4.6 - Output: RESET_N to CC2420 */
00172 #define CC2420_RESET_PORT(type)    P4##type
00173 #define CC2420_RESET_PIN           6
00174 
00175 #define CC2420_IRQ_VECTOR PORT1_VECTOR
00176 
00177 /* Pin status. */
00178 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
00179 #define CC2420_FIFO_IS_1  (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
00180 #define CC2420_CCA_IS_1   (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
00181 #define CC2420_SFD_IS_1   (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
00182 
00183 /* The CC2420 reset pin. */
00184 #define SET_RESET_INACTIVE()   (CC2420_RESET_PORT(OUT) |=  BV(CC2420_RESET_PIN))
00185 #define SET_RESET_ACTIVE()     (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
00186 
00187 /* CC2420 voltage regulator enable pin. */
00188 #define SET_VREG_ACTIVE()       (CC2420_VREG_PORT(OUT) |=  BV(CC2420_VREG_PIN))
00189 #define SET_VREG_INACTIVE()     (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
00190 
00191 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
00192 #define CC2420_FIFOP_INT_INIT() do {                  \
00193     CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN);  \
00194     CC2420_CLEAR_FIFOP_INT();                         \
00195   } while(0)
00196 
00197 /* FIFOP on external interrupt 0. */
00198 #define CC2420_ENABLE_FIFOP_INT()  do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
00199 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
00200 #define CC2420_CLEAR_FIFOP_INT()   do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
00201 
00202 /*
00203  * Enables/disables CC2420 access to the SPI bus (not the bus).
00204  * (Chip Select)
00205  */
00206 
00207  /* ENABLE CSn (active low) */
00208 #define CC2420_SPI_ENABLE()     (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
00209  /* DISABLE CSn (active low) */
00210 #define CC2420_SPI_DISABLE()    (CC2420_CSN_PORT(OUT) |=  BV(CC2420_CSN_PIN))
00211 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
00212 
00213 #endif /* __PLATFORM_CONF_H__ */