Contiki 2.6

cc1020-internal.h

00001 #ifndef CC1020_INTERNAL_H
00002 #define CC1020_INTERNAL_H
00003 
00004 #include "contiki.h"
00005 
00006 #define CC1020_MAIN             0x00
00007 #define CC1020_INTERFACE        0x01
00008 #define CC1020_RESET            0x02
00009 #define CC1020_SEQUENCING       0x03
00010 #define CC1020_FREQ_2A          0x04
00011 #define CC1020_FREQ_1A          0x05
00012 #define CC1020_FREQ_0A          0x06
00013 #define CC1020_CLOCK_A          0x07
00014 #define CC1020_FREQ_2B          0x08
00015 #define CC1020_FREQ_1B          0x09
00016 #define CC1020_FREQ_0B          0x0A
00017 #define CC1020_CLOCK_B          0x0B
00018 #define CC1020_VCO              0x0C
00019 #define CC1020_MODEM            0x0D
00020 #define CC1020_DEVIATION        0x0E
00021 #define CC1020_AFC_CONTROL      0x0F
00022 #define CC1020_FILTER           0x10
00023 #define CC1020_VGA1             0x11
00024 #define CC1020_VGA2             0x12
00025 #define CC1020_VGA3             0x13
00026 #define CC1020_VGA4             0x14
00027 #define CC1020_LOCK             0x15
00028 #define CC1020_FRONTEND         0x16
00029 #define CC1020_ANALOG           0x17
00030 #define CC1020_BUFF_SWING       0x18
00031 #define CC1020_BUFF_CURRENT     0x19
00032 #define CC1020_PLL_BW           0x1A
00033 #define CC1020_CALIBRATE        0x1B
00034 #define CC1020_PA_POWER         0x1C
00035 #define CC1020_MATCH            0x1D
00036 #define CC1020_PHASE_COMP       0x1E
00037 #define CC1020_GAIN_COMP        0x1F
00038 #define CC1020_POWERDOWN        0x20
00039 #define CC1020_TEST1            0x21
00040 #define CC1020_TEST2            0x22
00041 #define CC1020_TEST3            0x23
00042 #define CC1020_TEST4            0x24
00043 #define CC1020_TEST5            0x25
00044 #define CC1020_TEST6            0x26
00045 #define CC1020_TEST7            0x27
00046 #define CC1020_STATUS           0x40
00047 #define CC1020_RESET_DONE       0x41
00048 #define CC1020_RSS              0x42
00049 #define CC1020_AFC              0x43
00050 #define CC1020_GAUSS_FILTER     0x44
00051 #define CC1020_STATUS1          0x45
00052 #define CC1020_STATUS2          0x46
00053 #define CC1020_STATUS3          0x47
00054 #define CC1020_STATUS4          0x48
00055 #define CC1020_STATUS5          0x49
00056 #define CC1020_STATUS6          0x4A
00057 #define CC1020_STATUS7          0x4B
00058 
00059 /* Flags for the MAIN register. */
00060 #define RESET_N                 1
00061 #define BIAS_PD                 (1<<1)
00062 #define XOSC_PD                 (1<<2)
00063 #define FS_PD                   (1<<3)
00064 #define PD_MODE_1               (1<<4)
00065 #define PD_MODE_2               (1<<5)
00066 #define F_REG                   (1<<6)
00067 #define RXTX                    (1<<7)
00068 
00069 /* In power up mode, the MAIN register modifies some flags to the following. */
00070 #define SEQ_PD                  (1<<1)
00071 #define SEQ_CAL_1               (1<<2)
00072 #define SEQ_CAL_2               (1<<3)
00073 
00074 // For CC1020_STATUS
00075 #define CARRIER_SENSE           0x08
00076 #define LOCK_CONTINUOUS         0x10
00077 #define LOCK_INSTANT            0x20
00078 #define SEQ_ERROR               0x40
00079 #define CAL_COMPLETE            0x80
00080 
00081 #define PA_POWER                0x0F    // initial default for output power
00082 #define LOCK_NOK                0x00
00083 #define LOCK_OK                 0x01
00084 #define LOCK_RECAL_OK           0x02
00085 #define CAL_TIMEOUT             0x7FFE
00086 #define LOCK_TIMEOUT            0x7FFE
00087 #define RESET_TIMEOUT           0x7FFE
00088 #define TX_CURRENT              0x87
00089 #define RX_CURRENT              0x86
00090 
00091 // CC1020 driver configuration
00092 
00093 // PDI (Data in) is on P21
00094 #define PDO             (P2IN & 0x01)
00095 
00096 // PSEL is on P30 and low active
00097 #define PSEL_ON         do { P3OUT &= ~0x01; } while(0)
00098 #define PSEL_OFF        do { P3OUT |=  0x01; } while(0)
00099 #define PCLK_HIGH       do { P2OUT |=  0x08; }  while(0)
00100 #define PCLK_LOW        do { P2OUT &= ~0x08; }  while(0)
00101 
00102 // PDO (Data out) is on P22
00103 #define PDI_HIGH        do { P2OUT |=  0x02; }  while(0)
00104 
00105 #define PDI_LOW         do { P2OUT &= ~0x02; }  while(0)
00106 
00107 // Enable power for LNA (P24, low-active)
00108 #define LNA_POWER_ON()  do { P2OUT &= ~0x10; }  while(0)
00109 
00110 #define LNA_POWER_OFF() do { P2OUT |=  0x10; }  while(0)
00111 
00112 #define CC_LOCK         (P2IN & 0x04)
00113 
00114 #define DISABLE_RX_IRQ()                                \
00115                 do { IE1 &= ~(URXIE0); } while(0)
00116 
00117 #define ENABLE_RX_IRQ()                                 \
00118         do { IFG1 &= ~URXIFG0; IE1 |= URXIE0; } while(0)
00119 
00120 #define ACK_TIMEOUT_115         4       // In RADIO_STROKE ticks
00121 #define ACK_TIMEOUT_19          16
00122 
00123 #define MHZ_869525              1
00124 
00125 const uint8_t cc1020_config_19200[41] = {
00126   0x01,   // 0x00, MAIN
00127   0x0F,   // 0x01, INTERFACE
00128   0xFF,   // 0x02, RESET
00129   0x8F,   // 0x03, SEQUENCING
00130   // 869.525 at 50kHz
00131   0x3A,   // 0x04, FREQ_2A
00132   0x32,   // 0x05, FREQ_1A
00133   0x97,   // 0x06, FREQ_0A // 19200
00134   0x38,   // 0x07, CLOCK_A // 19200
00135   0x3A,   // 0x08, FREQ_2B
00136   0x37,   // 0x09, FREQ_1B
00137   0xEB,   // 0x0A, FREQ_0B // 19200
00138   0x38,   // 0x0B, CLOCK_B // 19200
00139   0x44,   // 0x0C, VCO     44
00140   0x51,   // 0x0D, MODEM   Manchester
00141   0x2B,   // 0x0E, DEVIATION // FSK
00142   0x4C,   // 0x0F, AFC_CONTROL Ruetten 0xCC
00143   0x25,   // 0x10, FILTER Bandwith 51.2 kHz i.e. channel spacing 100kHz
00144   0x61,   // 0x11, VGA1
00145   0x55,   // 0x12, VGA2
00146   0x2D,   // 0x13, VGA3
00147   0x37,   // 0x14, VGA4 // 0x29, VGA4 ADJUSTED CS to 23!
00148   0x40,   // 0x15, LOCK is Carrier SENSE
00149   0x76,   // 0x16, FRONTEND
00150   0x87,   // 0x17, ANALOG, RX=86/TX=87
00151   0x10,   // 0x18, BUFF_SWING
00152   0x25,   // 0x19, BUFF_CURRENT
00153   0xAE,   // 0x1A, PLL_BW
00154   0x34,   // 0x1B, CALIBRATE
00155   PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
00156   0xF0,   // 0x1D, MATCH
00157   0x00,   // 0x1E, PHASE_COMP
00158   0x00,   // 0x1F, GAIN_COMP
00159   0x00,   // 0x20, POWERDOWN
00160   0x4d,   // 0x4d,  // 0x21,
00161   0x10,   // 0x10,  // 0x22,
00162   0x06,   // 0x06,  // 0x23,
00163   0x00,   // 0x00,  // 0x24,
00164   0x40,   // 0x40,  // 0x25,
00165   0x00,   // 0x00,  // 0x26,
00166   0x00,   // 0x00,   // 0x27,
00167   // Not in real config of chipCon from here!!!
00168   ACK_TIMEOUT_19
00169 };
00170 
00171 const uint8_t cc1020_config_115200[41] = {
00172   0x01,   // 0x00, MAIN
00173   0x0F,   // 0x01, INTERFACE
00174   0xFF,   // 0x02, RESET
00175   0x8F,   // 0x03, SEQUENCING
00176   // 869.525 at 200kHz
00177   0x3A,   // 0x04, FREQ_2A
00178   0x32,   // 0x05, FREQ_1A
00179   0x97,   // 0x06, FREQ_0A // 19200
00180   0x29,   // 0x07, CLOCK_A // 19200
00181   0x3A,   // 0x08, FREQ_2B
00182   0x37,   // 0x09, FREQ_1B
00183   0xEB,   // 0x0A, FREQ_0B // 19200
00184   0x29,   // 0x0B, CLOCK_B // 19200
00185   0x44,   // 0x0C, VCO 44
00186   0x51,   // 0x0D, MODEM Manchester
00187   0x58,   // 0x0E, DEVIATION // FSK
00188   0x4C,   // 0x0F, AFC_CONTROL Ruetten 0xCC
00189   0x80,   // 0x10, FILTER Bandwith 307.2kHz, i.e. channel spacing 500 kHz
00190   0x61,   // 0x11, VGA1
00191   0x57,   // 0x12, VGA2
00192   0x30,   // 0x13, VGA3
00193   0x35,   // 0x14, VGA4
00194   0x20,   // 0x15, LOCK is Carrier SENSE
00195   0x76,   // 0x16, FRONTEND
00196   0x87,   // 0x17, ANALOG, RX=86/TX=87
00197   0x10,   // 0x18, BUFF_SWING
00198   0x25,   // 0x19, BUFF_CURRENT
00199   0xAE,   // 0x1A, PLL_BW
00200   0x34,   // 0x1B, CALIBRATE
00201   PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
00202   0xF0,   // 0x1D, MATCH
00203   0x00,   // 0x1E, PHASE_COMP
00204   0x00,   // 0x1F, GAIN_COMP
00205   0x00,   // 0x20, POWERDOWN
00206   0x4d,   // 0x21,
00207   0x10,   // 0x22,
00208   0x06,   // 0x23,
00209   0x00,   // 0x24,
00210   0x40,   // 0x25,
00211   0x00,   // 0x26,
00212   0x00,   // 0x27,             
00213   // Not in real config of chipCon from here!!!
00214   ACK_TIMEOUT_115
00215 };
00216 
00217 /// cc1020 state
00218 enum cc1020_state {
00219   CC1020_OFF = 0,
00220   CC1020_RX  = 0x01,
00221   CC1020_TX  = 0x02,
00222   
00223   CC1020_RX_SEARCHING = 0x10,           // searching for preamble + sync word
00224   CC1020_RX_RECEIVING = 0x20,           // receiving bytes
00225   CC1020_RX_PROCESSING = 0x40,          // processing data in buffer
00226   
00227   CC1020_OP_STATE = 0x73,
00228   
00229   CC1020_TURN_OFF = 0x80,
00230 };
00231 
00232 #define CC1020_SET_OPSTATE(opstate)             cc1020_state = ((cc1020_state & ~CC1020_OP_STATE) | (opstate))
00233 
00234 /******************************************************************************
00235  * @name        Packet specification
00236  * @{
00237  */
00238 
00239 // header: number of bytes in packet including header
00240 struct cc1020_header {
00241   uint8_t  pad;
00242   uint8_t  length;
00243 } __attribute__((packed));
00244 
00245 
00246 #define CC1020_BUFFERSIZE       128
00247 
00248 
00249 #define PREAMBLE_SIZE           6
00250 #define PREAMBLE                0xAA
00251 
00252 #define SYNCWORD_SIZE           2
00253 #define HDR_SIZE                (sizeof (struct cc1020_header))
00254 
00255 #define CRC_SIZE                2
00256 
00257 #define TAIL_SIZE               2
00258 #define TAIL                    0xFA
00259 
00260 
00261 ///@}
00262 
00263 #endif /* CC1020_INTERNAL_H */