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00001 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
00002 * File Name          : stm32f10x_map.h
00003 * Author             : MCD Application Team
00004 * Version            : V2.0.3
00005 * Date               : 09/22/2008
00006 * Description        : This file contains all the peripheral register's definitions,
00007 *                      bits definitions and memory mapping.
00008 ********************************************************************************
00009 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00010 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
00011 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
00012 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
00013 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
00014 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00015 *******************************************************************************/
00016
00017 /* Define to prevent recursive inclusion -------------------------------------*/
00018 #ifndef __STM32F10x_MAP_H
00019 #define __STM32F10x_MAP_H
00020
00021 #ifndef EXT
00022   #define EXT extern
00023 #endif /* EXT */
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm32f10x_conf.h"
00027 #include "stm32f10x_type.h"
00028 #include "cortexm3_macro.h"
00029
00030 /* Exported types ------------------------------------------------------------*/
00031 /******************************************************************************/
00032 /*                         Peripheral registers structures                    */
00033 /******************************************************************************/
00034
00035 /*------------------------ Analog to Digital Converter -----------------------*/
00036 typedef struct
00037 {
00038   vu32 SR;
00039   vu32 CR1;
00040   vu32 CR2;
00041   vu32 SMPR1;
00042   vu32 SMPR2;
00043   vu32 JOFR1;
00044   vu32 JOFR2;
00045   vu32 JOFR3;
00046   vu32 JOFR4;
00047   vu32 HTR;
00048   vu32 LTR;
00049   vu32 SQR1;
00050   vu32 SQR2;
00051   vu32 SQR3;
00052   vu32 JSQR;
00053   vu32 JDR1;
00054   vu32 JDR2;
00055   vu32 JDR3;
00056   vu32 JDR4;
00057   vu32 DR;
00058 } ADC_TypeDef;
00059
00060 /*------------------------ Backup Registers ----------------------------------*/
00061 typedef struct
00062 {
00063   u32  RESERVED0;
00064   vu16 DR1;
00065   u16  RESERVED1;
00066   vu16 DR2;
00067   u16  RESERVED2;
00068   vu16 DR3;
00069   u16  RESERVED3;
00070   vu16 DR4;
00071   u16  RESERVED4;
00072   vu16 DR5;
00073   u16  RESERVED5;
00074   vu16 DR6;
00075   u16  RESERVED6;
00076   vu16 DR7;
00077   u16  RESERVED7;
00078   vu16 DR8;
00079   u16  RESERVED8;
00080   vu16 DR9;
00081   u16  RESERVED9;
00082   vu16 DR10;
00083   u16  RESERVED10;
00084   vu16 RTCCR;
00085   u16  RESERVED11;
00086   vu16 CR;
00087   u16  RESERVED12;
00088   vu16 CSR;
00089   u16  RESERVED13[5];
00090   vu16 DR11;
00091   u16  RESERVED14;
00092   vu16 DR12;
00093   u16  RESERVED15;
00094   vu16 DR13;
00095   u16  RESERVED16;
00096   vu16 DR14;
00097   u16  RESERVED17;
00098   vu16 DR15;
00099   u16  RESERVED18;
00100   vu16 DR16;
00101   u16  RESERVED19;
00102   vu16 DR17;
00103   u16  RESERVED20;
00104   vu16 DR18;
00105   u16  RESERVED21;
00106   vu16 DR19;
00107   u16  RESERVED22;
00108   vu16 DR20;
00109   u16  RESERVED23;
00110   vu16 DR21;
00111   u16  RESERVED24;
00112   vu16 DR22;
00113   u16  RESERVED25;
00114   vu16 DR23;
00115   u16  RESERVED26;
00116   vu16 DR24;
00117   u16  RESERVED27;
00118   vu16 DR25;
00119   u16  RESERVED28;
00120   vu16 DR26;
00121   u16  RESERVED29;
00122   vu16 DR27;
00123   u16  RESERVED30;
00124   vu16 DR28;
00125   u16  RESERVED31;
00126   vu16 DR29;
00127   u16  RESERVED32;
00128   vu16 DR30;
00129   u16  RESERVED33;
00130   vu16 DR31;
00131   u16  RESERVED34;
00132   vu16 DR32;
00133   u16  RESERVED35;
00134   vu16 DR33;
00135   u16  RESERVED36;
00136   vu16 DR34;
00137   u16  RESERVED37;
00138   vu16 DR35;
00139   u16  RESERVED38;
00140   vu16 DR36;
00141   u16  RESERVED39;
00142   vu16 DR37;
00143   u16  RESERVED40;
00144   vu16 DR38;
00145   u16  RESERVED41;
00146   vu16 DR39;
00147   u16  RESERVED42;
00148   vu16 DR40;
00149   u16  RESERVED43;
00150   vu16 DR41;
00151   u16  RESERVED44;
00152   vu16 DR42;
00153   u16  RESERVED45;
00154 } BKP_TypeDef;
00155
00156 /*------------------------ Controller Area Network ---------------------------*/
00157 typedef struct
00158 {
00159   vu32 TIR;
00160   vu32 TDTR;
00161   vu32 TDLR;
00162   vu32 TDHR;
00163 } CAN_TxMailBox_TypeDef;
00164
00165 typedef struct
00166 {
00167   vu32 RIR;
00168   vu32 RDTR;
00169   vu32 RDLR;
00170   vu32 RDHR;
00171 } CAN_FIFOMailBox_TypeDef;
00172
00173 typedef struct
00174 {
00175   vu32 FR1;
00176   vu32 FR2;
00177 } CAN_FilterRegister_TypeDef;
00178
00179 typedef struct
00180 {
00181   vu32 MCR;
00182   vu32 MSR;
00183   vu32 TSR;
00184   vu32 RF0R;
00185   vu32 RF1R;
00186   vu32 IER;
00187   vu32 ESR;
00188   vu32 BTR;
00189   u32  RESERVED0[88];
00190   CAN_TxMailBox_TypeDef sTxMailBox[3];
00191   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
00192   u32  RESERVED1[12];
00193   vu32 FMR;
00194   vu32 FM1R;
00195   u32  RESERVED2;
00196   vu32 FS1R;
00197   u32  RESERVED3;
00198   vu32 FFA1R;
00199   u32  RESERVED4;
00200   vu32 FA1R;
00201   u32  RESERVED5[8];
00202   CAN_FilterRegister_TypeDef sFilterRegister[14];
00203 } CAN_TypeDef;
00204
00205 /*------------------------ CRC calculation unit ------------------------------*/
00206 typedef struct
00207 {
00208   vu32 DR;
00209   vu8  IDR;
00210   u8   RESERVED0;
00211   u16  RESERVED1;
00212   vu32 CR;
00213 } CRC_TypeDef;
00214
00215
00216 /*------------------------ Digital to Analog Converter -----------------------*/
00217 typedef struct
00218 {
00219   vu32 CR;
00220   vu32 SWTRIGR;
00221   vu32 DHR12R1;
00222   vu32 DHR12L1;
00223   vu32 DHR8R1;
00224   vu32 DHR12R2;
00225   vu32 DHR12L2;
00226   vu32 DHR8R2;
00227   vu32 DHR12RD;
00228   vu32 DHR12LD;
00229   vu32 DHR8RD;
00230   vu32 DOR1;
00231   vu32 DOR2;
00232 } DAC_TypeDef;
00233
00234 /*------------------------ Debug MCU -----------------------------------------*/
00235 typedef struct
00236 {
00237   vu32 IDCODE;
00238   vu32 CR;
00239 }DBGMCU_TypeDef;
00240
00241 /*------------------------ DMA Controller ------------------------------------*/
00242 typedef struct
00243 {
00244   vu32 CCR;
00245   vu32 CNDTR;
00246   vu32 CPAR;
00247   vu32 CMAR;
00248 } DMA_Channel_TypeDef;
00249
00250 typedef struct
00251 {
00252   vu32 ISR;
00253   vu32 IFCR;
00254 } DMA_TypeDef;
00255
00256 /*------------------------ External Interrupt/Event Controller ---------------*/
00257 typedef struct
00258 {
00259   vu32 IMR;
00260   vu32 EMR;
00261   vu32 RTSR;
00262   vu32 FTSR;
00263   vu32 SWIER;
00264   vu32 PR;
00265 } EXTI_TypeDef;
00266
00267 /*------------------------ FLASH and Option Bytes Registers ------------------*/
00268 typedef struct
00269 {
00270   vu32 ACR;
00271   vu32 KEYR;
00272   vu32 OPTKEYR;
00273   vu32 SR;
00274   vu32 CR;
00275   vu32 AR;
00276   vu32 RESERVED;
00277   vu32 OBR;
00278   vu32 WRPR;
00279 } FLASH_TypeDef;
00280
00281 typedef struct
00282 {
00283   vu16 RDP;
00284   vu16 USER;
00285   vu16 Data0;
00286   vu16 Data1;
00287   vu16 WRP0;
00288   vu16 WRP1;
00289   vu16 WRP2;
00290   vu16 WRP3;
00291 } OB_TypeDef;
00292
00293 /*------------------------ Flexible Static Memory Controller -----------------*/
00294 typedef struct
00295 {
00296   vu32 BTCR[8];
00297 } FSMC_Bank1_TypeDef;
00298
00299 typedef struct
00300 {
00301   vu32 BWTR[7];
00302 } FSMC_Bank1E_TypeDef;
00303
00304 typedef struct
00305 {
00306   vu32 PCR2;
00307   vu32 SR2;
00308   vu32 PMEM2;
00309   vu32 PATT2;
00310   u32  RESERVED0;
00311   vu32 ECCR2;
00312 } FSMC_Bank2_TypeDef;
00313
00314 typedef struct
00315 {
00316   vu32 PCR3;
00317   vu32 SR3;
00318   vu32 PMEM3;
00319   vu32 PATT3;
00320   u32  RESERVED0;
00321   vu32 ECCR3;
00322 } FSMC_Bank3_TypeDef;
00323
00324 typedef struct
00325 {
00326   vu32 PCR4;
00327   vu32 SR4;
00328   vu32 PMEM4;
00329   vu32 PATT4;
00330   vu32 PIO4;
00331 } FSMC_Bank4_TypeDef;
00332
00333 /*------------------------ General Purpose and Alternate Function IO ---------*/
00334 typedef struct
00335 {
00336   vu32 CRL;
00337   vu32 CRH;
00338   vu32 IDR;
00339   vu32 ODR;
00340   vu32 BSRR;
00341   vu32 BRR;
00342   vu32 LCKR;
00343 } GPIO_TypeDef;
00344
00345 typedef struct
00346 {
00347   vu32 EVCR;
00348   vu32 MAPR;
00349   vu32 EXTICR[4];
00350 } AFIO_TypeDef;
00351
00352 /*------------------------ Inter-integrated Circuit Interface ----------------*/
00353 typedef struct
00354 {
00355   vu16 CR1;
00356   u16  RESERVED0;
00357   vu16 CR2;
00358   u16  RESERVED1;
00359   vu16 OAR1;
00360   u16  RESERVED2;
00361   vu16 OAR2;
00362   u16  RESERVED3;
00363   vu16 DR;
00364   u16  RESERVED4;
00365   vu16 SR1;
00366   u16  RESERVED5;
00367   vu16 SR2;
00368   u16  RESERVED6;
00369   vu16 CCR;
00370   u16  RESERVED7;
00371   vu16 TRISE;
00372   u16  RESERVED8;
00373 } I2C_TypeDef;
00374
00375 /*------------------------ Independent WATCHDOG ------------------------------*/
00376 typedef struct
00377 {
00378   vu32 KR;
00379   vu32 PR;
00380   vu32 RLR;
00381   vu32 SR;
00382 } IWDG_TypeDef;
00383
00384 /*------------------------ Nested Vectored Interrupt Controller --------------*/
00385 typedef struct
00386 {
00387   vu32 ISER[2];
00388   u32  RESERVED0[30];
00389   vu32 ICER[2];
00390   u32  RSERVED1[30];
00391   vu32 ISPR[2];
00392   u32  RESERVED2[30];
00393   vu32 ICPR[2];
00394   u32  RESERVED3[30];
00395   vu32 IABR[2];
00396   u32  RESERVED4[62];
00397   vu32 IPR[15];
00398 } NVIC_TypeDef;
00399
00400 typedef struct
00401 {
00402   vuc32 CPUID;
00403   vu32 ICSR;
00404   vu32 VTOR;
00405   vu32 AIRCR;
00406   vu32 SCR;
00407   vu32 CCR;
00408   vu32 SHPR[3];
00409   vu32 SHCSR;
00410   vu32 CFSR;
00411   vu32 HFSR;
00412   vu32 DFSR;
00413   vu32 MMFAR;
00414   vu32 BFAR;
00415   vu32 AFSR;
00416 } SCB_TypeDef;
00417
00418 /*------------------------ Power Control -------------------------------------*/
00419 typedef struct
00420 {
00421   vu32 CR;
00422   vu32 CSR;
00423 } PWR_TypeDef;
00424
00425 /*------------------------ Reset and Clock Control ---------------------------*/
00426 typedef struct
00427 {
00428   vu32 CR;
00429   vu32 CFGR;
00430   vu32 CIR;
00431   vu32 APB2RSTR;
00432   vu32 APB1RSTR;
00433   vu32 AHBENR;
00434   vu32 APB2ENR;
00435   vu32 APB1ENR;
00436   vu32 BDCR;
00437   vu32 CSR;
00438 } RCC_TypeDef;
00439
00440 /*------------------------ Real-Time Clock -----------------------------------*/
00441 typedef struct
00442 {
00443   vu16 CRH;
00444   u16  RESERVED0;
00445   vu16 CRL;
00446   u16  RESERVED1;
00447   vu16 PRLH;
00448   u16  RESERVED2;
00449   vu16 PRLL;
00450   u16  RESERVED3;
00451   vu16 DIVH;
00452   u16  RESERVED4;
00453   vu16 DIVL;
00454   u16  RESERVED5;
00455   vu16 CNTH;
00456   u16  RESERVED6;
00457   vu16 CNTL;
00458   u16  RESERVED7;
00459   vu16 ALRH;
00460   u16  RESERVED8;
00461   vu16 ALRL;
00462   u16  RESERVED9;
00463 } RTC_TypeDef;
00464
00465 /*------------------------ SD host Interface ---------------------------------*/
00466 typedef struct
00467 {
00468   vu32 POWER;
00469   vu32 CLKCR;
00470   vu32 ARG;
00471   vu32 CMD;
00472   vuc32 RESPCMD;
00473   vuc32 RESP1;
00474   vuc32 RESP2;
00475   vuc32 RESP3;
00476   vuc32 RESP4;
00477   vu32 DTIMER;
00478   vu32 DLEN;
00479   vu32 DCTRL;
00480   vuc32 DCOUNT;
00481   vuc32 STA;
00482   vu32 ICR;
00483   vu32 MASK;
00484   u32  RESERVED0[2];
00485   vuc32 FIFOCNT;
00486   u32  RESERVED1[13];
00487   vu32 FIFO;
00488 } SDIO_TypeDef;
00489
00490 /*------------------------ Serial Peripheral Interface -----------------------*/
00491 typedef struct
00492 {
00493   vu16 CR1;
00494   u16  RESERVED0;
00495   vu16 CR2;
00496   u16  RESERVED1;
00497   vu16 SR;
00498   u16  RESERVED2;
00499   vu16 DR;
00500   u16  RESERVED3;
00501   vu16 CRCPR;
00502   u16  RESERVED4;
00503   vu16 RXCRCR;
00504   u16  RESERVED5;
00505   vu16 TXCRCR;
00506   u16  RESERVED6;
00507   vu16 I2SCFGR;
00508   u16  RESERVED7;
00509   vu16 I2SPR;
00510   u16  RESERVED8;
00511 } SPI_TypeDef;
00512
00513 /*------------------------ SystemTick ----------------------------------------*/
00514 typedef struct
00515 {
00516   vu32 CTRL;
00517   vu32 LOAD;
00518   vu32 VAL;
00519   vuc32 CALIB;
00520 } SysTick_TypeDef;
00521
00522 /*------------------------ TIM -----------------------------------------------*/
00523 typedef struct
00524 {
00525   vu16 CR1;
00526   u16  RESERVED0;
00527   vu16 CR2;
00528   u16  RESERVED1;
00529   vu16 SMCR;
00530   u16  RESERVED2;
00531   vu16 DIER;
00532   u16  RESERVED3;
00533   vu16 SR;
00534   u16  RESERVED4;
00535   vu16 EGR;
00536   u16  RESERVED5;
00537   vu16 CCMR1;
00538   u16  RESERVED6;
00539   vu16 CCMR2;
00540   u16  RESERVED7;
00541   vu16 CCER;
00542   u16  RESERVED8;
00543   vu16 CNT;
00544   u16  RESERVED9;
00545   vu16 PSC;
00546   u16  RESERVED10;
00547   vu16 ARR;
00548   u16  RESERVED11;
00549   vu16 RCR;
00550   u16  RESERVED12;
00551   vu16 CCR1;
00552   u16  RESERVED13;
00553   vu16 CCR2;
00554   u16  RESERVED14;
00555   vu16 CCR3;
00556   u16  RESERVED15;
00557   vu16 CCR4;
00558   u16  RESERVED16;
00559   vu16 BDTR;
00560   u16  RESERVED17;
00561   vu16 DCR;
00562   u16  RESERVED18;
00563   vu16 DMAR;
00564   u16  RESERVED19;
00565 } TIM_TypeDef;
00566
00567 /*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
00568 typedef struct
00569 {
00570   vu16 SR;
00571   u16  RESERVED0;
00572   vu16 DR;
00573   u16  RESERVED1;
00574   vu16 BRR;
00575   u16  RESERVED2;
00576   vu16 CR1;
00577   u16  RESERVED3;
00578   vu16 CR2;
00579   u16  RESERVED4;
00580   vu16 CR3;
00581   u16  RESERVED5;
00582   vu16 GTPR;
00583   u16  RESERVED6;
00584 } USART_TypeDef;
00585
00586 /*------------------------ Window WATCHDOG -----------------------------------*/
00587 typedef struct
00588 {
00589   vu32 CR;
00590   vu32 CFR;
00591   vu32 SR;
00592 } WWDG_TypeDef;
00593
00594 /******************************************************************************/
00595 /*                         Peripheral memory map                              */
00596 /******************************************************************************/
00597 /* Peripheral and SRAM base address in the alias region */
00598 #define PERIPH_BB_BASE        ((u32)0x42000000)
00599 #define SRAM_BB_BASE          ((u32)0x22000000)
00600
00601 /* Peripheral and SRAM base address in the bit-band region */
00602 #define SRAM_BASE             ((u32)0x20000000)
00603 #define PERIPH_BASE           ((u32)0x40000000)
00604
00605 /* FSMC registers base address */
00606 #define FSMC_R_BASE           ((u32)0xA0000000)
00607
00608 /* Peripheral memory map */
00609 #define APB1PERIPH_BASE       PERIPH_BASE
00610 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
00611 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
00612
00613 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
00614 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
00615 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
00616 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
00617 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
00618 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
00619 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
00620 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
00621 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
00622 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
00623 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
00624 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
00625 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
00626 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
00627 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
00628 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
00629 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
00630 #define CAN_BASE              (APB1PERIPH_BASE + 0x6400)
00631 #define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
00632 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
00633 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
00634
00635 #define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
00636 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
00637 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
00638 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
00639 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
00640 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
00641 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
00642 #define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
00643 #define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
00644 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
00645 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
00646 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
00647 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
00648 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
00649 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
00650 #define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
00651
00652 #define SDIO_BASE             (PERIPH_BASE + 0x18000)
00653
00654 #define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
00655 #define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
00656 #define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
00657 #define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
00658 #define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
00659 #define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
00660 #define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
00661 #define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
00662 #define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
00663 #define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
00664 #define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
00665 #define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
00666 #define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
00667 #define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
00668 #define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
00669 #define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
00670
00671 /* Flash registers base address */
00672 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000)
00673 /* Flash Option Bytes base address */
00674 #define OB_BASE               ((u32)0x1FFFF800)
00675
00676 /* FSMC Bankx registers base address */
00677 #define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
00678 #define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
00679 #define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
00680 #define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
00681 #define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
00682
00683 /* Debug MCU registers base address */
00684 #define DBGMCU_BASE          ((u32)0xE0042000)
00685
00686 /* System Control Space memory map */
00687 #define SCS_BASE              ((u32)0xE000E000)
00688
00689 #define SysTick_BASE          (SCS_BASE + 0x0010)
00690 #define NVIC_BASE             (SCS_BASE + 0x0100)
00691 #define SCB_BASE              (SCS_BASE + 0x0D00)
00692
00693 /******************************************************************************/
00694 /*                         Peripheral declaration                             */
00695 /******************************************************************************/
00696
00697 /*------------------------ Non Debug Mode ------------------------------------*/
00698 #ifndef DEBUG
00699 #ifdef _TIM2
00700   #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
00701 #endif /*_TIM2 */
00702
00703 #ifdef _TIM3
00704   #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
00705 #endif /*_TIM3 */
00706
00707 #ifdef _TIM4
00708   #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
00709 #endif /*_TIM4 */
00710
00711 #ifdef _TIM5
00712   #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
00713 #endif /*_TIM5 */
00714
00715 #ifdef _TIM6
00716   #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
00717 #endif /*_TIM6 */
00718
00719 #ifdef _TIM7
00720   #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
00721 #endif /*_TIM7 */
00722
00723 #ifdef _RTC
00724   #define RTC                 ((RTC_TypeDef *) RTC_BASE)
00725 #endif /*_RTC */
00726
00727 #ifdef _WWDG
00728   #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
00729 #endif /*_WWDG */
00730
00731 #ifdef _IWDG
00732   #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
00733 #endif /*_IWDG */
00734
00735 #ifdef _SPI2
00736   #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
00737 #endif /*_SPI2 */
00738
00739 #ifdef _SPI3
00740   #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
00741 #endif /*_SPI3 */
00742
00743 #ifdef _USART2
00744   #define USART2              ((USART_TypeDef *) USART2_BASE)
00745 #endif /*_USART2 */
00746
00747 #ifdef _USART3
00748   #define USART3              ((USART_TypeDef *) USART3_BASE)
00749 #endif /*_USART3 */
00750
00751 #ifdef _UART4
00752   #define UART4              ((USART_TypeDef *) UART4_BASE)
00753 #endif /*_UART4 */
00754
00755 #ifdef _UART5
00756   #define UART5              ((USART_TypeDef *) UART5_BASE)
00757 #endif /*_USART5 */
00758
00759 #ifdef _I2C1
00760   #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
00761 #endif /*_I2C1 */
00762
00763 #ifdef _I2C2
00764   #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
00765 #endif /*_I2C2 */
00766
00767 #ifdef _CAN
00768   #define CAN                 ((CAN_TypeDef *) CAN_BASE)
00769 #endif /*_CAN */
00770
00771 #ifdef _BKP
00772   #define BKP                 ((BKP_TypeDef *) BKP_BASE)
00773 #endif /*_BKP */
00774
00775 #ifdef _PWR
00776   #define PWR                 ((PWR_TypeDef *) PWR_BASE)
00777 #endif /*_PWR */
00778
00779 #ifdef _DAC
00780   #define DAC                 ((DAC_TypeDef *) DAC_BASE)
00781 #endif /*_DAC */
00782
00783 #ifdef _AFIO
00784   #define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
00785 #endif /*_AFIO */
00786
00787 #ifdef _EXTI
00788   #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
00789 #endif /*_EXTI */
00790
00791 #ifdef _GPIOA
00792   #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
00793 #endif /*_GPIOA */
00794
00795 #ifdef _GPIOB
00796   #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
00797 #endif /*_GPIOB */
00798
00799 #ifdef _GPIOC
00800   #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
00801 #endif /*_GPIOC */
00802
00803 #ifdef _GPIOD
00804   #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
00805 #endif /*_GPIOD */
00806
00807 #ifdef _GPIOE
00808   #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
00809 #endif /*_GPIOE */
00810
00811 #ifdef _GPIOF
00812   #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
00813 #endif /*_GPIOF */
00814
00815 #ifdef _GPIOG
00816   #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
00817 #endif /*_GPIOG */
00818
00819 #ifdef _ADC1
00820   #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
00821 #endif /*_ADC1 */
00822
00823 #ifdef _ADC2
00824   #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
00825 #endif /*_ADC2 */
00826
00827 #ifdef _TIM1
00828   #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
00829 #endif /*_TIM1 */
00830
00831 #ifdef _SPI1
00832   #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
00833 #endif /*_SPI1 */
00834
00835 #ifdef _TIM8
00836   #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
00837 #endif /*_TIM8 */
00838
00839 #ifdef _USART1
00840   #define USART1              ((USART_TypeDef *) USART1_BASE)
00841 #endif /*_USART1 */
00842
00843 #ifdef _ADC3
00844   #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
00845 #endif /*_ADC3 */
00846
00847 #ifdef _SDIO
00848   #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
00849 #endif /*_SDIO */
00850
00851 #ifdef _DMA
00852   #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
00853   #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
00854 #endif /*_DMA */
00855
00856 #ifdef _DMA1_Channel1
00857   #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
00858 #endif /*_DMA1_Channel1 */
00859
00860 #ifdef _DMA1_Channel2
00861   #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
00862 #endif /*_DMA1_Channel2 */
00863
00864 #ifdef _DMA1_Channel3
00865   #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
00866 #endif /*_DMA1_Channel3 */
00867
00868 #ifdef _DMA1_Channel4
00869   #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
00870 #endif /*_DMA1_Channel4 */
00871
00872 #ifdef _DMA1_Channel5
00873   #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
00874 #endif /*_DMA1_Channel5 */
00875
00876 #ifdef _DMA1_Channel6
00877   #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
00878 #endif /*_DMA1_Channel6 */
00879
00880 #ifdef _DMA1_Channel7
00881   #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
00882 #endif /*_DMA1_Channel7 */
00883
00884 #ifdef _DMA2_Channel1
00885   #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
00886 #endif /*_DMA2_Channel1 */
00887
00888 #ifdef _DMA2_Channel2
00889   #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
00890 #endif /*_DMA2_Channel2 */
00891
00892 #ifdef _DMA2_Channel3
00893   #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
00894 #endif /*_DMA2_Channel3 */
00895
00896 #ifdef _DMA2_Channel4
00897   #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
00898 #endif /*_DMA2_Channel4 */
00899
00900 #ifdef _DMA2_Channel5
00901   #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
00902 #endif /*_DMA2_Channel5 */
00903
00904 #ifdef _RCC
00905   #define RCC                 ((RCC_TypeDef *) RCC_BASE)
00906 #endif /*_RCC */
00907
00908 #ifdef _CRC
00909   #define CRC                 ((CRC_TypeDef *) CRC_BASE)
00910 #endif /*_CRC */
00911
00912 #ifdef _FLASH
00913   #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
00914   #define OB                  ((OB_TypeDef *) OB_BASE)
00915 #endif /*_FLASH */
00916
00917 #ifdef _FSMC
00918   #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
00919   #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
00920   #define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
00921   #define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
00922   #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
00923 #endif /*_FSMC */
00924
00925 #ifdef _DBGMCU
00926   #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
00927 #endif /*_DBGMCU */
00928
00929 #ifdef _SysTick
00930   #define SysTick             ((SysTick_TypeDef *) SysTick_BASE)
00931 #endif /*_SysTick */
00932
00933 #ifdef _NVIC
00934   #define NVIC                ((NVIC_TypeDef *) NVIC_BASE)
00935   #define SCB                 ((SCB_TypeDef *) SCB_BASE)
00936 #endif /*_NVIC */
00937
00938 /*------------------------ Debug Mode ----------------------------------------*/
00939 #else   /* DEBUG */
00940 #ifdef _TIM2
00941   EXT TIM_TypeDef             *TIM2;
00942 #endif /*_TIM2 */
00943
00944 #ifdef _TIM3
00945   EXT TIM_TypeDef             *TIM3;
00946 #endif /*_TIM3 */
00947
00948 #ifdef _TIM4
00949   EXT TIM_TypeDef             *TIM4;
00950 #endif /*_TIM4 */
00951
00952 #ifdef _TIM5
00953   EXT TIM_TypeDef             *TIM5;
00954 #endif /*_TIM5 */
00955
00956 #ifdef _TIM6
00957   EXT TIM_TypeDef             *TIM6;
00958 #endif /*_TIM6 */
00959
00960 #ifdef _TIM7
00961   EXT TIM_TypeDef             *TIM7;
00962 #endif /*_TIM7 */
00963
00964 #ifdef _RTC
00965   EXT RTC_TypeDef             *RTC;
00966 #endif /*_RTC */
00967
00968 #ifdef _WWDG
00969   EXT WWDG_TypeDef            *WWDG;
00970 #endif /*_WWDG */
00971
00972 #ifdef _IWDG
00973   EXT IWDG_TypeDef            *IWDG;
00974 #endif /*_IWDG */
00975
00976 #ifdef _SPI2
00977   EXT SPI_TypeDef             *SPI2;
00978 #endif /*_SPI2 */
00979
00980 #ifdef _SPI3
00981   EXT SPI_TypeDef             *SPI3;
00982 #endif /*_SPI3 */
00983
00984 #ifdef _USART2
00985   EXT USART_TypeDef           *USART2;
00986 #endif /*_USART2 */
00987
00988 #ifdef _USART3
00989   EXT USART_TypeDef           *USART3;
00990 #endif /*_USART3 */
00991
00992 #ifdef _UART4
00993   EXT USART_TypeDef           *UART4;
00994 #endif /*_UART4 */
00995
00996 #ifdef _UART5
00997   EXT USART_TypeDef           *UART5;
00998 #endif /*_UART5 */
00999
01000 #ifdef _I2C1
01001   EXT I2C_TypeDef             *I2C1;
01002 #endif /*_I2C1 */
01003
01004 #ifdef _I2C2
01005   EXT I2C_TypeDef             *I2C2;
01006 #endif /*_I2C2 */
01007
01008 #ifdef _CAN
01009   EXT CAN_TypeDef             *CAN;
01010 #endif /*_CAN */
01011
01012 #ifdef _BKP
01013   EXT BKP_TypeDef             *BKP;
01014 #endif /*_BKP */
01015
01016 #ifdef _PWR
01017   EXT PWR_TypeDef             *PWR;
01018 #endif /*_PWR */
01019
01020 #ifdef _DAC
01021   EXT DAC_TypeDef             *DAC;
01022 #endif /*_DAC */
01023
01024 #ifdef _AFIO
01025   EXT AFIO_TypeDef            *AFIO;
01026 #endif /*_AFIO */
01027
01028 #ifdef _EXTI
01029   EXT EXTI_TypeDef            *EXTI;
01030 #endif /*_EXTI */
01031
01032 #ifdef _GPIOA
01033   EXT GPIO_TypeDef            *GPIOA;
01034 #endif /*_GPIOA */
01035
01036 #ifdef _GPIOB
01037   EXT GPIO_TypeDef            *GPIOB;
01038 #endif /*_GPIOB */
01039
01040 #ifdef _GPIOC
01041   EXT GPIO_TypeDef            *GPIOC;
01042 #endif /*_GPIOC */
01043
01044 #ifdef _GPIOD
01045   EXT GPIO_TypeDef            *GPIOD;
01046 #endif /*_GPIOD */
01047
01048 #ifdef _GPIOE
01049   EXT GPIO_TypeDef            *GPIOE;
01050 #endif /*_GPIOE */
01051
01052 #ifdef _GPIOF
01053   EXT GPIO_TypeDef            *GPIOF;
01054 #endif /*_GPIOF */
01055
01056 #ifdef _GPIOG
01057   EXT GPIO_TypeDef            *GPIOG;
01058 #endif /*_GPIOG */
01059
01060 #ifdef _ADC1
01061   EXT ADC_TypeDef             *ADC1;
01062 #endif /*_ADC1 */
01063
01064 #ifdef _ADC2
01065   EXT ADC_TypeDef             *ADC2;
01066 #endif /*_ADC2 */
01067
01068 #ifdef _TIM1
01069   EXT TIM_TypeDef             *TIM1;
01070 #endif /*_TIM1 */
01071
01072 #ifdef _SPI1
01073   EXT SPI_TypeDef             *SPI1;
01074 #endif /*_SPI1 */
01075
01076 #ifdef _TIM8
01077   EXT TIM_TypeDef             *TIM8;
01078 #endif /*_TIM8 */
01079
01080 #ifdef _USART1
01081   EXT USART_TypeDef           *USART1;
01082 #endif /*_USART1 */
01083
01084 #ifdef _ADC3
01085   EXT ADC_TypeDef             *ADC3;
01086 #endif /*_ADC3 */
01087
01088 #ifdef _SDIO
01089   EXT SDIO_TypeDef            *SDIO;
01090 #endif /*_SDIO */
01091
01092 #ifdef _DMA
01093   EXT DMA_TypeDef             *DMA1;
01094   EXT DMA_TypeDef             *DMA2;
01095 #endif /*_DMA */
01096
01097 #ifdef _DMA1_Channel1
01098   EXT DMA_Channel_TypeDef     *DMA1_Channel1;
01099 #endif /*_DMA1_Channel1 */
01100
01101 #ifdef _DMA1_Channel2
01102   EXT DMA_Channel_TypeDef     *DMA1_Channel2;
01103 #endif /*_DMA1_Channel2 */
01104
01105 #ifdef _DMA1_Channel3
01106   EXT DMA_Channel_TypeDef     *DMA1_Channel3;
01107 #endif /*_DMA1_Channel3 */
01108
01109 #ifdef _DMA1_Channel4
01110   EXT DMA_Channel_TypeDef     *DMA1_Channel4;
01111 #endif /*_DMA1_Channel4 */
01112
01113 #ifdef _DMA1_Channel5
01114   EXT DMA_Channel_TypeDef     *DMA1_Channel5;
01115 #endif /*_DMA1_Channel5 */
01116
01117 #ifdef _DMA1_Channel6
01118   EXT DMA_Channel_TypeDef     *DMA1_Channel6;
01119 #endif /*_DMA1_Channel6 */
01120
01121 #ifdef _DMA1_Channel7
01122   EXT DMA_Channel_TypeDef     *DMA1_Channel7;
01123 #endif /*_DMA1_Channel7 */
01124
01125 #ifdef _DMA2_Channel1
01126   EXT DMA_Channel_TypeDef     *DMA2_Channel1;
01127 #endif /*_DMA2_Channel1 */
01128
01129 #ifdef _DMA2_Channel2
01130   EXT DMA_Channel_TypeDef     *DMA2_Channel2;
01131 #endif /*_DMA2_Channel2 */
01132
01133 #ifdef _DMA2_Channel3
01134   EXT DMA_Channel_TypeDef     *DMA2_Channel3;
01135 #endif /*_DMA2_Channel3 */
01136
01137 #ifdef _DMA2_Channel4
01138   EXT DMA_Channel_TypeDef     *DMA2_Channel4;
01139 #endif /*_DMA2_Channel4 */
01140
01141 #ifdef _DMA2_Channel5
01142   EXT DMA_Channel_TypeDef     *DMA2_Channel5;
01143 #endif /*_DMA2_Channel5 */
01144
01145 #ifdef _RCC
01146   EXT RCC_TypeDef             *RCC;
01147 #endif /*_RCC */
01148
01149 #ifdef _CRC
01150   EXT CRC_TypeDef             *CRC;
01151 #endif /*_CRC */
01152
01153 #ifdef _FLASH
01154   EXT FLASH_TypeDef            *FLASH;
01155   EXT OB_TypeDef               *OB;
01156 #endif /*_FLASH */
01157
01158 #ifdef _FSMC
01159   EXT FSMC_Bank1_TypeDef      *FSMC_Bank1;
01160   EXT FSMC_Bank1E_TypeDef     *FSMC_Bank1E;
01161   EXT FSMC_Bank2_TypeDef      *FSMC_Bank2;
01162   EXT FSMC_Bank3_TypeDef      *FSMC_Bank3;
01163   EXT FSMC_Bank4_TypeDef      *FSMC_Bank4;
01164 #endif /*_FSMC */
01165
01166 #ifdef _DBGMCU
01167   EXT DBGMCU_TypeDef          *DBGMCU;
01168 #endif /*_DBGMCU */
01169
01170 #ifdef _SysTick
01171   EXT SysTick_TypeDef         *SysTick;
01172 #endif /*_SysTick */
01173
01174 #ifdef _NVIC
01175   EXT NVIC_TypeDef            *NVIC;
01176   EXT SCB_TypeDef             *SCB;
01177 #endif /*_NVIC */
01178
01179 #endif  /* DEBUG */
01180
01181 /* Exported constants --------------------------------------------------------*/
01182 /******************************************************************************/
01183 /*                                                                            */
01184 /*                          CRC calculation unit                              */
01185 /*                                                                            */
01186 /******************************************************************************/
01187
01188 /*******************  Bit definition for CRC_DR register  *********************/
01189 #define  CRC_DR_DR                           ((u32)0xFFFFFFFF) /* Data register bits */
01190
01191
01192 /*******************  Bit definition for CRC_IDR register  ********************/
01193 #define  CRC_IDR_IDR                         ((u8)0xFF)        /* General-purpose 8-bit data register bits */
01194
01195
01196 /********************  Bit definition for CRC_CR register  ********************/
01197 #define  CRC_CR_RESET                        ((u8)0x01)        /* RESET bit */
01198
01199
01200
01201 /******************************************************************************/
01202 /*                                                                            */
01203 /*                             Power Control                                  */
01204 /*                                                                            */
01205 /******************************************************************************/
01206
01207 /********************  Bit definition for PWR_CR register  ********************/
01208 #define  PWR_CR_LPDS                         ((u16)0x0001)     /* Low-Power Deepsleep */
01209 #define  PWR_CR_PDDS                         ((u16)0x0002)     /* Power Down Deepsleep */
01210 #define  PWR_CR_CWUF                         ((u16)0x0004)     /* Clear Wakeup Flag */
01211 #define  PWR_CR_CSBF                         ((u16)0x0008)     /* Clear Standby Flag */
01212 #define  PWR_CR_PVDE                         ((u16)0x0010)     /* Power Voltage Detector Enable */
01213
01214 #define  PWR_CR_PLS                          ((u16)0x00E0)     /* PLS[2:0] bits (PVD Level Selection) */
01215 #define  PWR_CR_PLS_0                        ((u16)0x0020)     /* Bit 0 */
01216 #define  PWR_CR_PLS_1                        ((u16)0x0040)     /* Bit 1 */
01217 #define  PWR_CR_PLS_2                        ((u16)0x0080)     /* Bit 2 */
01218
01219 /* PVD level configuration */
01220 #define  PWR_CR_PLS_2V2                      ((u16)0x0000)     /* PVD level 2.2V */
01221 #define  PWR_CR_PLS_2V3                      ((u16)0x0020)     /* PVD level 2.3V */
01222 #define  PWR_CR_PLS_2V4                      ((u16)0x0040)     /* PVD level 2.4V */
01223 #define  PWR_CR_PLS_2V5                      ((u16)0x0060)     /* PVD level 2.5V */
01224 #define  PWR_CR_PLS_2V6                      ((u16)0x0080)     /* PVD level 2.6V */
01225 #define  PWR_CR_PLS_2V7                      ((u16)0x00A0)     /* PVD level 2.7V */
01226 #define  PWR_CR_PLS_2V8                      ((u16)0x00C0)     /* PVD level 2.8V */
01227 #define  PWR_CR_PLS_2V9                      ((u16)0x00E0)     /* PVD level 2.9V */
01228
01229 #define  PWR_CR_DBP                          ((u16)0x0100)     /* Disable Backup Domain write protection */
01230
01231
01232 /*******************  Bit definition for PWR_CSR register  ********************/
01233 #define  PWR_CSR_WUF                         ((u16)0x0001)     /* Wakeup Flag */
01234 #define  PWR_CSR_SBF                         ((u16)0x0002)     /* Standby Flag */
01235 #define  PWR_CSR_PVDO                        ((u16)0x0004)     /* PVD Output */
01236 #define  PWR_CSR_EWUP                        ((u16)0x0100)     /* Enable WKUP pin */
01237
01238
01239
01240 /******************************************************************************/
01241 /*                                                                            */
01242 /*                            Backup registers                                */
01243 /*                                                                            */
01244 /******************************************************************************/
01245
01246 /*******************  Bit definition for BKP_DR1 register  ********************/
01247 #define  BKP_DR1_D                           ((u16)0xFFFF)     /* Backup data */
01248
01249
01250 /*******************  Bit definition for BKP_DR2 register  ********************/
01251 #define  BKP_DR2_D                           ((u16)0xFFFF)     /* Backup data */
01252
01253
01254 /*******************  Bit definition for BKP_DR3 register  ********************/
01255 #define  BKP_DR3_D                           ((u16)0xFFFF)     /* Backup data */
01256
01257
01258 /*******************  Bit definition for BKP_DR4 register  ********************/
01259 #define  BKP_DR4_D                           ((u16)0xFFFF)     /* Backup data */
01260
01261
01262 /*******************  Bit definition for BKP_DR5 register  ********************/
01263 #define  BKP_DR5_D                           ((u16)0xFFFF)     /* Backup data */
01264
01265
01266 /*******************  Bit definition for BKP_DR6 register  ********************/
01267 #define  BKP_DR6_D                           ((u16)0xFFFF)     /* Backup data */
01268
01269
01270 /*******************  Bit definition for BKP_DR7 register  ********************/
01271 #define  BKP_DR7_D                           ((u16)0xFFFF)     /* Backup data */
01272
01273
01274 /*******************  Bit definition for BKP_DR8 register  ********************/
01275 #define  BKP_DR8_D                           ((u16)0xFFFF)     /* Backup data */
01276
01277
01278 /*******************  Bit definition for BKP_DR9 register  ********************/
01279 #define  BKP_DR9_D                           ((u16)0xFFFF)     /* Backup data */
01280
01281
01282 /*******************  Bit definition for BKP_DR10 register  *******************/
01283 #define  BKP_DR10_D                          ((u16)0xFFFF)     /* Backup data */
01284
01285
01286 /*******************  Bit definition for BKP_DR11 register  *******************/
01287 #define  BKP_DR11_D                          ((u16)0xFFFF)     /* Backup data */
01288
01289
01290 /*******************  Bit definition for BKP_DR12 register  *******************/
01291 #define  BKP_DR12_D                          ((u16)0xFFFF)     /* Backup data */
01292
01293
01294 /*******************  Bit definition for BKP_DR13 register  *******************/
01295 #define  BKP_DR13_D                          ((u16)0xFFFF)     /* Backup data */
01296
01297
01298 /*******************  Bit definition for BKP_DR14 register  *******************/
01299 #define  BKP_DR14_D                          ((u16)0xFFFF)     /* Backup data */
01300
01301
01302 /*******************  Bit definition for BKP_DR15 register  *******************/
01303 #define  BKP_DR15_D                          ((u16)0xFFFF)     /* Backup data */
01304
01305
01306 /*******************  Bit definition for BKP_DR16 register  *******************/
01307 #define  BKP_DR16_D                          ((u16)0xFFFF)     /* Backup data */
01308
01309
01310 /*******************  Bit definition for BKP_DR17 register  *******************/
01311 #define  BKP_DR17_D                          ((u16)0xFFFF)     /* Backup data */
01312
01313
01314 /******************  Bit definition for BKP_DR18 register  ********************/
01315 #define  BKP_DR18_D                          ((u16)0xFFFF)     /* Backup data */
01316
01317
01318 /*******************  Bit definition for BKP_DR19 register  *******************/
01319 #define  BKP_DR19_D                          ((u16)0xFFFF)     /* Backup data */
01320
01321
01322 /*******************  Bit definition for BKP_DR20 register  *******************/
01323 #define  BKP_DR20_D                          ((u16)0xFFFF)     /* Backup data */
01324
01325
01326 /*******************  Bit definition for BKP_DR21 register  *******************/
01327 #define  BKP_DR21_D                          ((u16)0xFFFF)     /* Backup data */
01328
01329
01330 /*******************  Bit definition for BKP_DR22 register  *******************/
01331 #define  BKP_DR22_D                          ((u16)0xFFFF)     /* Backup data */
01332
01333
01334 /*******************  Bit definition for BKP_DR23 register  *******************/
01335 #define  BKP_DR23_D                          ((u16)0xFFFF)     /* Backup data */
01336
01337
01338 /*******************  Bit definition for BKP_DR24 register  *******************/
01339 #define  BKP_DR24_D                          ((u16)0xFFFF)     /* Backup data */
01340
01341
01342 /*******************  Bit definition for BKP_DR25 register  *******************/
01343 #define  BKP_DR25_D                          ((u16)0xFFFF)     /* Backup data */
01344
01345
01346 /*******************  Bit definition for BKP_DR26 register  *******************/
01347 #define  BKP_DR26_D                          ((u16)0xFFFF)     /* Backup data */
01348
01349
01350 /*******************  Bit definition for BKP_DR27 register  *******************/
01351 #define  BKP_DR27_D                          ((u16)0xFFFF)     /* Backup data */
01352
01353
01354 /*******************  Bit definition for BKP_DR28 register  *******************/
01355 #define  BKP_DR28_D                          ((u16)0xFFFF)     /* Backup data */
01356
01357
01358 /*******************  Bit definition for BKP_DR29 register  *******************/
01359 #define  BKP_DR29_D                          ((u16)0xFFFF)     /* Backup data */
01360
01361
01362 /*******************  Bit definition for BKP_DR30 register  *******************/
01363 #define  BKP_DR30_D                          ((u16)0xFFFF)     /* Backup data */
01364
01365
01366 /*******************  Bit definition for BKP_DR31 register  *******************/
01367 #define  BKP_DR31_D                          ((u16)0xFFFF)     /* Backup data */
01368
01369
01370 /*******************  Bit definition for BKP_DR32 register  *******************/
01371 #define  BKP_DR32_D                          ((u16)0xFFFF)     /* Backup data */
01372
01373
01374 /*******************  Bit definition for BKP_DR33 register  *******************/
01375 #define  BKP_DR33_D                          ((u16)0xFFFF)     /* Backup data */
01376
01377
01378 /*******************  Bit definition for BKP_DR34 register  *******************/
01379 #define  BKP_DR34_D                          ((u16)0xFFFF)     /* Backup data */
01380
01381
01382 /*******************  Bit definition for BKP_DR35 register  *******************/
01383 #define  BKP_DR35_D                          ((u16)0xFFFF)     /* Backup data */
01384
01385
01386 /*******************  Bit definition for BKP_DR36 register  *******************/
01387 #define  BKP_DR36_D                          ((u16)0xFFFF)     /* Backup data */
01388
01389
01390 /*******************  Bit definition for BKP_DR37 register  *******************/
01391 #define  BKP_DR37_D                          ((u16)0xFFFF)     /* Backup data */
01392
01393
01394 /*******************  Bit definition for BKP_DR38 register  *******************/
01395 #define  BKP_DR38_D                          ((u16)0xFFFF)     /* Backup data */
01396
01397
01398 /*******************  Bit definition for BKP_DR39 register  *******************/
01399 #define  BKP_DR39_D                          ((u16)0xFFFF)     /* Backup data */
01400
01401
01402 /*******************  Bit definition for BKP_DR40 register  *******************/
01403 #define  BKP_DR40_D                          ((u16)0xFFFF)     /* Backup data */
01404
01405
01406 /*******************  Bit definition for BKP_DR41 register  *******************/
01407 #define  BKP_DR41_D                          ((u16)0xFFFF)     /* Backup data */
01408
01409
01410 /*******************  Bit definition for BKP_DR42 register  *******************/
01411 #define  BKP_DR42_D                          ((u16)0xFFFF)     /* Backup data */
01412
01413
01414 /******************  Bit definition for BKP_RTCCR register  *******************/
01415 #define  BKP_RTCCR_CAL                       ((u16)0x007F)     /* Calibration value */
01416 #define  BKP_RTCCR_CCO                       ((u16)0x0080)     /* Calibration Clock Output */
01417 #define  BKP_RTCCR_ASOE                      ((u16)0x0100)     /* Alarm or Second Output Enable */
01418 #define  BKP_RTCCR_ASOS                      ((u16)0x0200)     /* Alarm or Second Output Selection */
01419
01420
01421 /********************  Bit definition for BKP_CR register  ********************/
01422 #define  BKP_CR_TPE                          ((u8)0x01)        /* TAMPER pin enable */
01423 #define  BKP_CR_TPAL                         ((u8)0x02)        /* TAMPER pin active level */
01424
01425
01426 /*******************  Bit definition for BKP_CSR register  ********************/
01427 #define  BKP_CSR_CTE                         ((u16)0x0001)     /* Clear Tamper event */
01428 #define  BKP_CSR_CTI                         ((u16)0x0002)     /* Clear Tamper Interrupt */
01429 #define  BKP_CSR_TPIE                        ((u16)0x0004)     /* TAMPER Pin interrupt enable */
01430 #define  BKP_CSR_TEF                         ((u16)0x0100)     /* Tamper Event Flag */
01431 #define  BKP_CSR_TIF                         ((u16)0x0200)     /* Tamper Interrupt Flag */
01432
01433
01434
01435 /******************************************************************************/
01436 /*                                                                            */
01437 /*                         Reset and Clock Control                            */
01438 /*                                                                            */
01439 /******************************************************************************/
01440
01441
01442 /********************  Bit definition for RCC_CR register  ********************/
01443 #define  RCC_CR_HSION                        ((u32)0x00000001)        /* Internal High Speed clock enable */
01444 #define  RCC_CR_HSIRDY                       ((u32)0x00000002)        /* Internal High Speed clock ready flag */
01445 #define  RCC_CR_HSITRIM                      ((u32)0x000000F8)        /* Internal High Speed clock trimming */
01446 #define  RCC_CR_HSICAL                       ((u32)0x0000FF00)        /* Internal High Speed clock Calibration */
01447 #define  RCC_CR_HSEON                        ((u32)0x00010000)        /* External High Speed clock enable */
01448 #define  RCC_CR_HSERDY                       ((u32)0x00020000)        /* External High Speed clock ready flag */
01449 #define  RCC_CR_HSEBYP                       ((u32)0x00040000)        /* External High Speed clock Bypass */
01450 #define  RCC_CR_CSSON                        ((u32)0x00080000)        /* Clock Security System enable */
01451 #define  RCC_CR_PLLON                        ((u32)0x01000000)        /* PLL enable */
01452 #define  RCC_CR_PLLRDY                       ((u32)0x02000000)        /* PLL clock ready flag */
01453
01454
01455 /*******************  Bit definition for RCC_CFGR register  *******************/
01456 #define  RCC_CFGR_SW                         ((u32)0x00000003)        /* SW[1:0] bits (System clock Switch) */
01457 #define  RCC_CFGR_SW_0                       ((u32)0x00000001)        /* Bit 0 */
01458 #define  RCC_CFGR_SW_1                       ((u32)0x00000002)        /* Bit 1 */
01459
01460 /* SW configuration */
01461 #define  RCC_CFGR_SW_HSI                     ((u32)0x00000000)        /* HSI selected as system clock */
01462 #define  RCC_CFGR_SW_HSE                     ((u32)0x00000001)        /* HSE selected as system clock */
01463 #define  RCC_CFGR_SW_PLL                     ((u32)0x00000002)        /* PLL selected as system clock */
01464
01465 #define  RCC_CFGR_SWS                        ((u32)0x0000000C)        /* SWS[1:0] bits (System Clock Switch Status) */
01466 #define  RCC_CFGR_SWS_0                      ((u32)0x00000004)        /* Bit 0 */
01467 #define  RCC_CFGR_SWS_1                      ((u32)0x00000008)        /* Bit 1 */
01468
01469 /* SWS configuration */
01470 #define  RCC_CFGR_SWS_HSI                    ((u32)0x00000000)        /* HSI oscillator used as system clock */
01471 #define  RCC_CFGR_SWS_HSE                    ((u32)0x00000004)        /* HSE oscillator used as system clock */
01472 #define  RCC_CFGR_SWS_PLL                    ((u32)0x00000008)        /* PLL used as system clock */
01473
01474 #define  RCC_CFGR_HPRE                       ((u32)0x000000F0)        /* HPRE[3:0] bits (AHB prescaler) */
01475 #define  RCC_CFGR_HPRE_0                     ((u32)0x00000010)        /* Bit 0 */
01476 #define  RCC_CFGR_HPRE_1                     ((u32)0x00000020)        /* Bit 1 */
01477 #define  RCC_CFGR_HPRE_2                     ((u32)0x00000040)        /* Bit 2 */
01478 #define  RCC_CFGR_HPRE_3                     ((u32)0x00000080)        /* Bit 3 */
01479
01480 /* HPRE configuration */
01481 #define  RCC_CFGR_HPRE_DIV1                  ((u32)0x00000000)        /* SYSCLK not divided */
01482 #define  RCC_CFGR_HPRE_DIV2                  ((u32)0x00000080)        /* SYSCLK divided by 2 */
01483 #define  RCC_CFGR_HPRE_DIV4                  ((u32)0x00000090)        /* SYSCLK divided by 4 */
01484 #define  RCC_CFGR_HPRE_DIV8                  ((u32)0x000000A0)        /* SYSCLK divided by 8 */
01485 #define  RCC_CFGR_HPRE_DIV16                 ((u32)0x000000B0)        /* SYSCLK divided by 16 */
01486 #define  RCC_CFGR_HPRE_DIV64                 ((u32)0x000000C0)        /* SYSCLK divided by 64 */
01487 #define  RCC_CFGR_HPRE_DIV128                ((u32)0x000000D0)        /* SYSCLK divided by 128 */
01488 #define  RCC_CFGR_HPRE_DIV256                ((u32)0x000000E0)        /* SYSCLK divided by 256 */
01489 #define  RCC_CFGR_HPRE_DIV512                ((u32)0x000000F0)        /* SYSCLK divided by 512 */
01490
01491 #define  RCC_CFGR_PPRE1                      ((u32)0x00000700)        /* PRE1[2:0] bits (APB1 prescaler) */
01492 #define  RCC_CFGR_PPRE1_0                    ((u32)0x00000100)        /* Bit 0 */
01493 #define  RCC_CFGR_PPRE1_1                    ((u32)0x00000200)        /* Bit 1 */
01494 #define  RCC_CFGR_PPRE1_2                    ((u32)0x00000400)        /* Bit 2 */
01495
01496 /* PPRE1 configuration */
01497 #define  RCC_CFGR_PPRE1_DIV1                 ((u32)0x00000000)        /* HCLK not divided */
01498 #define  RCC_CFGR_PPRE1_DIV2                 ((u32)0x00000400)        /* HCLK divided by 2 */
01499 #define  RCC_CFGR_PPRE1_DIV4                 ((u32)0x00000500)        /* HCLK divided by 4 */
01500 #define  RCC_CFGR_PPRE1_DIV8                 ((u32)0x00000600)        /* HCLK divided by 8 */
01501 #define  RCC_CFGR_PPRE1_DIV16                ((u32)0x00000700)        /* HCLK divided by 16 */
01502
01503 #define  RCC_CFGR_PPRE2                      ((u32)0x00003800)        /* PRE2[2:0] bits (APB2 prescaler) */
01504 #define  RCC_CFGR_PPRE2_0                    ((u32)0x00000800)        /* Bit 0 */
01505 #define  RCC_CFGR_PPRE2_1                    ((u32)0x00001000)        /* Bit 1 */
01506 #define  RCC_CFGR_PPRE2_2                    ((u32)0x00002000)        /* Bit 2 */
01507
01508 /* PPRE2 configuration */
01509 #define  RCC_CFGR_PPRE2_DIV1                 ((u32)0x00000000)        /* HCLK not divided */
01510 #define  RCC_CFGR_PPRE2_DIV2                 ((u32)0x00002000)        /* HCLK divided by 2 */
01511 #define  RCC_CFGR_PPRE2_DIV4                 ((u32)0x00002800)        /* HCLK divided by 4 */
01512 #define  RCC_CFGR_PPRE2_DIV8                 ((u32)0x00003000)        /* HCLK divided by 8 */
01513 #define  RCC_CFGR_PPRE2_DIV16                ((u32)0x00003800)        /* HCLK divided by 16 */
01514
01515 #define  RCC_CFGR_ADCPRE                     ((u32)0x0000C000)        /* ADCPRE[1:0] bits (ADC prescaler) */
01516 #define  RCC_CFGR_ADCPRE_0                   ((u32)0x00004000)        /* Bit 0 */
01517 #define  RCC_CFGR_ADCPRE_1                   ((u32)0x00008000)        /* Bit 1 */
01518
01519 /* ADCPPRE configuration */
01520 #define  RCC_CFGR_ADCPRE_DIV2                ((u32)0x00000000)        /* PCLK2 divided by 2 */
01521 #define  RCC_CFGR_ADCPRE_DIV4                ((u32)0x00004000)        /* PCLK2 divided by 4 */
01522 #define  RCC_CFGR_ADCPRE_DIV6                ((u32)0x00008000)        /* PCLK2 divided by 6 */
01523 #define  RCC_CFGR_ADCPRE_DIV8                ((u32)0x0000C000)        /* PCLK2 divided by 8 */
01524
01525 #define  RCC_CFGR_PLLSRC                     ((u32)0x00010000)        /* PLL entry clock source */
01526 #define  RCC_CFGR_PLLXTPRE                   ((u32)0x00020000)        /* HSE divider for PLL entry */
01527
01528 #define  RCC_CFGR_PLLMULL                    ((u32)0x003C0000)        /* PLLMUL[3:0] bits (PLL multiplication factor) */
01529 #define  RCC_CFGR_PLLMULL_0                  ((u32)0x00040000)        /* Bit 0 */
01530 #define  RCC_CFGR_PLLMULL_1                  ((u32)0x00080000)        /* Bit 1 */
01531 #define  RCC_CFGR_PLLMULL_2                  ((u32)0x00100000)        /* Bit 2 */
01532 #define  RCC_CFGR_PLLMULL_3                  ((u32)0x00200000)        /* Bit 3 */
01533
01534 /* PLLMUL configuration */
01535 #define  RCC_CFGR_PLLMULL2                   ((u32)0x00000000)        /* PLL input clock*2 */
01536 #define  RCC_CFGR_PLLMULL3                   ((u32)0x00040000)        /* PLL input clock*3 */
01537 #define  RCC_CFGR_PLLMULL4                   ((u32)0x00080000)        /* PLL input clock*4 */
01538 #define  RCC_CFGR_PLLMULL5                   ((u32)0x000C0000)        /* PLL input clock*5 */
01539 #define  RCC_CFGR_PLLMULL6                   ((u32)0x00100000)        /* PLL input clock*6 */
01540 #define  RCC_CFGR_PLLMULL7                   ((u32)0x00140000)        /* PLL input clock*7 */
01541 #define  RCC_CFGR_PLLMULL8                   ((u32)0x00180000)        /* PLL input clock*8 */
01542 #define  RCC_CFGR_PLLMULL9                   ((u32)0x001C0000)        /* PLL input clock*9 */
01543 #define  RCC_CFGR_PLLMULL10                  ((u32)0x00200000)        /* PLL input clock10 */
01544 #define  RCC_CFGR_PLLMULL11                  ((u32)0x00240000)        /* PLL input clock*11 */
01545 #define  RCC_CFGR_PLLMULL12                  ((u32)0x00280000)        /* PLL input clock*12 */
01546 #define  RCC_CFGR_PLLMULL13                  ((u32)0x002C0000)        /* PLL input clock*13 */
01547 #define  RCC_CFGR_PLLMULL14                  ((u32)0x00300000)        /* PLL input clock*14 */
01548 #define  RCC_CFGR_PLLMULL15                  ((u32)0x00340000)        /* PLL input clock*15 */
01549 #define  RCC_CFGR_PLLMULL16                  ((u32)0x00380000)        /* PLL input clock*16 */
01550
01551 #define  RCC_CFGR_USBPRE                     ((u32)0x00400000)        /* USB prescaler */
01552
01553 #define  RCC_CFGR_MCO                        ((u32)0x07000000)        /* MCO[2:0] bits (Microcontroller Clock Output) */
01554 #define  RCC_CFGR_MCO_0                      ((u32)0x01000000)        /* Bit 0 */
01555 #define  RCC_CFGR_MCO_1                      ((u32)0x02000000)        /* Bit 1 */
01556 #define  RCC_CFGR_MCO_2                      ((u32)0x04000000)        /* Bit 2 */
01557
01558 /* MCO configuration */
01559 #define  RCC_CFGR_MCO_NOCLOCK                ((u32)0x00000000)        /* No clock */
01560 #define  RCC_CFGR_MCO_SYSCLK                 ((u32)0x04000000)        /* System clock selected */
01561 #define  RCC_CFGR_MCO_HSI                    ((u32)0x05000000)        /* Internal 8 MHz RC oscillator clock selected */
01562 #define  RCC_CFGR_MCO_HSE                    ((u32)0x06000000)        /* External 1-25 MHz oscillator clock selected */
01563 #define  RCC_CFGR_MCO_PLL                    ((u32)0x07000000)        /* PLL clock divided by 2 selected*/
01564
01565
01566 /*******************  Bit definition for RCC_CIR register  ********************/
01567 #define  RCC_CIR_LSIRDYF                     ((u32)0x00000001)        /* LSI Ready Interrupt flag */
01568 #define  RCC_CIR_LSERDYF                     ((u32)0x00000002)        /* LSE Ready Interrupt flag */
01569 #define  RCC_CIR_HSIRDYF                     ((u32)0x00000004)        /* HSI Ready Interrupt flag */
01570 #define  RCC_CIR_HSERDYF                     ((u32)0x00000008)        /* HSE Ready Interrupt flag */
01571 #define  RCC_CIR_PLLRDYF                     ((u32)0x00000010)        /* PLL Ready Interrupt flag */
01572 #define  RCC_CIR_CSSF                        ((u32)0x00000080)        /* Clock Security System Interrupt flag */
01573 #define  RCC_CIR_LSIRDYIE                    ((u32)0x00000100)        /* LSI Ready Interrupt Enable */
01574 #define  RCC_CIR_LSERDYIE                    ((u32)0x00000200)        /* LSE Ready Interrupt Enable */
01575 #define  RCC_CIR_HSIRDYIE                    ((u32)0x00000400)        /* HSI Ready Interrupt Enable */
01576 #define  RCC_CIR_HSERDYIE                    ((u32)0x00000800)        /* HSE Ready Interrupt Enable */
01577 #define  RCC_CIR_PLLRDYIE                    ((u32)0x00001000)        /* PLL Ready Interrupt Enable */
01578 #define  RCC_CIR_LSIRDYC                     ((u32)0x00010000)        /* LSI Ready Interrupt Clear */
01579 #define  RCC_CIR_LSERDYC                     ((u32)0x00020000)        /* LSE Ready Interrupt Clear */
01580 #define  RCC_CIR_HSIRDYC                     ((u32)0x00040000)        /* HSI Ready Interrupt Clear */
01581 #define  RCC_CIR_HSERDYC                     ((u32)0x00080000)        /* HSE Ready Interrupt Clear */
01582 #define  RCC_CIR_PLLRDYC                     ((u32)0x00100000)        /* PLL Ready Interrupt Clear */
01583 #define  RCC_CIR_CSSC                        ((u32)0x00800000)        /* Clock Security System Interrupt Clear */
01584
01585
01586 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
01587 #define  RCC_APB2RSTR_AFIORST                ((u16)0x0001)            /* Alternate Function I/O reset */
01588 #define  RCC_APB2RSTR_IOPARST                ((u16)0x0004)            /* I/O port A reset */
01589 #define  RCC_APB2RSTR_IOPBRST                ((u16)0x0008)            /* IO port B reset */
01590 #define  RCC_APB2RSTR_IOPCRST                ((u16)0x0010)            /* IO port C reset */
01591 #define  RCC_APB2RSTR_IOPDRST                ((u16)0x0020)            /* IO port D reset */
01592 #define  RCC_APB2RSTR_IOPERST                ((u16)0x0040)            /* IO port E reset */
01593 #define  RCC_APB2RSTR_IOPFRST                ((u16)0x0080)            /* IO port F reset */
01594 #define  RCC_APB2RSTR_IOPGRST                ((u16)0x0100)            /* IO port G reset */
01595 #define  RCC_APB2RSTR_ADC1RST                ((u16)0x0200)            /* ADC 1 interface reset */
01596 #define  RCC_APB2RSTR_ADC2RST                ((u16)0x0400)            /* ADC 2 interface reset */
01597 #define  RCC_APB2RSTR_TIM1RST                ((u16)0x0800)            /* TIM1 Timer reset */
01598 #define  RCC_APB2RSTR_SPI1RST                ((u16)0x1000)            /* SPI 1 reset */
01599 #define  RCC_APB2RSTR_TIM8RST                ((u16)0x2000)            /* TIM8 Timer reset */
01600 #define  RCC_APB2RSTR_USART1RST              ((u16)0x4000)            /* USART1 reset */
01601 #define  RCC_APB2RSTR_ADC3RST                ((u16)0x8000)            /* ADC3 interface reset */
01602
01603
01604 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
01605 #define  RCC_APB1RSTR_TIM2RST                ((u32)0x00000001)        /* Timer 2 reset */
01606 #define  RCC_APB1RSTR_TIM3RST                ((u32)0x00000002)        /* Timer 3 reset */
01607 #define  RCC_APB1RSTR_TIM4RST                ((u32)0x00000004)        /* Timer 4 reset */
01608 #define  RCC_APB1RSTR_TIM5RST                ((u32)0x00000008)        /* Timer 5 reset */
01609 #define  RCC_APB1RSTR_TIM6RST                ((u32)0x00000010)        /* Timer 6 reset */
01610 #define  RCC_APB1RSTR_TIM7RST                ((u32)0x00000020)        /* Timer 7 reset */
01611 #define  RCC_APB1RSTR_WWDGRST                ((u32)0x00000800)        /* Window Watchdog reset */
01612 #define  RCC_APB1RSTR_SPI2RST                ((u32)0x00004000)        /* SPI 2 reset */
01613 #define  RCC_APB1RSTR_SPI3RST                ((u32)0x00008000)        /* SPI 3 reset */
01614 #define  RCC_APB1RSTR_USART2RST              ((u32)0x00020000)        /* USART 2 reset */
01615 #define  RCC_APB1RSTR_USART3RST              ((u32)0x00040000)        /* RUSART 3 reset */
01616 #define  RCC_APB1RSTR_UART4RST               ((u32)0x00080000)        /* USART 4 reset */
01617 #define  RCC_APB1RSTR_UART5RST               ((u32)0x00100000)        /* USART 5 reset */
01618 #define  RCC_APB1RSTR_I2C1RST                ((u32)0x00200000)        /* I2C 1 reset */
01619 #define  RCC_APB1RSTR_I2C2RST                ((u32)0x00400000)        /* I2C 2 reset */
01620 #define  RCC_APB1RSTR_USBRST                 ((u32)0x00800000)        /* USB reset */
01621 #define  RCC_APB1RSTR_CANRST                 ((u32)0x02000000)        /* CAN reset */
01622 #define  RCC_APB1RSTR_BKPRST                 ((u32)0x08000000)        /* Backup interface reset */
01623 #define  RCC_APB1RSTR_PWRRST                 ((u32)0x10000000)        /* Power interface reset */
01624 #define  RCC_APB1RSTR_DACRST                 ((u32)0x20000000)        /* DAC interface reset */
01625
01626
01627 /******************  Bit definition for RCC_AHBENR register  ******************/
01628 #define  RCC_AHBENR_DMA1EN                   ((u16)0x0001)            /* DMA1 clock enable */
01629 #define  RCC_AHBENR_DMA2EN                   ((u16)0x0002)            /* DMA2 clock enable */
01630 #define  RCC_AHBENR_SRAMEN                   ((u16)0x0004)            /* SRAM interface clock enable */
01631 #define  RCC_AHBENR_FLITFEN                  ((u16)0x0010)            /* FLITF clock enable */
01632 #define  RCC_AHBENR_CRCEN                    ((u16)0x0040)            /* CRC clock enable */
01633 #define  RCC_AHBENR_FSMCEN                   ((u16)0x0100)            /* FSMC clock enable */
01634 #define  RCC_AHBENR_SDIOEN                   ((u16)0x0400)            /* SDIO clock enable */
01635
01636
01637 /******************  Bit definition for RCC_APB2ENR register  *****************/
01638 #define  RCC_APB2ENR_AFIOEN                  ((u16)0x0001)            /* Alternate Function I/O clock enable */
01639 #define  RCC_APB2ENR_IOPAEN                  ((u16)0x0004)            /* I/O port A clock enable */
01640 #define  RCC_APB2ENR_IOPBEN                  ((u16)0x0008)            /* I/O port B clock enable */
01641 #define  RCC_APB2ENR_IOPCEN                  ((u16)0x0010)            /* I/O port C clock enable */
01642 #define  RCC_APB2ENR_IOPDEN                  ((u16)0x0020)            /* I/O port D clock enable */
01643 #define  RCC_APB2ENR_IOPEEN                  ((u16)0x0040)            /* I/O port E clock enable */
01644 #define  RCC_APB2ENR_IOPFEN                  ((u16)0x0080)            /* I/O port F clock enable */
01645 #define  RCC_APB2ENR_IOPGEN                  ((u16)0x0100)            /* I/O port G clock enable */
01646 #define  RCC_APB2ENR_ADC1EN                  ((u16)0x0200)            /* ADC 1 interface clock enable */
01647 #define  RCC_APB2ENR_ADC2EN                  ((u16)0x0400)            /* ADC 2 interface clock enable */
01648 #define  RCC_APB2ENR_TIM1EN                  ((u16)0x0800)            /* TIM1 Timer clock enable */
01649 #define  RCC_APB2ENR_SPI1EN                  ((u16)0x1000)            /* SPI 1 clock enable */
01650 #define  RCC_APB2ENR_TIM8EN                  ((u16)0x2000)            /* TIM8 Timer clock enable */
01651 #define  RCC_APB2ENR_USART1EN                ((u16)0x4000)            /* USART1 clock enable */
01652 #define  RCC_APB2ENR_ADC3EN                  ((u16)0x8000)            /* DMA1 clock enable */
01653
01654
01655 /*****************  Bit definition for RCC_APB1ENR register  ******************/
01656 #define  RCC_APB1ENR_TIM2EN                  ((u32)0x00000001)        /* Timer 2 clock enabled*/
01657 #define  RCC_APB1ENR_TIM3EN                  ((u32)0x00000002)        /* Timer 3 clock enable */
01658 #define  RCC_APB1ENR_TIM4EN                  ((u32)0x00000004)        /* Timer 4 clock enable */
01659 #define  RCC_APB1ENR_TIM5EN                  ((u32)0x00000008)        /* Timer 5 clock enable */
01660 #define  RCC_APB1ENR_TIM6EN                  ((u32)0x00000010)        /* Timer 6 clock enable */
01661 #define  RCC_APB1ENR_TIM7EN                  ((u32)0x00000020)        /* Timer 7 clock enable */
01662 #define  RCC_APB1ENR_WWDGEN                  ((u32)0x00000800)        /* Window Watchdog clock enable */
01663 #define  RCC_APB1ENR_SPI2EN                  ((u32)0x00004000)        /* SPI 2 clock enable */
01664 #define  RCC_APB1ENR_SPI3EN                  ((u32)0x00008000)        /* SPI 3 clock enable */
01665 #define  RCC_APB1ENR_USART2EN                ((u32)0x00020000)        /* USART 2 clock enable */
01666 #define  RCC_APB1ENR_USART3EN                ((u32)0x00040000)        /* USART 3 clock enable */
01667 #define  RCC_APB1ENR_UART4EN                 ((u32)0x00080000)        /* USART 4 clock enable */
01668 #define  RCC_APB1ENR_UART5EN                 ((u32)0x00100000)        /* USART 5 clock enable */
01669 #define  RCC_APB1ENR_I2C1EN                  ((u32)0x00200000)        /* I2C 1 clock enable */
01670 #define  RCC_APB1ENR_I2C2EN                  ((u32)0x00400000)        /* I2C 2 clock enable */
01671 #define  RCC_APB1ENR_USBEN                   ((u32)0x00800000)        /* USB clock enable */
01672 #define  RCC_APB1ENR_CANEN                   ((u32)0x02000000)        /* CAN clock enable */
01673 #define  RCC_APB1ENR_BKPEN                   ((u32)0x08000000)        /* Backup interface clock enable */
01674 #define  RCC_APB1ENR_PWREN                   ((u32)0x10000000)        /* Power interface clock enable */
01675 #define  RCC_APB1ENR_DACEN                   ((u32)0x20000000)        /* DAC interface clock enable */
01676
01677
01678 /*******************  Bit definition for RCC_BDCR register  *******************/
01679 #define  RCC_BDCR_LSEON                      ((u32)0x00000001)        /* External Low Speed oscillator enable */
01680 #define  RCC_BDCR_LSERDY                     ((u32)0x00000002)        /* External Low Speed oscillator Ready */
01681 #define  RCC_BDCR_LSEBYP                     ((u32)0x00000004)        /* External Low Speed oscillator Bypass */
01682
01683 #define  RCC_BDCR_RTCSEL                     ((u32)0x00000300)        /* RTCSEL[1:0] bits (RTC clock source selection) */
01684 #define  RCC_BDCR_RTCSEL_0                   ((u32)0x00000100)        /* Bit 0 */
01685 #define  RCC_BDCR_RTCSEL_1                   ((u32)0x00000200)        /* Bit 1 */
01686 /* RTC congiguration */
01687 #define  RCC_BDCR_RTCSEL_NOCLOCK             ((u32)0x00000000)        /* No clock */
01688 #define  RCC_BDCR_RTCSEL_LSE                 ((u32)0x00000100)        /* LSE oscillator clock used as RTC clock */
01689 #define  RCC_BDCR_RTCSEL_LSI                 ((u32)0x00000200)        /* LSI oscillator clock used as RTC clock */
01690 #define  RCC_BDCR_RTCSEL_HSE                 ((u32)0x00000300)        /* HSE oscillator clock divided by 128 used as RTC clock */
01691
01692 #define  RCC_BDCR_RTCEN                      ((u32)0x00008000)        /* RTC clock enable */
01693 #define  RCC_BDCR_BDRST                      ((u32)0x00010000)        /* Backup domain software reset  */
01694
01695
01696 /*******************  Bit definition for RCC_CSR register  ********************/
01697 #define  RCC_CSR_LSION                       ((u32)0x00000001)        /* Internal Low Speed oscillator enable */
01698 #define  RCC_CSR_LSIRDY                      ((u32)0x00000002)        /* Internal Low Speed oscillator Ready */
01699 #define  RCC_CSR_RMVF                        ((u32)0x01000000)        /* Remove reset flag */
01700 #define  RCC_CSR_PINRSTF                     ((u32)0x04000000)        /* PIN reset flag */
01701 #define  RCC_CSR_PORRSTF                     ((u32)0x08000000)        /* POR/PDR reset flag */
01702 #define  RCC_CSR_SFTRSTF                     ((u32)0x10000000)        /* Software Reset flag */
01703 #define  RCC_CSR_IWDGRSTF                    ((u32)0x20000000)        /* Independent Watchdog reset flag */
01704 #define  RCC_CSR_WWDGRSTF                    ((u32)0x40000000)        /* Window watchdog reset flag */
01705 #define  RCC_CSR_LPWRRSTF                    ((u32)0x80000000)        /* Low-Power reset flag */
01706
01707
01708
01709 /******************************************************************************/
01710 /*                                                                            */
01711 /*                General Purpose and Alternate Function IO                   */
01712 /*                                                                            */
01713 /******************************************************************************/
01714
01715 /*******************  Bit definition for GPIO_CRL register  *******************/
01716 #define  GPIO_CRL_MODE                       ((u32)0x33333333)        /* Port x mode bits */
01717
01718 #define  GPIO_CRL_MODE0                      ((u32)0x00000003)        /* MODE0[1:0] bits (Port x mode bits, pin 0) */
01719 #define  GPIO_CRL_MODE0_0                    ((u32)0x00000001)        /* Bit 0 */
01720 #define  GPIO_CRL_MODE0_1                    ((u32)0x00000002)        /* Bit 1 */
01721
01722 #define  GPIO_CRL_MODE1                      ((u32)0x00000030)        /* MODE1[1:0] bits (Port x mode bits, pin 1) */
01723 #define  GPIO_CRL_MODE1_0                    ((u32)0x00000010)        /* Bit 0 */
01724 #define  GPIO_CRL_MODE1_1                    ((u32)0x00000020)        /* Bit 1 */
01725
01726 #define  GPIO_CRL_MODE2                      ((u32)0x00000300)        /* MODE2[1:0] bits (Port x mode bits, pin 2) */
01727 #define  GPIO_CRL_MODE2_0                    ((u32)0x00000100)        /* Bit 0 */
01728 #define  GPIO_CRL_MODE2_1                    ((u32)0x00000200)        /* Bit 1 */
01729
01730 #define  GPIO_CRL_MODE3                      ((u32)0x00003000)        /* MODE3[1:0] bits (Port x mode bits, pin 3) */
01731 #define  GPIO_CRL_MODE3_0                    ((u32)0x00001000)        /* Bit 0 */
01732 #define  GPIO_CRL_MODE3_1                    ((u32)0x00002000)        /* Bit 1 */
01733
01734 #define  GPIO_CRL_MODE4                      ((u32)0x00030000)        /* MODE4[1:0] bits (Port x mode bits, pin 4) */
01735 #define  GPIO_CRL_MODE4_0                    ((u32)0x00010000)        /* Bit 0 */
01736 #define  GPIO_CRL_MODE4_1                    ((u32)0x00020000)        /* Bit 1 */
01737
01738 #define  GPIO_CRL_MODE5                      ((u32)0x00300000)        /* MODE5[1:0] bits (Port x mode bits, pin 5) */
01739 #define  GPIO_CRL_MODE5_0                    ((u32)0x00100000)        /* Bit 0 */
01740 #define  GPIO_CRL_MODE5_1                    ((u32)0x00200000)        /* Bit 1 */
01741
01742 #define  GPIO_CRL_MODE6                      ((u32)0x03000000)        /* MODE6[1:0] bits (Port x mode bits, pin 6) */
01743 #define  GPIO_CRL_MODE6_0                    ((u32)0x01000000)        /* Bit 0 */
01744 #define  GPIO_CRL_MODE6_1                    ((u32)0x02000000)        /* Bit 1 */
01745
01746 #define  GPIO_CRL_MODE7                      ((u32)0x30000000)        /* MODE7[1:0] bits (Port x mode bits, pin 7) */
01747 #define  GPIO_CRL_MODE7_0                    ((u32)0x10000000)        /* Bit 0 */
01748 #define  GPIO_CRL_MODE7_1                    ((u32)0x20000000)        /* Bit 1 */
01749
01750
01751 #define  GPIO_CRL_CNF                        ((u32)0xCCCCCCCC)        /* Port x configuration bits */
01752
01753 #define  GPIO_CRL_CNF0                       ((u32)0x0000000C)        /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
01754 #define  GPIO_CRL_CNF0_0                     ((u32)0x00000004)        /* Bit 0 */
01755 #define  GPIO_CRL_CNF0_1                     ((u32)0x00000008)        /* Bit 1 */
01756
01757 #define  GPIO_CRL_CNF1                       ((u32)0x000000C0)        /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
01758 #define  GPIO_CRL_CNF1_0                     ((u32)0x00000040)        /* Bit 0 */
01759 #define  GPIO_CRL_CNF1_1                     ((u32)0x00000080)        /* Bit 1 */
01760
01761 #define  GPIO_CRL_CNF2                       ((u32)0x00000C00)        /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
01762 #define  GPIO_CRL_CNF2_0                     ((u32)0x00000400)        /* Bit 0 */
01763 #define  GPIO_CRL_CNF2_1                     ((u32)0x00000800)        /* Bit 1 */
01764
01765 #define  GPIO_CRL_CNF3                       ((u32)0x0000C000)        /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
01766 #define  GPIO_CRL_CNF3_0                     ((u32)0x00004000)        /* Bit 0 */
01767 #define  GPIO_CRL_CNF3_1                     ((u32)0x00008000)        /* Bit 1 */
01768
01769 #define  GPIO_CRL_CNF4                       ((u32)0x000C0000)        /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
01770 #define  GPIO_CRL_CNF4_0                     ((u32)0x00040000)        /* Bit 0 */
01771 #define  GPIO_CRL_CNF4_1                     ((u32)0x00080000)        /* Bit 1 */
01772
01773 #define  GPIO_CRL_CNF5                       ((u32)0x00C00000)        /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
01774 #define  GPIO_CRL_CNF5_0                     ((u32)0x00400000)        /* Bit 0 */
01775 #define  GPIO_CRL_CNF5_1                     ((u32)0x00800000)        /* Bit 1 */
01776
01777 #define  GPIO_CRL_CNF6                       ((u32)0x0C000000)        /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
01778 #define  GPIO_CRL_CNF6_0                     ((u32)0x04000000)        /* Bit 0 */
01779 #define  GPIO_CRL_CNF6_1                     ((u32)0x08000000)        /* Bit 1 */
01780
01781 #define  GPIO_CRL_CNF7                       ((u32)0xC0000000)        /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
01782 #define  GPIO_CRL_CNF7_0                     ((u32)0x40000000)        /* Bit 0 */
01783 #define  GPIO_CRL_CNF7_1                     ((u32)0x80000000)        /* Bit 1 */
01784
01785
01786 /*******************  Bit definition for GPIO_CRH register  *******************/
01787 #define  GPIO_CRH_MODE                       ((u32)0x33333333)        /* Port x mode bits */
01788
01789 #define  GPIO_CRH_MODE8                      ((u32)0x00000003)        /* MODE8[1:0] bits (Port x mode bits, pin 8) */
01790 #define  GPIO_CRH_MODE8_0                    ((u32)0x00000001)        /* Bit 0 */
01791 #define  GPIO_CRH_MODE8_1                    ((u32)0x00000002)        /* Bit 1 */
01792
01793 #define  GPIO_CRH_MODE9                      ((u32)0x00000030)        /* MODE9[1:0] bits (Port x mode bits, pin 9) */
01794 #define  GPIO_CRH_MODE9_0                    ((u32)0x00000010)        /* Bit 0 */
01795 #define  GPIO_CRH_MODE9_1                    ((u32)0x00000020)        /* Bit 1 */
01796
01797 #define  GPIO_CRH_MODE10                     ((u32)0x00000300)        /* MODE10[1:0] bits (Port x mode bits, pin 10) */
01798 #define  GPIO_CRH_MODE10_0                   ((u32)0x00000100)        /* Bit 0 */
01799 #define  GPIO_CRH_MODE10_1                   ((u32)0x00000200)        /* Bit 1 */
01800
01801 #define  GPIO_CRH_MODE11                     ((u32)0x00003000)        /* MODE11[1:0] bits (Port x mode bits, pin 11) */
01802 #define  GPIO_CRH_MODE11_0                   ((u32)0x00001000)        /* Bit 0 */
01803 #define  GPIO_CRH_MODE11_1                   ((u32)0x00002000)        /* Bit 1 */
01804
01805 #define  GPIO_CRH_MODE12                     ((u32)0x00030000)        /* MODE12[1:0] bits (Port x mode bits, pin 12) */
01806 #define  GPIO_CRH_MODE12_0                   ((u32)0x00010000)        /* Bit 0 */
01807 #define  GPIO_CRH_MODE12_1                   ((u32)0x00020000)        /* Bit 1 */
01808
01809 #define  GPIO_CRH_MODE13                     ((u32)0x00300000)        /* MODE13[1:0] bits (Port x mode bits, pin 13) */
01810 #define  GPIO_CRH_MODE13_0                   ((u32)0x00100000)        /* Bit 0 */
01811 #define  GPIO_CRH_MODE13_1                   ((u32)0x00200000)        /* Bit 1 */
01812
01813 #define  GPIO_CRH_MODE14                     ((u32)0x03000000)        /* MODE14[1:0] bits (Port x mode bits, pin 14) */
01814 #define  GPIO_CRH_MODE14_0                   ((u32)0x01000000)        /* Bit 0 */
01815 #define  GPIO_CRH_MODE14_1                   ((u32)0x02000000)        /* Bit 1 */
01816
01817 #define  GPIO_CRH_MODE15                     ((u32)0x30000000)        /* MODE15[1:0] bits (Port x mode bits, pin 15) */
01818 #define  GPIO_CRH_MODE15_0                   ((u32)0x10000000)        /* Bit 0 */
01819 #define  GPIO_CRH_MODE15_1                   ((u32)0x20000000)        /* Bit 1 */
01820
01821
01822 #define  GPIO_CRH_CNF                        ((u32)0xCCCCCCCC)        /* Port x configuration bits */
01823
01824 #define  GPIO_CRH_CNF8                       ((u32)0x0000000C)        /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
01825 #define  GPIO_CRH_CNF8_0                     ((u32)0x00000004)        /* Bit 0 */
01826 #define  GPIO_CRH_CNF8_1                     ((u32)0x00000008)        /* Bit 1 */
01827
01828 #define  GPIO_CRH_CNF9                       ((u32)0x000000C0)        /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
01829 #define  GPIO_CRH_CNF9_0                     ((u32)0x00000040)        /* Bit 0 */
01830 #define  GPIO_CRH_CNF9_1                     ((u32)0x00000080)        /* Bit 1 */
01831
01832 #define  GPIO_CRH_CNF10                      ((u32)0x00000C00)        /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
01833 #define  GPIO_CRH_CNF10_0                    ((u32)0x00000400)        /* Bit 0 */
01834 #define  GPIO_CRH_CNF10_1                    ((u32)0x00000800)        /* Bit 1 */
01835
01836 #define  GPIO_CRH_CNF11                      ((u32)0x0000C000)        /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
01837 #define  GPIO_CRH_CNF11_0                    ((u32)0x00004000)        /* Bit 0 */
01838 #define  GPIO_CRH_CNF11_1                    ((u32)0x00008000)        /* Bit 1 */
01839
01840 #define  GPIO_CRH_CNF12                      ((u32)0x000C0000)        /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
01841 #define  GPIO_CRH_CNF12_0                    ((u32)0x00040000)        /* Bit 0 */
01842 #define  GPIO_CRH_CNF12_1                    ((u32)0x00080000)        /* Bit 1 */
01843
01844 #define  GPIO_CRH_CNF13                      ((u32)0x00C00000)        /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
01845 #define  GPIO_CRH_CNF13_0                    ((u32)0x00400000)        /* Bit 0 */
01846 #define  GPIO_CRH_CNF13_1                    ((u32)0x00800000)        /* Bit 1 */
01847
01848 #define  GPIO_CRH_CNF14                      ((u32)0x0C000000)        /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
01849 #define  GPIO_CRH_CNF14_0                    ((u32)0x04000000)        /* Bit 0 */
01850 #define  GPIO_CRH_CNF14_1                    ((u32)0x08000000)        /* Bit 1 */
01851
01852 #define  GPIO_CRH_CNF15                      ((u32)0xC0000000)        /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
01853 #define  GPIO_CRH_CNF15_0                    ((u32)0x40000000)        /* Bit 0 */
01854 #define  GPIO_CRH_CNF15_1                    ((u32)0x80000000)        /* Bit 1 */
01855
01856
01857 /*******************  Bit definition for GPIO_IDR register  *******************/
01858 #define GPIO_IDR_IDR0                        ((u16)0x0001)            /* Port input data, bit 0 */
01859 #define GPIO_IDR_IDR1                        ((u16)0x0002)            /* Port input data, bit 1 */
01860 #define GPIO_IDR_IDR2                        ((u16)0x0004)            /* Port input data, bit 2 */
01861 #define GPIO_IDR_IDR3                        ((u16)0x0008)            /* Port input data, bit 3 */
01862 #define GPIO_IDR_IDR4                        ((u16)0x0010)            /* Port input data, bit 4 */
01863 #define GPIO_IDR_IDR5                        ((u16)0x0020)            /* Port input data, bit 5 */
01864 #define GPIO_IDR_IDR6                        ((u16)0x0040)            /* Port input data, bit 6 */
01865 #define GPIO_IDR_IDR7                        ((u16)0x0080)            /* Port input data, bit 7 */
01866 #define GPIO_IDR_IDR8                        ((u16)0x0100)            /* Port input data, bit 8 */
01867 #define GPIO_IDR_IDR9                        ((u16)0x0200)            /* Port input data, bit 9 */
01868 #define GPIO_IDR_IDR10                       ((u16)0x0400)            /* Port input data, bit 10 */
01869 #define GPIO_IDR_IDR11                       ((u16)0x0800)            /* Port input data, bit 11 */
01870 #define GPIO_IDR_IDR12                       ((u16)0x1000)            /* Port input data, bit 12 */
01871 #define GPIO_IDR_IDR13                       ((u16)0x2000)            /* Port input data, bit 13 */
01872 #define GPIO_IDR_IDR14                       ((u16)0x4000)            /* Port input data, bit 14 */
01873 #define GPIO_IDR_IDR15                       ((u16)0x8000)            /* Port input data, bit 15 */
01874
01875
01876 /*******************  Bit definition for GPIO_ODR register  *******************/
01877 #define GPIO_ODR_ODR0                        ((u16)0x0001)            /* Port output data, bit 0 */
01878 #define GPIO_ODR_ODR1                        ((u16)0x0002)            /* Port output data, bit 1 */
01879 #define GPIO_ODR_ODR2                        ((u16)0x0004)            /* Port output data, bit 2 */
01880 #define GPIO_ODR_ODR3                        ((u16)0x0008)            /* Port output data, bit 3 */
01881 #define GPIO_ODR_ODR4                        ((u16)0x0010)            /* Port output data, bit 4 */
01882 #define GPIO_ODR_ODR5                        ((u16)0x0020)            /* Port output data, bit 5 */
01883 #define GPIO_ODR_ODR6                        ((u16)0x0040)            /* Port output data, bit 6 */
01884 #define GPIO_ODR_ODR7                        ((u16)0x0080)            /* Port output data, bit 7 */
01885 #define GPIO_ODR_ODR8                        ((u16)0x0100)            /* Port output data, bit 8 */
01886 #define GPIO_ODR_ODR9                        ((u16)0x0200)            /* Port output data, bit 9 */
01887 #define GPIO_ODR_ODR10                       ((u16)0x0400)            /* Port output data, bit 10 */
01888 #define GPIO_ODR_ODR11                       ((u16)0x0800)            /* Port output data, bit 11 */
01889 #define GPIO_ODR_ODR12                       ((u16)0x1000)            /* Port output data, bit 12 */
01890 #define GPIO_ODR_ODR13                       ((u16)0x2000)            /* Port output data, bit 13 */
01891 #define GPIO_ODR_ODR14                       ((u16)0x4000)            /* Port output data, bit 14 */
01892 #define GPIO_ODR_ODR15                       ((u16)0x8000)            /* Port output data, bit 15 */
01893
01894
01895 /******************  Bit definition for GPIO_BSRR register  *******************/
01896 #define GPIO_BSRR_BS0                        ((u32)0x00000001)        /* Port x Set bit 0 */
01897 #define GPIO_BSRR_BS1                        ((u32)0x00000002)        /* Port x Set bit 1 */
01898 #define GPIO_BSRR_BS2                        ((u32)0x00000004)        /* Port x Set bit 2 */
01899 #define GPIO_BSRR_BS3                        ((u32)0x00000008)        /* Port x Set bit 3 */
01900 #define GPIO_BSRR_BS4                        ((u32)0x00000010)        /* Port x Set bit 4 */
01901 #define GPIO_BSRR_BS5                        ((u32)0x00000020)        /* Port x Set bit 5 */
01902 #define GPIO_BSRR_BS6                        ((u32)0x00000040)        /* Port x Set bit 6 */
01903 #define GPIO_BSRR_BS7                        ((u32)0x00000080)        /* Port x Set bit 7 */
01904 #define GPIO_BSRR_BS8                        ((u32)0x00000100)        /* Port x Set bit 8 */
01905 #define GPIO_BSRR_BS9                        ((u32)0x00000200)        /* Port x Set bit 9 */
01906 #define GPIO_BSRR_BS10                       ((u32)0x00000400)        /* Port x Set bit 10 */
01907 #define GPIO_BSRR_BS11                       ((u32)0x00000800)        /* Port x Set bit 11 */
01908 #define GPIO_BSRR_BS12                       ((u32)0x00001000)        /* Port x Set bit 12 */
01909 #define GPIO_BSRR_BS13                       ((u32)0x00002000)        /* Port x Set bit 13 */
01910 #define GPIO_BSRR_BS14                       ((u32)0x00004000)        /* Port x Set bit 14 */
01911 #define GPIO_BSRR_BS15                       ((u32)0x00008000)        /* Port x Set bit 15 */
01912
01913 #define GPIO_BSRR_BR0                        ((u32)0x00010000)        /* Port x Reset bit 0 */
01914 #define GPIO_BSRR_BR1                        ((u32)0x00020000)        /* Port x Reset bit 1 */
01915 #define GPIO_BSRR_BR2                        ((u32)0x00040000)        /* Port x Reset bit 2 */
01916 #define GPIO_BSRR_BR3                        ((u32)0x00080000)        /* Port x Reset bit 3 */
01917 #define GPIO_BSRR_BR4                        ((u32)0x00100000)        /* Port x Reset bit 4 */
01918 #define GPIO_BSRR_BR5                        ((u32)0x00200000)        /* Port x Reset bit 5 */
01919 #define GPIO_BSRR_BR6                        ((u32)0x00400000)        /* Port x Reset bit 6 */
01920 #define GPIO_BSRR_BR7                        ((u32)0x00800000)        /* Port x Reset bit 7 */
01921 #define GPIO_BSRR_BR8                        ((u32)0x01000000)        /* Port x Reset bit 8 */
01922 #define GPIO_BSRR_BR9                        ((u32)0x02000000)        /* Port x Reset bit 9 */
01923 #define GPIO_BSRR_BR10                       ((u32)0x04000000)        /* Port x Reset bit 10 */
01924 #define GPIO_BSRR_BR11                       ((u32)0x08000000)        /* Port x Reset bit 11 */
01925 #define GPIO_BSRR_BR12                       ((u32)0x10000000)        /* Port x Reset bit 12 */
01926 #define GPIO_BSRR_BR13                       ((u32)0x20000000)        /* Port x Reset bit 13 */
01927 #define GPIO_BSRR_BR14                       ((u32)0x40000000)        /* Port x Reset bit 14 */
01928 #define GPIO_BSRR_BR15                       ((u32)0x80000000)        /* Port x Reset bit 15 */
01929
01930
01931 /*******************  Bit definition for GPIO_BRR register  *******************/
01932 #define GPIO_BRR_BR0                         ((u16)0x0001)            /* Port x Reset bit 0 */
01933 #define GPIO_BRR_BR1                         ((u16)0x0002)            /* Port x Reset bit 1 */
01934 #define GPIO_BRR_BR2                         ((u16)0x0004)            /* Port x Reset bit 2 */
01935 #define GPIO_BRR_BR3                         ((u16)0x0008)            /* Port x Reset bit 3 */
01936 #define GPIO_BRR_BR4                         ((u16)0x0010)            /* Port x Reset bit 4 */
01937 #define GPIO_BRR_BR5                         ((u16)0x0020)            /* Port x Reset bit 5 */
01938 #define GPIO_BRR_BR6                         ((u16)0x0040)            /* Port x Reset bit 6 */
01939 #define GPIO_BRR_BR7                         ((u16)0x0080)            /* Port x Reset bit 7 */
01940 #define GPIO_BRR_BR8                         ((u16)0x0100)            /* Port x Reset bit 8 */
01941 #define GPIO_BRR_BR9                         ((u16)0x0200)            /* Port x Reset bit 9 */
01942 #define GPIO_BRR_BR10                        ((u16)0x0400)            /* Port x Reset bit 10 */
01943 #define GPIO_BRR_BR11                        ((u16)0x0800)            /* Port x Reset bit 11 */
01944 #define GPIO_BRR_BR12                        ((u16)0x1000)            /* Port x Reset bit 12 */
01945 #define GPIO_BRR_BR13                        ((u16)0x2000)            /* Port x Reset bit 13 */
01946 #define GPIO_BRR_BR14                        ((u16)0x4000)            /* Port x Reset bit 14 */
01947 #define GPIO_BRR_BR15                        ((u16)0x8000)            /* Port x Reset bit 15 */
01948
01949
01950 /******************  Bit definition for GPIO_LCKR register  *******************/
01951 #define GPIO_LCKR_LCK0                       ((u32)0x00000001)        /* Port x Lock bit 0 */
01952 #define GPIO_LCKR_LCK1                       ((u32)0x00000002)        /* Port x Lock bit 1 */
01953 #define GPIO_LCKR_LCK2                       ((u32)0x00000004)        /* Port x Lock bit 2 */
01954 #define GPIO_LCKR_LCK3                       ((u32)0x00000008)        /* Port x Lock bit 3 */
01955 #define GPIO_LCKR_LCK4                       ((u32)0x00000010)        /* Port x Lock bit 4 */
01956 #define GPIO_LCKR_LCK5                       ((u32)0x00000020)        /* Port x Lock bit 5 */
01957 #define GPIO_LCKR_LCK6                       ((u32)0x00000040)        /* Port x Lock bit 6 */
01958 #define GPIO_LCKR_LCK7                       ((u32)0x00000080)        /* Port x Lock bit 7 */
01959 #define GPIO_LCKR_LCK8                       ((u32)0x00000100)        /* Port x Lock bit 8 */
01960 #define GPIO_LCKR_LCK9                       ((u32)0x00000200)        /* Port x Lock bit 9 */
01961 #define GPIO_LCKR_LCK10                      ((u32)0x00000400)        /* Port x Lock bit 10 */
01962 #define GPIO_LCKR_LCK11                      ((u32)0x00000800)        /* Port x Lock bit 11 */
01963 #define GPIO_LCKR_LCK12                      ((u32)0x00001000)        /* Port x Lock bit 12 */
01964 #define GPIO_LCKR_LCK13                      ((u32)0x00002000)        /* Port x Lock bit 13 */
01965 #define GPIO_LCKR_LCK14                      ((u32)0x00004000)        /* Port x Lock bit 14 */
01966 #define GPIO_LCKR_LCK15                      ((u32)0x00008000)        /* Port x Lock bit 15 */
01967 #define GPIO_LCKR_LCKK                       ((u32)0x00010000)        /* Lock key */
01968
01969
01970 /*----------------------------------------------------------------------------*/
01971
01972
01973 /******************  Bit definition for AFIO_EVCR register  *******************/
01974 #define AFIO_EVCR_PIN                        ((u8)0x0F)               /* PIN[3:0] bits (Pin selection) */
01975 #define AFIO_EVCR_PIN_0                      ((u8)0x01)               /* Bit 0 */
01976 #define AFIO_EVCR_PIN_1                      ((u8)0x02)               /* Bit 1 */
01977 #define AFIO_EVCR_PIN_2                      ((u8)0x04)               /* Bit 2 */
01978 #define AFIO_EVCR_PIN_3                      ((u8)0x08)               /* Bit 3 */
01979
01980 /* PIN configuration */
01981 #define AFIO_EVCR_PIN_PX0                    ((u8)0x00)               /* Pin 0 selected */
01982 #define AFIO_EVCR_PIN_PX1                    ((u8)0x01)               /* Pin 1 selected */
01983 #define AFIO_EVCR_PIN_PX2                    ((u8)0x02)               /* Pin 2 selected */
01984 #define AFIO_EVCR_PIN_PX3                    ((u8)0x03)               /* Pin 3 selected */
01985 #define AFIO_EVCR_PIN_PX4                    ((u8)0x04)               /* Pin 4 selected */
01986 #define AFIO_EVCR_PIN_PX5                    ((u8)0x05)               /* Pin 5 selected */
01987 #define AFIO_EVCR_PIN_PX6                    ((u8)0x06)               /* Pin 6 selected */
01988 #define AFIO_EVCR_PIN_PX7                    ((u8)0x07)               /* Pin 7 selected */
01989 #define AFIO_EVCR_PIN_PX8                    ((u8)0x08)               /* Pin 8 selected */
01990 #define AFIO_EVCR_PIN_PX9                    ((u8)0x09)               /* Pin 9 selected */
01991 #define AFIO_EVCR_PIN_PX10                   ((u8)0x0A)               /* Pin 10 selected */
01992 #define AFIO_EVCR_PIN_PX11                   ((u8)0x0B)               /* Pin 11 selected */
01993 #define AFIO_EVCR_PIN_PX12                   ((u8)0x0C)               /* Pin 12 selected */
01994 #define AFIO_EVCR_PIN_PX13                   ((u8)0x0D)               /* Pin 13 selected */
01995 #define AFIO_EVCR_PIN_PX14                   ((u8)0x0E)               /* Pin 14 selected */
01996 #define AFIO_EVCR_PIN_PX15                   ((u8)0x0F)               /* Pin 15 selected */
01997
01998 #define AFIO_EVCR_PORT                       ((u8)0x70)               /* PORT[2:0] bits (Port selection) */
01999 #define AFIO_EVCR_PORT_0                     ((u8)0x10)               /* Bit 0 */
02000 #define AFIO_EVCR_PORT_1                     ((u8)0x20)               /* Bit 1 */
02001 #define AFIO_EVCR_PORT_2                     ((u8)0x40)               /* Bit 2 */
02002
02003 /* PORT configuration */
02004 #define AFIO_EVCR_PORT_PA                    ((u8)0x00)               /* Port A selected */
02005 #define AFIO_EVCR_PORT_PB                    ((u8)0x10)               /* Port B selected */
02006 #define AFIO_EVCR_PORT_PC                    ((u8)0x20)               /* Port C selected */
02007 #define AFIO_EVCR_PORT_PD                    ((u8)0x30)               /* Port D selected */
02008 #define AFIO_EVCR_PORT_PE                    ((u8)0x40)               /* Port E selected */
02009
02010 #define AFIO_EVCR_EVOE                       ((u8)0x80)               /* Event Output Enable */
02011
02012
02013 /******************  Bit definition for AFIO_MAPR register  *******************/
02014 #define AFIO_MAPR_SPI1 _REMAP                ((u32)0x00000001)        /* SPI1 remapping */
02015 #define AFIO_MAPR_I2C1_REMAP                 ((u32)0x00000002)        /* I2C1 remapping */
02016 #define AFIO_MAPR_USART1_REMAP               ((u32)0x00000004)        /* USART1 remapping */
02017 #define AFIO_MAPR_USART2_REMAP               ((u32)0x00000008)        /* USART2 remapping */
02018
02019 #define AFIO_MAPR_USART3_REMAP               ((u32)0x00000030)        /* USART3_REMAP[1:0] bits (USART3 remapping) */
02020 #define AFIO_MAPR_USART3_REMAP_0             ((u32)0x00000010)        /* Bit 0 */
02021 #define AFIO_MAPR_USART3_REMAP_1             ((u32)0x00000020)        /* Bit 1 */
02022
02023 /* USART3_REMAP configuration */
02024 #define AFIO_MAPR_USART3_REMAP_NOREMAP       ((u32)0x00000000)        /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
02025 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((u32)0x00000010)        /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
02026 #define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((u32)0x00000030)        /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
02027
02028 #define AFIO_MAPR_TIM1_REMAP                 ((u32)0x000000C0)        /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
02029 #define AFIO_MAPR_TIM1_REMAP_0               ((u32)0x00000040)        /* Bit 0 */
02030 #define AFIO_MAPR_TIM1_REMAP_1               ((u32)0x00000080)        /* Bit 1 */
02031
02032 /* TIM1_REMAP configuration */
02033 #define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((u32)0x00000000)        /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
02034 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((u32)0x00000040)        /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
02035 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((u32)0x000000C0)        /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
02036
02037 #define AFIO_MAPR_TIM2_REMAP                 ((u32)0x00000300)        /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
02038 #define AFIO_MAPR_TIM2_REMAP_0               ((u32)0x00000100)        /* Bit 0 */
02039 #define AFIO_MAPR_TIM2_REMAP_1               ((u32)0x00000200)        /* Bit 1 */
02040
02041 /* TIM2_REMAP configuration */
02042 #define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((u32)0x00000000)        /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
02043 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((u32)0x00000100)        /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
02044 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((u32)0x00000200)        /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
02045 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((u32)0x00000300)        /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
02046
02047 #define AFIO_MAPR_TIM3_REMAP                 ((u32)0x00000C00)        /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
02048 #define AFIO_MAPR_TIM3_REMAP_0               ((u32)0x00000400)        /* Bit 0 */
02049 #define AFIO_MAPR_TIM3_REMAP_1               ((u32)0x00000800)        /* Bit 1 */
02050
02051 /* TIM3_REMAP configuration */
02052 #define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((u32)0x00000000)        /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
02053 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((u32)0x00000800)        /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
02054 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((u32)0x00000C00)        /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
02055
02056 #define AFIO_MAPR_TIM4_REMAP                 ((u32)0x00001000)        /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
02057
02058 #define AFIO_MAPR_CAN_REMAP                  ((u32)0x00006000)        /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
02059 #define AFIO_MAPR_CAN_REMAP_0                ((u32)0x00002000)        /* Bit 0 */
02060 #define AFIO_MAPR_CAN_REMAP_1                ((u32)0x00004000)        /* Bit 1 */
02061
02062 /* CAN_REMAP configuration */
02063 #define AFIO_MAPR_CAN_REMAP_REMAP1           ((u32)0x00000000)        /* CANRX mapped to PA11, CANTX mapped to PA12 */
02064 #define AFIO_MAPR_CAN_REMAP_REMAP2           ((u32)0x00004000)        /* CANRX mapped to PB8, CANTX mapped to PB9 */
02065 #define AFIO_MAPR_CAN_REMAP_REMAP3           ((u32)0x00006000)        /* CANRX mapped to PD0, CANTX mapped to PD1 */
02066
02067 #define AFIO_MAPR_PD01_REMAP                 ((u32)0x00008000)        /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
02068 #define AFIO_MAPR_TIM5CH4_IREMAP             ((u32)0x00010000)        /* TIM5 Channel4 Internal Remap */
02069 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((u32)0x00020000)        /* ADC 1 External Trigger Injected Conversion remapping */
02070 #define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((u32)0x00040000)        /* ADC 1 External Trigger Regular Conversion remapping */
02071 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((u32)0x00080000)        /* ADC 2 External Trigger Injected Conversion remapping */
02072 #define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((u32)0x00100000)        /* ADC 2 External Trigger Regular Conversion remapping */
02073
02074 #define AFIO_MAPR_SWJ_CFG                    ((u32)0x07000000)        /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
02075 #define AFIO_MAPR_SWJ_CFG_0                  ((u32)0x01000000)        /* Bit 0 */
02076 #define AFIO_MAPR_SWJ_CFG_1                  ((u32)0x02000000)        /* Bit 1 */
02077 #define AFIO_MAPR_SWJ_CFG_2                  ((u32)0x04000000)        /* Bit 2 */
02078
02079 /* SWJ_CFG configuration */
02080 #define AFIO_MAPR_SWJ_CFG_RESET              ((u32)0x00000000)        /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
02081 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((u32)0x01000000)        /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
02082 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((u32)0x02000000)        /* JTAG-DP Disabled and SW-DP Enabled */
02083 #define AFIO_MAPR_SWJ_CFG_DISABLE            ((u32)0x04000000)        /* JTAG-DP Disabled and SW-DP Disabled */
02084
02085
02086 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
02087 #define AFIO_EXTICR1_EXTI0                   ((u16)0x000F)            /* EXTI 0 configuration */
02088 #define AFIO_EXTICR1_EXTI1                   ((u16)0x00F0)            /* EXTI 1 configuration */
02089 #define AFIO_EXTICR1_EXTI2                   ((u16)0x0F00)            /* EXTI 2 configuration */
02090 #define AFIO_EXTICR1_EXTI3                   ((u16)0xF000)            /* EXTI 3 configuration */
02091
02092 /* EXTI0 configuration */
02093 #define AFIO_EXTICR1_EXTI0_PA                ((u16)0x0000)            /* PA[0] pin */
02094 #define AFIO_EXTICR1_EXTI0_PB                ((u16)0x0001)            /* PB[0] pin */
02095 #define AFIO_EXTICR1_EXTI0_PC                ((u16)0x0002)            /* PC[0] pin */
02096 #define AFIO_EXTICR1_EXTI0_PD                ((u16)0x0003)            /* PD[0] pin */
02097 #define AFIO_EXTICR1_EXTI0_PE                ((u16)0x0004)            /* PE[0] pin */
02098 #define AFIO_EXTICR1_EXTI0_PF                ((u16)0x0005)            /* PF[0] pin */
02099 #define AFIO_EXTICR1_EXTI0_PG                ((u16)0x0006)            /* PG[0] pin */
02100
02101 /* EXTI1 configuration */
02102 #define AFIO_EXTICR1_EXTI1_PA                ((u16)0x0000)            /* PA[1] pin */
02103 #define AFIO_EXTICR1_EXTI1_PB                ((u16)0x0010)            /* PB[1] pin */
02104 #define AFIO_EXTICR1_EXTI1_PC                ((u16)0x0020)            /* PC[1] pin */
02105 #define AFIO_EXTICR1_EXTI1_PD                ((u16)0x0030)            /* PD[1] pin */
02106 #define AFIO_EXTICR1_EXTI1_PE                ((u16)0x0040)            /* PE[1] pin */
02107 #define AFIO_EXTICR1_EXTI1_PF                ((u16)0x0050)            /* PF[1] pin */
02108 #define AFIO_EXTICR1_EXTI1_PG                ((u16)0x0060)            /* PG[1] pin */
02109
02110 /* EXTI2 configuration */
02111 #define AFIO_EXTICR1_EXTI2_PA                ((u16)0x0000)            /* PA[2] pin */
02112 #define AFIO_EXTICR1_EXTI2_PB                ((u16)0x0100)            /* PB[2] pin */
02113 #define AFIO_EXTICR1_EXTI2_PC                ((u16)0x0200)            /* PC[2] pin */
02114 #define AFIO_EXTICR1_EXTI2_PD                ((u16)0x0300)            /* PD[2] pin */
02115 #define AFIO_EXTICR1_EXTI2_PE                ((u16)0x0400)            /* PE[2] pin */
02116 #define AFIO_EXTICR1_EXTI2_PF                ((u16)0x0500)            /* PF[2] pin */
02117 #define AFIO_EXTICR1_EXTI2_PG                ((u16)0x0600)            /* PG[2] pin */
02118
02119 /* EXTI3 configuration */
02120 #define AFIO_EXTICR1_EXTI3_PA                ((u16)0x0000)            /* PA[3] pin */
02121 #define AFIO_EXTICR1_EXTI3_PB                ((u16)0x1000)            /* PB[3] pin */
02122 #define AFIO_EXTICR1_EXTI3_PC                ((u16)0x2000)            /* PC[3] pin */
02123 #define AFIO_EXTICR1_EXTI3_PD                ((u16)0x3000)            /* PD[3] pin */
02124 #define AFIO_EXTICR1_EXTI3_PE                ((u16)0x4000)            /* PE[3] pin */
02125 #define AFIO_EXTICR1_EXTI3_PF                ((u16)0x5000)            /* PF[3] pin */
02126 #define AFIO_EXTICR1_EXTI3_PG                ((u16)0x6000)            /* PG[3] pin */
02127
02128
02129 /*****************  Bit definition for AFIO_EXTICR2 register  *****************/
02130 #define AFIO_EXTICR2_EXTI4                   ((u16)0x000F)            /* EXTI 4 configuration */
02131 #define AFIO_EXTICR2_EXTI5                   ((u16)0x00F0)            /* EXTI 5 configuration */
02132 #define AFIO_EXTICR2_EXTI6                   ((u16)0x0F00)            /* EXTI 6 configuration */
02133 #define AFIO_EXTICR2_EXTI7                   ((u16)0xF000)            /* EXTI 7 configuration */
02134
02135 /* EXTI4 configuration */
02136 #define AFIO_EXTICR2_EXTI4_PA                ((u16)0x0000)            /* PA[4] pin */
02137 #define AFIO_EXTICR2_EXTI4_PB                ((u16)0x0001)            /* PB[4] pin */
02138 #define AFIO_EXTICR2_EXTI4_PC                ((u16)0x0002)            /* PC[4] pin */
02139 #define AFIO_EXTICR2_EXTI4_PD                ((u16)0x0003)            /* PD[4] pin */
02140 #define AFIO_EXTICR2_EXTI4_PE                ((u16)0x0004)            /* PE[4] pin */
02141 #define AFIO_EXTICR2_EXTI4_PF                ((u16)0x0005)            /* PF[4] pin */
02142 #define AFIO_EXTICR2_EXTI4_PG                ((u16)0x0006)            /* PG[4] pin */
02143
02144 /* EXTI5 configuration */
02145 #define AFIO_EXTICR2_EXTI5_PA                ((u16)0x0000)            /* PA[5] pin */
02146 #define AFIO_EXTICR2_EXTI5_PB                ((u16)0x0010)            /* PB[5] pin */
02147 #define AFIO_EXTICR2_EXTI5_PC                ((u16)0x0020)            /* PC[5] pin */
02148 #define AFIO_EXTICR2_EXTI5_PD                ((u16)0x0030)            /* PD[5] pin */
02149 #define AFIO_EXTICR2_EXTI5_PE                ((u16)0x0040)            /* PE[5] pin */
02150 #define AFIO_EXTICR2_EXTI5_PF                ((u16)0x0050)            /* PF[5] pin */
02151 #define AFIO_EXTICR2_EXTI5_PG                ((u16)0x0060)            /* PG[5] pin */
02152
02153 /* EXTI6 configuration */
02154 #define AFIO_EXTICR2_EXTI6_PA                ((u16)0x0000)            /* PA[6] pin */
02155 #define AFIO_EXTICR2_EXTI6_PB                ((u16)0x0100)            /* PB[6] pin */
02156 #define AFIO_EXTICR2_EXTI6_PC                ((u16)0x0200)            /* PC[6] pin */
02157 #define AFIO_EXTICR2_EXTI6_PD                ((u16)0x0300)            /* PD[6] pin */
02158 #define AFIO_EXTICR2_EXTI6_PE                ((u16)0x0400)            /* PE[6] pin */
02159 #define AFIO_EXTICR2_EXTI6_PF                ((u16)0x0500)            /* PF[6] pin */
02160 #define AFIO_EXTICR2_EXTI6_PG                ((u16)0x0600)            /* PG[6] pin */
02161
02162 /* EXTI7 configuration */
02163 #define AFIO_EXTICR2_EXTI7_PA                ((u16)0x0000)            /* PA[7] pin */
02164 #define AFIO_EXTICR2_EXTI7_PB                ((u16)0x1000)            /* PB[7] pin */
02165 #define AFIO_EXTICR2_EXTI7_PC                ((u16)0x2000)            /* PC[7] pin */
02166 #define AFIO_EXTICR2_EXTI7_PD                ((u16)0x3000)            /* PD[7] pin */
02167 #define AFIO_EXTICR2_EXTI7_PE                ((u16)0x4000)            /* PE[7] pin */
02168 #define AFIO_EXTICR2_EXTI7_PF                ((u16)0x5000)            /* PF[7] pin */
02169 #define AFIO_EXTICR2_EXTI7_PG                ((u16)0x6000)            /* PG[7] pin */
02170
02171
02172 /*****************  Bit definition for AFIO_EXTICR3 register  *****************/
02173 #define AFIO_EXTICR3_EXTI8                   ((u16)0x000F)            /* EXTI 8 configuration */
02174 #define AFIO_EXTICR3_EXTI9                   ((u16)0x00F0)            /* EXTI 9 configuration */
02175 #define AFIO_EXTICR3_EXTI10                  ((u16)0x0F00)            /* EXTI 10 configuration */
02176 #define AFIO_EXTICR3_EXTI11                  ((u16)0xF000)            /* EXTI 11 configuration */
02177
02178 /* EXTI8 configuration */
02179 #define AFIO_EXTICR3_EXTI8_PA                ((u16)0x0000)            /* PA[8] pin */
02180 #define AFIO_EXTICR3_EXTI8_PB                ((u16)0x0001)            /* PB[8] pin */
02181 #define AFIO_EXTICR3_EXTI8_PC                ((u16)0x0002)            /* PC[8] pin */
02182 #define AFIO_EXTICR3_EXTI8_PD                ((u16)0x0003)            /* PD[8] pin */
02183 #define AFIO_EXTICR3_EXTI8_PE                ((u16)0x0004)            /* PE[8] pin */
02184 #define AFIO_EXTICR3_EXTI8_PF                ((u16)0x0005)            /* PF[8] pin */
02185 #define AFIO_EXTICR3_EXTI8_PG                ((u16)0x0006)            /* PG[8] pin */
02186
02187 /* EXTI9 configuration */
02188 #define AFIO_EXTICR3_EXTI9_PA                ((u16)0x0000)            /* PA[9] pin */
02189 #define AFIO_EXTICR3_EXTI9_PB                ((u16)0x0010)            /* PB[9] pin */
02190 #define AFIO_EXTICR3_EXTI9_PC                ((u16)0x0020)            /* PC[9] pin */
02191 #define AFIO_EXTICR3_EXTI9_PD                ((u16)0x0030)            /* PD[9] pin */
02192 #define AFIO_EXTICR3_EXTI9_PE                ((u16)0x0040)            /* PE[9] pin */
02193 #define AFIO_EXTICR3_EXTI9_PF                ((u16)0x0050)            /* PF[9] pin */
02194 #define AFIO_EXTICR3_EXTI9_PG                ((u16)0x0060)            /* PG[9] pin */
02195
02196 /* EXTI10 configuration */
02197 #define AFIO_EXTICR3_EXTI10_PA               ((u16)0x0000)            /* PA[10] pin */
02198 #define AFIO_EXTICR3_EXTI10_PB               ((u16)0x0100)            /* PB[10] pin */
02199 #define AFIO_EXTICR3_EXTI10_PC               ((u16)0x0200)            /* PC[10] pin */
02200 #define AFIO_EXTICR3_EXTI10_PD               ((u16)0x0300)            /* PD[10] pin */
02201 #define AFIO_EXTICR3_EXTI10_PE               ((u16)0x0400)            /* PE[10] pin */
02202 #define AFIO_EXTICR3_EXTI10_PF               ((u16)0x0500)            /* PF[10] pin */
02203 #define AFIO_EXTICR3_EXTI10_PG               ((u16)0x0600)            /* PG[10] pin */
02204
02205 /* EXTI11 configuration */
02206 #define AFIO_EXTICR3_EXTI11_PA               ((u16)0x0000)            /* PA[11] pin */
02207 #define AFIO_EXTICR3_EXTI11_PB               ((u16)0x1000)            /* PB[11] pin */
02208 #define AFIO_EXTICR3_EXTI11_PC               ((u16)0x2000)            /* PC[11] pin */
02209 #define AFIO_EXTICR3_EXTI11_PD               ((u16)0x3000)            /* PD[11] pin */
02210 #define AFIO_EXTICR3_EXTI11_PE               ((u16)0x4000)            /* PE[11] pin */
02211 #define AFIO_EXTICR3_EXTI11_PF               ((u16)0x5000)            /* PF[11] pin */
02212 #define AFIO_EXTICR3_EXTI11_PG               ((u16)0x6000)            /* PG[11] pin */
02213
02214
02215 /*****************  Bit definition for AFIO_EXTICR4 register  *****************/
02216 #define AFIO_EXTICR4_EXTI12                  ((u16)0x000F)            /* EXTI 12 configuration */
02217 #define AFIO_EXTICR4_EXTI13                  ((u16)0x00F0)            /* EXTI 13 configuration */
02218 #define AFIO_EXTICR4_EXTI14                  ((u16)0x0F00)            /* EXTI 14 configuration */
02219 #define AFIO_EXTICR4_EXTI15                  ((u16)0xF000)            /* EXTI 15 configuration */
02220
02221 /* EXTI12 configuration */
02222 #define AFIO_EXTICR4_EXTI12_PA               ((u16)0x0000)            /* PA[12] pin */
02223 #define AFIO_EXTICR4_EXTI12_PB               ((u16)0x0001)            /* PB[12] pin */
02224 #define AFIO_EXTICR4_EXTI12_PC               ((u16)0x0002)            /* PC[12] pin */
02225 #define AFIO_EXTICR4_EXTI12_PD               ((u16)0x0003)            /* PD[12] pin */
02226 #define AFIO_EXTICR4_EXTI12_PE               ((u16)0x0004)            /* PE[12] pin */
02227 #define AFIO_EXTICR4_EXTI12_PF               ((u16)0x0005)            /* PF[12] pin */
02228 #define AFIO_EXTICR4_EXTI12_PG               ((u16)0x0006)            /* PG[12] pin */
02229
02230 /* EXTI13 configuration */
02231 #define AFIO_EXTICR4_EXTI13_PA               ((u16)0x0000)            /* PA[13] pin */
02232 #define AFIO_EXTICR4_EXTI13_PB               ((u16)0x0010)            /* PB[13] pin */
02233 #define AFIO_EXTICR4_EXTI13_PC               ((u16)0x0020)            /* PC[13] pin */
02234 #define AFIO_EXTICR4_EXTI13_PD               ((u16)0x0030)            /* PD[13] pin */
02235 #define AFIO_EXTICR4_EXTI13_PE               ((u16)0x0040)            /* PE[13] pin */
02236 #define AFIO_EXTICR4_EXTI13_PF               ((u16)0x0050)            /* PF[13] pin */
02237 #define AFIO_EXTICR4_EXTI13_PG               ((u16)0x0060)            /* PG[13] pin */
02238
02239 /* EXTI14 configuration */
02240 #define AFIO_EXTICR4_EXTI14_PA               ((u16)0x0000)            /* PA[14] pin */
02241 #define AFIO_EXTICR4_EXTI14_PB               ((u16)0x0100)            /* PB[14] pin */
02242 #define AFIO_EXTICR4_EXTI14_PC               ((u16)0x0200)            /* PC[14] pin */
02243 #define AFIO_EXTICR4_EXTI14_PD               ((u16)0x0300)            /* PD[14] pin */
02244 #define AFIO_EXTICR4_EXTI14_PE               ((u16)0x0400)            /* PE[14] pin */
02245 #define AFIO_EXTICR4_EXTI14_PF               ((u16)0x0500)            /* PF[14] pin */
02246 #define AFIO_EXTICR4_EXTI14_PG               ((u16)0x0600)            /* PG[14] pin */
02247
02248 /* EXTI15 configuration */
02249 #define AFIO_EXTICR4_EXTI15_PA               ((u16)0x0000)            /* PA[15] pin */
02250 #define AFIO_EXTICR4_EXTI15_PB               ((u16)0x1000)            /* PB[15] pin */
02251 #define AFIO_EXTICR4_EXTI15_PC               ((u16)0x2000)            /* PC[15] pin */
02252 #define AFIO_EXTICR4_EXTI15_PD               ((u16)0x3000)            /* PD[15] pin */
02253 #define AFIO_EXTICR4_EXTI15_PE               ((u16)0x4000)            /* PE[15] pin */
02254 #define AFIO_EXTICR4_EXTI15_PF               ((u16)0x5000)            /* PF[15] pin */
02255 #define AFIO_EXTICR4_EXTI15_PG               ((u16)0x6000)            /* PG[15] pin */
02256
02257
02258
02259 /******************************************************************************/
02260 /*                                                                            */
02261 /*                               SystemTick                                   */
02262 /*                                                                            */
02263 /******************************************************************************/
02264
02265 /*****************  Bit definition for SysTick_CTRL register  *****************/
02266 #define  SysTick_CTRL_ENABLE                 ((u32)0x00000001)        /* Counter enable */
02267 #define  SysTick_CTRL_TICKINT                ((u32)0x00000002)        /* Counting down to 0 pends the SysTick handler */
02268 #define  SysTick_CTRL_CLKSOURCE              ((u32)0x00000004)        /* Clock source */
02269 #define  SysTick_CTRL_COUNTFLAG              ((u32)0x00010000)        /* Count Flag */
02270
02271
02272 /*****************  Bit definition for SysTick_LOAD register  *****************/
02273 #define  SysTick_LOAD_RELOAD                 ((u32)0x00FFFFFF)        /* Value to load into the SysTick Current Value Register when the counter reaches 0 */
02274
02275
02276 /*****************  Bit definition for SysTick_VAL register  ******************/
02277 #define  SysTick_VAL_CURRENT                 ((u32)0x00FFFFFF)        /* Current value at the time the register is accessed */
02278
02279
02280 /*****************  Bit definition for SysTick_CALIB register  ****************/
02281 #define  SysTick_CALIB_TENMS                 ((u32)0x00FFFFFF)        /* Reload value to use for 10ms timing */
02282 #define  SysTick_CALIB_SKEW                  ((u32)0x40000000)        /* Calibration value is not exactly 10 ms */
02283 #define  SysTick_CALIB_NOREF                 ((u32)0x80000000)        /* The reference clock is not provided */
02284
02285
02286
02287 /******************************************************************************/
02288 /*                                                                            */
02289 /*                  Nested Vectored Interrupt Controller                      */
02290 /*                                                                            */
02291 /******************************************************************************/
02292
02293 /******************  Bit definition for NVIC_ISER register  *******************/
02294 #define  NVIC_ISER_SETENA                    ((u32)0xFFFFFFFF)        /* Interrupt set enable bits */
02295 #define  NVIC_ISER_SETENA_0                  ((u32)0x00000001)        /* bit 0 */
02296 #define  NVIC_ISER_SETENA_1                  ((u32)0x00000002)        /* bit 1 */
02297 #define  NVIC_ISER_SETENA_2                  ((u32)0x00000004)        /* bit 2 */
02298 #define  NVIC_ISER_SETENA_3                  ((u32)0x00000008)        /* bit 3 */
02299 #define  NVIC_ISER_SETENA_4                  ((u32)0x00000010)        /* bit 4 */
02300 #define  NVIC_ISER_SETENA_5                  ((u32)0x00000020)        /* bit 5 */
02301 #define  NVIC_ISER_SETENA_6                  ((u32)0x00000040)        /* bit 6 */
02302 #define  NVIC_ISER_SETENA_7                  ((u32)0x00000080)        /* bit 7 */
02303 #define  NVIC_ISER_SETENA_8                  ((u32)0x00000100)        /* bit 8 */
02304 #define  NVIC_ISER_SETENA_9                  ((u32)0x00000200)        /* bit 9 */
02305 #define  NVIC_ISER_SETENA_10                 ((u32)0x00000400)        /* bit 10 */
02306 #define  NVIC_ISER_SETENA_11                 ((u32)0x00000800)        /* bit 11 */
02307 #define  NVIC_ISER_SETENA_12                 ((u32)0x00001000)        /* bit 12 */
02308 #define  NVIC_ISER_SETENA_13                 ((u32)0x00002000)        /* bit 13 */
02309 #define  NVIC_ISER_SETENA_14                 ((u32)0x00004000)        /* bit 14 */
02310 #define  NVIC_ISER_SETENA_15                 ((u32)0x00008000)        /* bit 15 */
02311 #define  NVIC_ISER_SETENA_16                 ((u32)0x00010000)        /* bit 16 */
02312 #define  NVIC_ISER_SETENA_17                 ((u32)0x00020000)        /* bit 17 */
02313 #define  NVIC_ISER_SETENA_18                 ((u32)0x00040000)        /* bit 18 */
02314 #define  NVIC_ISER_SETENA_19                 ((u32)0x00080000)        /* bit 19 */
02315 #define  NVIC_ISER_SETENA_20                 ((u32)0x00100000)        /* bit 20 */
02316 #define  NVIC_ISER_SETENA_21                 ((u32)0x00200000)        /* bit 21 */
02317 #define  NVIC_ISER_SETENA_22                 ((u32)0x00400000)        /* bit 22 */
02318 #define  NVIC_ISER_SETENA_23                 ((u32)0x00800000)        /* bit 23 */
02319 #define  NVIC_ISER_SETENA_24                 ((u32)0x01000000)        /* bit 24 */
02320 #define  NVIC_ISER_SETENA_25                 ((u32)0x02000000)        /* bit 25 */
02321 #define  NVIC_ISER_SETENA_26                 ((u32)0x04000000)        /* bit 26 */
02322 #define  NVIC_ISER_SETENA_27                 ((u32)0x08000000)        /* bit 27 */
02323 #define  NVIC_ISER_SETENA_28                 ((u32)0x10000000)        /* bit 28 */
02324 #define  NVIC_ISER_SETENA_29                 ((u32)0x20000000)        /* bit 29 */
02325 #define  NVIC_ISER_SETENA_30                 ((u32)0x40000000)        /* bit 30 */
02326 #define  NVIC_ISER_SETENA_31                 ((u32)0x80000000)        /* bit 31 */
02327
02328
02329
02330 /******************  Bit definition for NVIC_ICER register  *******************/
02331 #define  NVIC_ICER_CLRENA                   ((u32)0xFFFFFFFF)        /* Interrupt clear-enable bits */
02332 #define  NVIC_ICER_CLRENA_0                  ((u32)0x00000001)        /* bit 0 */
02333 #define  NVIC_ICER_CLRENA_1                  ((u32)0x00000002)        /* bit 1 */
02334 #define  NVIC_ICER_CLRENA_2                  ((u32)0x00000004)        /* bit 2 */
02335 #define  NVIC_ICER_CLRENA_3                  ((u32)0x00000008)        /* bit 3 */
02336 #define  NVIC_ICER_CLRENA_4                  ((u32)0x00000010)        /* bit 4 */
02337 #define  NVIC_ICER_CLRENA_5                  ((u32)0x00000020)        /* bit 5 */
02338 #define  NVIC_ICER_CLRENA_6                  ((u32)0x00000040)        /* bit 6 */
02339 #define  NVIC_ICER_CLRENA_7                  ((u32)0x00000080)        /* bit 7 */
02340 #define  NVIC_ICER_CLRENA_8                  ((u32)0x00000100)        /* bit 8 */
02341 #define  NVIC_ICER_CLRENA_9                  ((u32)0x00000200)        /* bit 9 */
02342 #define  NVIC_ICER_CLRENA_10                 ((u32)0x00000400)        /* bit 10 */
02343 #define  NVIC_ICER_CLRENA_11                 ((u32)0x00000800)        /* bit 11 */
02344 #define  NVIC_ICER_CLRENA_12                 ((u32)0x00001000)        /* bit 12 */
02345 #define  NVIC_ICER_CLRENA_13                 ((u32)0x00002000)        /* bit 13 */
02346 #define  NVIC_ICER_CLRENA_14                 ((u32)0x00004000)        /* bit 14 */
02347 #define  NVIC_ICER_CLRENA_15                 ((u32)0x00008000)        /* bit 15 */
02348 #define  NVIC_ICER_CLRENA_16                 ((u32)0x00010000)        /* bit 16 */
02349 #define  NVIC_ICER_CLRENA_17                 ((u32)0x00020000)        /* bit 17 */
02350 #define  NVIC_ICER_CLRENA_18                 ((u32)0x00040000)        /* bit 18 */
02351 #define  NVIC_ICER_CLRENA_19                 ((u32)0x00080000)        /* bit 19 */
02352 #define  NVIC_ICER_CLRENA_20                 ((u32)0x00100000)        /* bit 20 */
02353 #define  NVIC_ICER_CLRENA_21                 ((u32)0x00200000)        /* bit 21 */
02354 #define  NVIC_ICER_CLRENA_22                 ((u32)0x00400000)        /* bit 22 */
02355 #define  NVIC_ICER_CLRENA_23                 ((u32)0x00800000)        /* bit 23 */
02356 #define  NVIC_ICER_CLRENA_24                 ((u32)0x01000000)        /* bit 24 */
02357 #define  NVIC_ICER_CLRENA_25                 ((u32)0x02000000)        /* bit 25 */
02358 #define  NVIC_ICER_CLRENA_26                 ((u32)0x04000000)        /* bit 26 */
02359 #define  NVIC_ICER_CLRENA_27                 ((u32)0x08000000)        /* bit 27 */
02360 #define  NVIC_ICER_CLRENA_28                 ((u32)0x10000000)        /* bit 28 */
02361 #define  NVIC_ICER_CLRENA_29                 ((u32)0x20000000)        /* bit 29 */
02362 #define  NVIC_ICER_CLRENA_30                 ((u32)0x40000000)        /* bit 30 */
02363 #define  NVIC_ICER_CLRENA_31                 ((u32)0x80000000)        /* bit 31 */
02364
02365
02366 /******************  Bit definition for NVIC_ISPR register  *******************/
02367 #define  NVIC_ISPR_SETPEND                   ((u32)0xFFFFFFFF)        /* Interrupt set-pending bits */
02368 #define  NVIC_ISPR_SETPEND_0                 ((u32)0x00000001)        /* bit 0 */
02369 #define  NVIC_ISPR_SETPEND_1                 ((u32)0x00000002)        /* bit 1 */
02370 #define  NVIC_ISPR_SETPEND_2                 ((u32)0x00000004)        /* bit 2 */
02371 #define  NVIC_ISPR_SETPEND_3                 ((u32)0x00000008)        /* bit 3 */
02372 #define  NVIC_ISPR_SETPEND_4                 ((u32)0x00000010)        /* bit 4 */
02373 #define  NVIC_ISPR_SETPEND_5                 ((u32)0x00000020)        /* bit 5 */
02374 #define  NVIC_ISPR_SETPEND_6                 ((u32)0x00000040)        /* bit 6 */
02375 #define  NVIC_ISPR_SETPEND_7                 ((u32)0x00000080)        /* bit 7 */
02376 #define  NVIC_ISPR_SETPEND_8                 ((u32)0x00000100)        /* bit 8 */
02377 #define  NVIC_ISPR_SETPEND_9                 ((u32)0x00000200)        /* bit 9 */
02378 #define  NVIC_ISPR_SETPEND_10                ((u32)0x00000400)        /* bit 10 */
02379 #define  NVIC_ISPR_SETPEND_11                ((u32)0x00000800)        /* bit 11 */
02380 #define  NVIC_ISPR_SETPEND_12                ((u32)0x00001000)        /* bit 12 */
02381 #define  NVIC_ISPR_SETPEND_13                ((u32)0x00002000)        /* bit 13 */
02382 #define  NVIC_ISPR_SETPEND_14                ((u32)0x00004000)        /* bit 14 */
02383 #define  NVIC_ISPR_SETPEND_15                ((u32)0x00008000)        /* bit 15 */
02384 #define  NVIC_ISPR_SETPEND_16                ((u32)0x00010000)        /* bit 16 */
02385 #define  NVIC_ISPR_SETPEND_17                ((u32)0x00020000)        /* bit 17 */
02386 #define  NVIC_ISPR_SETPEND_18                ((u32)0x00040000)        /* bit 18 */
02387 #define  NVIC_ISPR_SETPEND_19                ((u32)0x00080000)        /* bit 19 */
02388 #define  NVIC_ISPR_SETPEND_20                ((u32)0x00100000)        /* bit 20 */
02389 #define  NVIC_ISPR_SETPEND_21                ((u32)0x00200000)        /* bit 21 */
02390 #define  NVIC_ISPR_SETPEND_22                ((u32)0x00400000)        /* bit 22 */
02391 #define  NVIC_ISPR_SETPEND_23                ((u32)0x00800000)        /* bit 23 */
02392 #define  NVIC_ISPR_SETPEND_24                ((u32)0x01000000)        /* bit 24 */
02393 #define  NVIC_ISPR_SETPEND_25                ((u32)0x02000000)        /* bit 25 */
02394 #define  NVIC_ISPR_SETPEND_26                ((u32)0x04000000)        /* bit 26 */
02395 #define  NVIC_ISPR_SETPEND_27                ((u32)0x08000000)        /* bit 27 */
02396 #define  NVIC_ISPR_SETPEND_28                ((u32)0x10000000)        /* bit 28 */
02397 #define  NVIC_ISPR_SETPEND_29                ((u32)0x20000000)        /* bit 29 */
02398 #define  NVIC_ISPR_SETPEND_30                ((u32)0x40000000)        /* bit 30 */
02399 #define  NVIC_ISPR_SETPEND_31                ((u32)0x80000000)        /* bit 31 */
02400
02401
02402 /******************  Bit definition for NVIC_ICPR register  *******************/
02403 #define  NVIC_ICPR_CLRPEND                   ((u32)0xFFFFFFFF)        /* Interrupt clear-pending bits */
02404 #define  NVIC_ICPR_CLRPEND_0                 ((u32)0x00000001)        /* bit 0 */
02405 #define  NVIC_ICPR_CLRPEND_1                 ((u32)0x00000002)        /* bit 1 */
02406 #define  NVIC_ICPR_CLRPEND_2                 ((u32)0x00000004)        /* bit 2 */
02407 #define  NVIC_ICPR_CLRPEND_3                 ((u32)0x00000008)        /* bit 3 */
02408 #define  NVIC_ICPR_CLRPEND_4                 ((u32)0x00000010)        /* bit 4 */
02409 #define  NVIC_ICPR_CLRPEND_5                 ((u32)0x00000020)        /* bit 5 */
02410 #define  NVIC_ICPR_CLRPEND_6                 ((u32)0x00000040)        /* bit 6 */
02411 #define  NVIC_ICPR_CLRPEND_7                 ((u32)0x00000080)        /* bit 7 */
02412 #define  NVIC_ICPR_CLRPEND_8                 ((u32)0x00000100)        /* bit 8 */
02413 #define  NVIC_ICPR_CLRPEND_9                 ((u32)0x00000200)        /* bit 9 */
02414 #define  NVIC_ICPR_CLRPEND_10                ((u32)0x00000400)        /* bit 10 */
02415 #define  NVIC_ICPR_CLRPEND_11                ((u32)0x00000800)        /* bit 11 */
02416 #define  NVIC_ICPR_CLRPEND_12                ((u32)0x00001000)        /* bit 12 */
02417 #define  NVIC_ICPR_CLRPEND_13                ((u32)0x00002000)        /* bit 13 */
02418 #define  NVIC_ICPR_CLRPEND_14                ((u32)0x00004000)        /* bit 14 */
02419 #define  NVIC_ICPR_CLRPEND_15                ((u32)0x00008000)        /* bit 15 */
02420 #define  NVIC_ICPR_CLRPEND_16                ((u32)0x00010000)        /* bit 16 */
02421 #define  NVIC_ICPR_CLRPEND_17                ((u32)0x00020000)        /* bit 17 */
02422 #define  NVIC_ICPR_CLRPEND_18                ((u32)0x00040000)        /* bit 18 */
02423 #define  NVIC_ICPR_CLRPEND_19                ((u32)0x00080000)        /* bit 19 */
02424 #define  NVIC_ICPR_CLRPEND_20                ((u32)0x00100000)        /* bit 20 */
02425 #define  NVIC_ICPR_CLRPEND_21                ((u32)0x00200000)        /* bit 21 */
02426 #define  NVIC_ICPR_CLRPEND_22                ((u32)0x00400000)        /* bit 22 */
02427 #define  NVIC_ICPR_CLRPEND_23                ((u32)0x00800000)        /* bit 23 */
02428 #define  NVIC_ICPR_CLRPEND_24                ((u32)0x01000000)        /* bit 24 */
02429 #define  NVIC_ICPR_CLRPEND_25                ((u32)0x02000000)        /* bit 25 */
02430 #define  NVIC_ICPR_CLRPEND_26                ((u32)0x04000000)        /* bit 26 */
02431 #define  NVIC_ICPR_CLRPEND_27                ((u32)0x08000000)        /* bit 27 */
02432 #define  NVIC_ICPR_CLRPEND_28                ((u32)0x10000000)        /* bit 28 */
02433 #define  NVIC_ICPR_CLRPEND_29                ((u32)0x20000000)        /* bit 29 */
02434 #define  NVIC_ICPR_CLRPEND_30                ((u32)0x40000000)        /* bit 30 */
02435 #define  NVIC_ICPR_CLRPEND_31                ((u32)0x80000000)        /* bit 31 */
02436
02437
02438 /******************  Bit definition for NVIC_IABR register  *******************/
02439 #define  NVIC_IABR_ACTIVE                    ((u32)0xFFFFFFFF)        /* Interrupt active flags */
02440 #define  NVIC_IABR_ACTIVE_0                  ((u32)0x00000001)        /* bit 0 */
02441 #define  NVIC_IABR_ACTIVE_1                  ((u32)0x00000002)        /* bit 1 */
02442 #define  NVIC_IABR_ACTIVE_2                  ((u32)0x00000004)        /* bit 2 */
02443 #define  NVIC_IABR_ACTIVE_3                  ((u32)0x00000008)        /* bit 3 */
02444 #define  NVIC_IABR_ACTIVE_4                  ((u32)0x00000010)        /* bit 4 */
02445 #define  NVIC_IABR_ACTIVE_5                  ((u32)0x00000020)        /* bit 5 */
02446 #define  NVIC_IABR_ACTIVE_6                  ((u32)0x00000040)        /* bit 6 */
02447 #define  NVIC_IABR_ACTIVE_7                  ((u32)0x00000080)        /* bit 7 */
02448 #define  NVIC_IABR_ACTIVE_8                  ((u32)0x00000100)        /* bit 8 */
02449 #define  NVIC_IABR_ACTIVE_9                  ((u32)0x00000200)        /* bit 9 */
02450 #define  NVIC_IABR_ACTIVE_10                 ((u32)0x00000400)        /* bit 10 */
02451 #define  NVIC_IABR_ACTIVE_11                 ((u32)0x00000800)        /* bit 11 */
02452 #define  NVIC_IABR_ACTIVE_12                 ((u32)0x00001000)        /* bit 12 */
02453 #define  NVIC_IABR_ACTIVE_13                 ((u32)0x00002000)        /* bit 13 */
02454 #define  NVIC_IABR_ACTIVE_14                 ((u32)0x00004000)        /* bit 14 */
02455 #define  NVIC_IABR_ACTIVE_15                 ((u32)0x00008000)        /* bit 15 */
02456 #define  NVIC_IABR_ACTIVE_16                 ((u32)0x00010000)        /* bit 16 */
02457 #define  NVIC_IABR_ACTIVE_17                 ((u32)0x00020000)        /* bit 17 */
02458 #define  NVIC_IABR_ACTIVE_18                 ((u32)0x00040000)        /* bit 18 */
02459 #define  NVIC_IABR_ACTIVE_19                 ((u32)0x00080000)        /* bit 19 */
02460 #define  NVIC_IABR_ACTIVE_20                 ((u32)0x00100000)        /* bit 20 */
02461 #define  NVIC_IABR_ACTIVE_21                 ((u32)0x00200000)        /* bit 21 */
02462 #define  NVIC_IABR_ACTIVE_22                 ((u32)0x00400000)        /* bit 22 */
02463 #define  NVIC_IABR_ACTIVE_23                 ((u32)0x00800000)        /* bit 23 */
02464 #define  NVIC_IABR_ACTIVE_24                 ((u32)0x01000000)        /* bit 24 */
02465 #define  NVIC_IABR_ACTIVE_25                 ((u32)0x02000000)        /* bit 25 */
02466 #define  NVIC_IABR_ACTIVE_26                 ((u32)0x04000000)        /* bit 26 */
02467 #define  NVIC_IABR_ACTIVE_27                 ((u32)0x08000000)        /* bit 27 */
02468 #define  NVIC_IABR_ACTIVE_28                 ((u32)0x10000000)        /* bit 28 */
02469 #define  NVIC_IABR_ACTIVE_29                 ((u32)0x20000000)        /* bit 29 */
02470 #define  NVIC_IABR_ACTIVE_30                 ((u32)0x40000000)        /* bit 30 */
02471 #define  NVIC_IABR_ACTIVE_31                 ((u32)0x80000000)        /* bit 31 */
02472
02473
02474 /******************  Bit definition for NVIC_PRI0 register  *******************/
02475 #define  NVIC_IPR0_PRI_0                     ((u32)0x000000FF)        /* Priority of interrupt 0 */
02476 #define  NVIC_IPR0_PRI_1                     ((u32)0x0000FF00)        /* Priority of interrupt 1 */
02477 #define  NVIC_IPR0_PRI_2                     ((u32)0x00FF0000)        /* Priority of interrupt 2 */
02478 #define  NVIC_IPR0_PRI_3                     ((u32)0xFF000000)        /* Priority of interrupt 3 */
02479
02480
02481 /******************  Bit definition for NVIC_PRI1 register  *******************/
02482 #define  NVIC_IPR1_PRI_4                     ((u32)0x000000FF)        /* Priority of interrupt 4 */
02483 #define  NVIC_IPR1_PRI_5                     ((u32)0x0000FF00)        /* Priority of interrupt 5 */
02484 #define  NVIC_IPR1_PRI_6                     ((u32)0x00FF0000)        /* Priority of interrupt 6 */
02485 #define  NVIC_IPR1_PRI_7                     ((u32)0xFF000000)        /* Priority of interrupt 7 */
02486
02487
02488 /******************  Bit definition for NVIC_PRI2 register  *******************/
02489 #define  NVIC_IPR2_PRI_8                     ((u32)0x000000FF)        /* Priority of interrupt 8 */
02490 #define  NVIC_IPR2_PRI_9                     ((u32)0x0000FF00)        /* Priority of interrupt 9 */
02491 #define  NVIC_IPR2_PRI_10                    ((u32)0x00FF0000)        /* Priority of interrupt 10 */
02492 #define  NVIC_IPR2_PRI_11                    ((u32)0xFF000000)        /* Priority of interrupt 11 */
02493
02494
02495 /******************  Bit definition for NVIC_PRI3 register  *******************/
02496 #define  NVIC_IPR3_PRI_12                    ((u32)0x000000FF)        /* Priority of interrupt 12 */
02497 #define  NVIC_IPR3_PRI_13                    ((u32)0x0000FF00)        /* Priority of interrupt 13 */
02498 #define  NVIC_IPR3_PRI_14                    ((u32)0x00FF0000)        /* Priority of interrupt 14 */
02499 #define  NVIC_IPR3_PRI_15                    ((u32)0xFF000000)        /* Priority of interrupt 15 */
02500
02501
02502 /******************  Bit definition for NVIC_PRI4 register  *******************/
02503 #define  NVIC_IPR4_PRI_16                    ((u32)0x000000FF)        /* Priority of interrupt 16 */
02504 #define  NVIC_IPR4_PRI_17                    ((u32)0x0000FF00)        /* Priority of interrupt 17 */
02505 #define  NVIC_IPR4_PRI_18                    ((u32)0x00FF0000)        /* Priority of interrupt 18 */
02506 #define  NVIC_IPR4_PRI_19                    ((u32)0xFF000000)        /* Priority of interrupt 19 */
02507
02508
02509 /******************  Bit definition for NVIC_PRI5 register  *******************/
02510 #define  NVIC_IPR5_PRI_20                    ((u32)0x000000FF)        /* Priority of interrupt 20 */
02511 #define  NVIC_IPR5_PRI_21                    ((u32)0x0000FF00)        /* Priority of interrupt 21 */
02512 #define  NVIC_IPR5_PRI_22                    ((u32)0x00FF0000)        /* Priority of interrupt 22 */
02513 #define  NVIC_IPR5_PRI_23                    ((u32)0xFF000000)        /* Priority of interrupt 23 */
02514
02515
02516 /******************  Bit definition for NVIC_PRI6 register  *******************/
02517 #define  NVIC_IPR6_PRI_24                    ((u32)0x000000FF)        /* Priority of interrupt 24 */
02518 #define  NVIC_IPR6_PRI_25                    ((u32)0x0000FF00)        /* Priority of interrupt 25 */
02519 #define  NVIC_IPR6_PRI_26                    ((u32)0x00FF0000)        /* Priority of interrupt 26 */
02520 #define  NVIC_IPR6_PRI_27                    ((u32)0xFF000000)        /* Priority of interrupt 27 */
02521
02522
02523 /******************  Bit definition for NVIC_PRI7 register  *******************/
02524 #define  NVIC_IPR7_PRI_28                    ((u32)0x000000FF)        /* Priority of interrupt 28 */
02525 #define  NVIC_IPR7_PRI_29                    ((u32)0x0000FF00)        /* Priority of interrupt 29 */
02526 #define  NVIC_IPR7_PRI_30                    ((u32)0x00FF0000)        /* Priority of interrupt 30 */
02527 #define  NVIC_IPR7_PRI_31                    ((u32)0xFF000000)        /* Priority of interrupt 31 */
02528
02529
02530 /******************  Bit definition for SCB_CPUID register  *******************/
02531 #define  SCB_CPUID_REVISION                  ((u32)0x0000000F)        /* Implementation defined revision number */
02532 #define  SCB_CPUID_PARTNO                    ((u32)0x0000FFF0)        /* Number of processor within family */
02533 #define  SCB_CPUID_Constant                  ((u32)0x000F0000)        /* Reads as 0x0F */
02534 #define  SCB_CPUID_VARIANT                   ((u32)0x00F00000)        /* Implementation defined variant number */
02535 #define  SCB_CPUID_IMPLEMENTER               ((u32)0xFF000000)        /* Implementer code. ARM is 0x41 */
02536
02537
02538 /*******************  Bit definition for SCB_ICSR register  *******************/
02539 #define  SCB_ICSR_VECTACTIVE                 ((u32)0x000001FF)        /* Active ISR number field */
02540 #define  SCB_ICSR_RETTOBASE                  ((u32)0x00000800)        /* All active exceptions minus the IPSR_current_exception yields the empty set */
02541 #define  SCB_ICSR_VECTPENDING                ((u32)0x003FF000)        /* Pending ISR number field */
02542 #define  SCB_ICSR_ISRPENDING                 ((u32)0x00400000)        /* Interrupt pending flag */
02543 #define  SCB_ICSR_ISRPREEMPT                 ((u32)0x00800000)        /* It indicates that a pending interrupt becomes active in the next running cycle */
02544 #define  SCB_ICSR_PENDSTCLR                  ((u32)0x02000000)        /* Clear pending SysTick bit */
02545 #define  SCB_ICSR_PENDSTSET                  ((u32)0x04000000)        /* Set pending SysTick bit */
02546 #define  SCB_ICSR_PENDSVCLR                  ((u32)0x08000000)        /* Clear pending pendSV bit */
02547 #define  SCB_ICSR_PENDSVSET                  ((u32)0x10000000)        /* Set pending pendSV bit */
02548 #define  SCB_ICSR_NMIPENDSET                 ((u32)0x80000000)        /* Set pending NMI bit */
02549
02550
02551 /*******************  Bit definition for SCB_VTOR register  *******************/
02552 #define  SCB_VTOR_TBLOFF                     ((u32)0x1FFFFF80)        /* Vector table base offset field */
02553 #define  SCB_VTOR_TBLBASE                    ((u32)0x20000000)        /* Table base in code(0) or RAM(1) */
02554
02555
02556 /******************  Bit definition for SCB_AIRCR register  *******************/
02557 #define  SCB_AIRCR_VECTRESET                 ((u32)0x00000001)        /* System Reset bit */
02558 #define  SCB_AIRCR_VECTCLRACTIVE             ((u32)0x00000002)        /* Clear active vector bit */
02559 #define  SCB_AIRCR_SYSRESETREQ               ((u32)0x00000004)        /* Requests chip control logic to generate a reset */
02560
02561 #define  SCB_AIRCR_PRIGROUP                  ((u32)0x00000700)        /* PRIGROUP[2:0] bits (Priority group) */
02562 #define  SCB_AIRCR_PRIGROUP_0                ((u32)0x00000100)        /* Bit 0 */
02563 #define  SCB_AIRCR_PRIGROUP_1                ((u32)0x00000200)        /* Bit 1 */
02564 #define  SCB_AIRCR_PRIGROUP_2                ((u32)0x00000400)        /* Bit 2  */
02565
02566 /* prority group configuration */
02567 #define  SCB_AIRCR_PRIGROUP0                 ((u32)0x00000000)        /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
02568 #define  SCB_AIRCR_PRIGROUP1                 ((u32)0x00000100)        /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
02569 #define  SCB_AIRCR_PRIGROUP2                 ((u32)0x00000200)        /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
02570 #define  SCB_AIRCR_PRIGROUP3                 ((u32)0x00000300)        /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
02571 #define  SCB_AIRCR_PRIGROUP4                 ((u32)0x00000400)        /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
02572 #define  SCB_AIRCR_PRIGROUP5                 ((u32)0x00000500)        /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
02573 #define  SCB_AIRCR_PRIGROUP6                 ((u32)0x00000600)        /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
02574 #define  SCB_AIRCR_PRIGROUP7                 ((u32)0x00000700)        /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
02575
02576 #define  SCB_AIRCR_ENDIANESS                 ((u32)0x00008000)        /* Data endianness bit */
02577 #define  SCB_AIRCR_VECTKEY                   ((u32)0xFFFF0000)        /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
02578
02579
02580 /*******************  Bit definition for SCB_SCR register  ********************/
02581 #define  SCB_SCR_SLEEPONEXIT                 ((u8)0x02)               /* Sleep on exit bit */
02582 #define  SCB_SCR_SLEEPDEEP                   ((u8)0x04)               /* Sleep deep bit */
02583 #define  SCB_SCR_SEVONPEND                   ((u8)0x10)               /* Wake up from WFE */
02584
02585
02586 /********************  Bit definition for SCB_CCR register  *******************/
02587 #define  SCB_CCR_NONBASETHRDENA              ((u16)0x0001)            /* Thread mode can be entered from any level in Handler mode by controlled return value */
02588 #define  SCB_CCR_USERSETMPEND                ((u16)0x0002)            /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
02589 #define  SCB_CCR_UNALIGN_TRP                 ((u16)0x0008)            /* Trap for unaligned access */
02590 #define  SCB_CCR_DIV_0_TRP                   ((u16)0x0010)            /* Trap on Divide by 0 */
02591 #define  SCB_CCR_BFHFNMIGN                   ((u16)0x0100)            /* Handlers running at priority -1 and -2 */
02592 #define  SCB_CCR_STKALIGN                    ((u16)0x0200)            /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
02593
02594
02595 /*******************  Bit definition for SCB_SHPR register ********************/
02596 #define  SCB_SHPR_PRI_N                      ((u32)0x000000FF)        /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
02597 #define  SCB_SHPR_PRI_N1                     ((u32)0x0000FF00)        /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
02598 #define  SCB_SHPR_PRI_N2                     ((u32)0x00FF0000)        /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
02599 #define  SCB_SHPR_PRI_N3                     ((u32)0xFF000000)        /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
02600
02601
02602 /******************  Bit definition for SCB_SHCSR register  *******************/
02603 #define  SCB_SHCSR_MEMFAULTACT               ((u32)0x00000001)        /* MemManage is active */
02604 #define  SCB_SHCSR_BUSFAULTACT               ((u32)0x00000002)        /* BusFault is active */
02605 #define  SCB_SHCSR_USGFAULTACT               ((u32)0x00000008)        /* UsageFault is active */
02606 #define  SCB_SHCSR_SVCALLACT                 ((u32)0x00000080)        /* SVCall is active */
02607 #define  SCB_SHCSR_MONITORACT                ((u32)0x00000100)        /* Monitor is active */
02608 #define  SCB_SHCSR_PENDSVACT                 ((u32)0x00000400)        /* PendSV is active */
02609 #define  SCB_SHCSR_SYSTICKACT                ((u32)0x00000800)        /* SysTick is active */
02610 #define  SCB_SHCSR_USGFAULTPENDED            ((u32)0x00001000)        /* Usage Fault is pended */
02611 #define  SCB_SHCSR_MEMFAULTPENDED            ((u32)0x00002000)        /* MemManage is pended */
02612 #define  SCB_SHCSR_BUSFAULTPENDED            ((u32)0x00004000)        /* Bus Fault is pended */
02613 #define  SCB_SHCSR_SVCALLPENDED              ((u32)0x00008000)        /* SVCall is pended */
02614 #define  SCB_SHCSR_MEMFAULTENA               ((u32)0x00010000)        /* MemManage enable */
02615 #define  SCB_SHCSR_BUSFAULTENA               ((u32)0x00020000)        /* Bus Fault enable */
02616 #define  SCB_SHCSR_USGFAULTENA               ((u32)0x00040000)        /* UsageFault enable */
02617
02618
02619 /*******************  Bit definition for SCB_CFSR register  *******************/
02620 /* MFSR */
02621 #define  SCB_CFSR_IACCVIOL                   ((u32)0x00000001)        /* Instruction access violation */
02622 #define  SCB_CFSR_DACCVIOL                   ((u32)0x00000002)        /* Data access violation */
02623 #define  SCB_CFSR_MUNSTKERR                  ((u32)0x00000008)        /* Unstacking error */
02624 #define  SCB_CFSR_MSTKERR                    ((u32)0x00000010)        /* Stacking error */
02625 #define  SCB_CFSR_MMARVALID                  ((u32)0x00000080)        /* Memory Manage Address Register address valid flag */
02626 /* BFSR */
02627 #define  SCB_CFSR_IBUSERR                    ((u32)0x00000100)        /* Instruction bus error flag */
02628 #define  SCB_CFSR_PRECISERR                  ((u32)0x00000200)        /* Precise data bus error */
02629 #define  SCB_CFSR_IMPRECISERR                ((u32)0x00000400)        /* Imprecise data bus error */
02630 #define  SCB_CFSR_UNSTKERR                   ((u32)0x00000800)        /* Unstacking error */
02631 #define  SCB_CFSR_STKERR                     ((u32)0x00001000)        /* Stacking error */
02632 #define  SCB_CFSR_BFARVALID                  ((u32)0x00008000)        /* Bus Fault Address Register address valid flag */
02633 /* UFSR */
02634 #define  SCB_CFSR_UNDEFINSTR                 ((u32)0x00010000)        /* The processor attempt to excecute an undefined instruction */
02635 #define  SCB_CFSR_INVSTATE                   ((u32)0x00020000)        /* Invalid combination of EPSR and instruction */
02636 #define  SCB_CFSR_INVPC                      ((u32)0x00040000)        /* Attempt to load EXC_RETURN into pc illegally */
02637 #define  SCB_CFSR_NOCP                       ((u32)0x00080000)        /* Attempt to use a coprocessor instruction */
02638 #define  SCB_CFSR_UNALIGNED                  ((u32)0x01000000)        /* Fault occurs when there is an attempt to make an unaligned memory access */
02639 #define  SCB_CFSR_DIVBYZERO                  ((u32)0x02000000)        /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
02640
02641
02642 /*******************  Bit definition for SCB_HFSR register  *******************/
02643 #define  SCB_HFSR_VECTTBL                    ((u32)0x00000002)        /* Fault occures because of vector table read on exception processing */
02644 #define  SCB_HFSR_FORCED                     ((u32)0x40000000)        /* Hard Fault activated when a configurable Fault was received and cannot activate */
02645 #define  SCB_HFSR_DEBUGEVT                   ((u32)0x80000000)        /* Fault related to debug */
02646
02647
02648 /*******************  Bit definition for SCB_DFSR register  *******************/
02649 #define  SCB_DFSR_HALTED                     ((u8)0x01)               /* Halt request flag */
02650 #define  SCB_DFSR_BKPT                       ((u8)0x02)               /* BKPT flag */
02651 #define  SCB_DFSR_DWTTRAP                    ((u8)0x04)               /* Data Watchpoint and Trace (DWT) flag */
02652 #define  SCB_DFSR_VCATCH                     ((u8)0x08)               /* Vector catch flag */
02653 #define  SCB_DFSR_EXTERNAL                   ((u8)0x10)               /* External debug request flag */
02654
02655
02656 /*******************  Bit definition for SCB_MMFAR register  ******************/
02657 #define  SCB_MMFAR_ADDRESS                   ((u32)0xFFFFFFFF)        /* Mem Manage fault address field */
02658
02659
02660 /*******************  Bit definition for SCB_BFAR register  *******************/
02661 #define  SCB_BFAR_ADDRESS                    ((u32)0xFFFFFFFF)        /* Bus fault address field */
02662
02663
02664 /*******************  Bit definition for SCB_afsr register  *******************/
02665 #define  SCB_AFSR_IMPDEF                     ((u32)0xFFFFFFFF)        /* Implementation defined */
02666
02667
02668
02669 /******************************************************************************/
02670 /*                                                                            */
02671 /*                    External Interrupt/Event Controller                     */
02672 /*                                                                            */
02673 /******************************************************************************/
02674
02675 /*******************  Bit definition for EXTI_IMR register  *******************/
02676 #define  EXTI_IMR_MR0                        ((u32)0x00000001)        /* Interrupt Mask on line 0 */
02677 #define  EXTI_IMR_MR1                        ((u32)0x00000002)        /* Interrupt Mask on line 1 */
02678 #define  EXTI_IMR_MR2                        ((u32)0x00000004)        /* Interrupt Mask on line 2 */
02679 #define  EXTI_IMR_MR3                        ((u32)0x00000008)        /* Interrupt Mask on line 3 */
02680 #define  EXTI_IMR_MR4                        ((u32)0x00000010)        /* Interrupt Mask on line 4 */
02681 #define  EXTI_IMR_MR5                        ((u32)0x00000020)        /* Interrupt Mask on line 5 */
02682 #define  EXTI_IMR_MR6                        ((u32)0x00000040)        /* Interrupt Mask on line 6 */
02683 #define  EXTI_IMR_MR7                        ((u32)0x00000080)        /* Interrupt Mask on line 7 */
02684 #define  EXTI_IMR_MR8                        ((u32)0x00000100)        /* Interrupt Mask on line 8 */
02685 #define  EXTI_IMR_MR9                        ((u32)0x00000200)        /* Interrupt Mask on line 9 */
02686 #define  EXTI_IMR_MR10                       ((u32)0x00000400)        /* Interrupt Mask on line 10 */
02687 #define  EXTI_IMR_MR11                       ((u32)0x00000800)        /* Interrupt Mask on line 11 */
02688 #define  EXTI_IMR_MR12                       ((u32)0x00001000)        /* Interrupt Mask on line 12 */
02689 #define  EXTI_IMR_MR13                       ((u32)0x00002000)        /* Interrupt Mask on line 13 */
02690 #define  EXTI_IMR_MR14                       ((u32)0x00004000)        /* Interrupt Mask on line 14 */
02691 #define  EXTI_IMR_MR15                       ((u32)0x00008000)        /* Interrupt Mask on line 15 */
02692 #define  EXTI_IMR_MR16                       ((u32)0x00010000)        /* Interrupt Mask on line 16 */
02693 #define  EXTI_IMR_MR17                       ((u32)0x00020000)        /* Interrupt Mask on line 17 */
02694 #define  EXTI_IMR_MR18                       ((u32)0x00040000)        /* Interrupt Mask on line 18 */
02695
02696
02697 /*******************  Bit definition for EXTI_EMR register  *******************/
02698 #define  EXTI_EMR_MR0                        ((u32)0x00000001)        /* Event Mask on line 0 */
02699 #define  EXTI_EMR_MR1                        ((u32)0x00000002)        /* Event Mask on line 1 */
02700 #define  EXTI_EMR_MR2                        ((u32)0x00000004)        /* Event Mask on line 2 */
02701 #define  EXTI_EMR_MR3                        ((u32)0x00000008)        /* Event Mask on line 3 */
02702 #define  EXTI_EMR_MR4                        ((u32)0x00000010)        /* Event Mask on line 4 */
02703 #define  EXTI_EMR_MR5                        ((u32)0x00000020)        /* Event Mask on line 5 */
02704 #define  EXTI_EMR_MR6                        ((u32)0x00000040)        /* Event Mask on line 6 */
02705 #define  EXTI_EMR_MR7                        ((u32)0x00000080)        /* Event Mask on line 7 */
02706 #define  EXTI_EMR_MR8                        ((u32)0x00000100)        /* Event Mask on line 8 */
02707 #define  EXTI_EMR_MR9                        ((u32)0x00000200)        /* Event Mask on line 9 */
02708 #define  EXTI_EMR_MR10                       ((u32)0x00000400)        /* Event Mask on line 10 */
02709 #define  EXTI_EMR_MR11                       ((u32)0x00000800)        /* Event Mask on line 11 */
02710 #define  EXTI_EMR_MR12                       ((u32)0x00001000)        /* Event Mask on line 12 */
02711 #define  EXTI_EMR_MR13                       ((u32)0x00002000)        /* Event Mask on line 13 */
02712 #define  EXTI_EMR_MR14                       ((u32)0x00004000)        /* Event Mask on line 14 */
02713 #define  EXTI_EMR_MR15                       ((u32)0x00008000)        /* Event Mask on line 15 */
02714 #define  EXTI_EMR_MR16                       ((u32)0x00010000)        /* Event Mask on line 16 */
02715 #define  EXTI_EMR_MR17                       ((u32)0x00020000)        /* Event Mask on line 17 */
02716 #define  EXTI_EMR_MR18                       ((u32)0x00040000)        /* Event Mask on line 18 */
02717
02718
02719 /******************  Bit definition for EXTI_RTSR register  *******************/
02720 #define  EXTI_RTSR_TR0                       ((u32)0x00000001)        /* Rising trigger event configuration bit of line 0 */
02721 #define  EXTI_RTSR_TR1                       ((u32)0x00000002)        /* Rising trigger event configuration bit of line 1 */
02722 #define  EXTI_RTSR_TR2                       ((u32)0x00000004)        /* Rising trigger event configuration bit of line 2 */
02723 #define  EXTI_RTSR_TR3                       ((u32)0x00000008)        /* Rising trigger event configuration bit of line 3 */
02724 #define  EXTI_RTSR_TR4                       ((u32)0x00000010)        /* Rising trigger event configuration bit of line 4 */
02725 #define  EXTI_RTSR_TR5                       ((u32)0x00000020)        /* Rising trigger event configuration bit of line 5 */
02726 #define  EXTI_RTSR_TR6                       ((u32)0x00000040)        /* Rising trigger event configuration bit of line 6 */
02727 #define  EXTI_RTSR_TR7                       ((u32)0x00000080)        /* Rising trigger event configuration bit of line 7 */
02728 #define  EXTI_RTSR_TR8                       ((u32)0x00000100)        /* Rising trigger event configuration bit of line 8 */
02729 #define  EXTI_RTSR_TR9                       ((u32)0x00000200)        /* Rising trigger event configuration bit of line 9 */
02730 #define  EXTI_RTSR_TR10                      ((u32)0x00000400)        /* Rising trigger event configuration bit of line 10 */
02731 #define  EXTI_RTSR_TR11                      ((u32)0x00000800)        /* Rising trigger event configuration bit of line 11 */
02732 #define  EXTI_RTSR_TR12                      ((u32)0x00001000)        /* Rising trigger event configuration bit of line 12 */
02733 #define  EXTI_RTSR_TR13                      ((u32)0x00002000)        /* Rising trigger event configuration bit of line 13 */
02734 #define  EXTI_RTSR_TR14                      ((u32)0x00004000)        /* Rising trigger event configuration bit of line 14 */
02735 #define  EXTI_RTSR_TR15                      ((u32)0x00008000)        /* Rising trigger event configuration bit of line 15 */
02736 #define  EXTI_RTSR_TR16                      ((u32)0x00010000)        /* Rising trigger event configuration bit of line 16 */
02737 #define  EXTI_RTSR_TR17                      ((u32)0x00020000)        /* Rising trigger event configuration bit of line 17 */
02738 #define  EXTI_RTSR_TR18                      ((u32)0x00040000)        /* Rising trigger event configuration bit of line 18 */
02739
02740
02741 /******************  Bit definition for EXTI_FTSR register  *******************/
02742 #define  EXTI_FTSR_TR0                       ((u32)0x00000001)        /* Falling trigger event configuration bit of line 0 */
02743 #define  EXTI_FTSR_TR1                       ((u32)0x00000002)        /* Falling trigger event configuration bit of line 1 */
02744 #define  EXTI_FTSR_TR2                       ((u32)0x00000004)        /* Falling trigger event configuration bit of line 2 */
02745 #define  EXTI_FTSR_TR3                       ((u32)0x00000008)        /* Falling trigger event configuration bit of line 3 */
02746 #define  EXTI_FTSR_TR4                       ((u32)0x00000010)        /* Falling trigger event configuration bit of line 4 */
02747 #define  EXTI_FTSR_TR5                       ((u32)0x00000020)        /* Falling trigger event configuration bit of line 5 */
02748 #define  EXTI_FTSR_TR6                       ((u32)0x00000040)        /* Falling trigger event configuration bit of line 6 */
02749 #define  EXTI_FTSR_TR7                       ((u32)0x00000080)        /* Falling trigger event configuration bit of line 7 */
02750 #define  EXTI_FTSR_TR8                       ((u32)0x00000100)        /* Falling trigger event configuration bit of line 8 */
02751 #define  EXTI_FTSR_TR9                       ((u32)0x00000200)        /* Falling trigger event configuration bit of line 9 */
02752 #define  EXTI_FTSR_TR10                      ((u32)0x00000400)        /* Falling trigger event configuration bit of line 10 */
02753 #define  EXTI_FTSR_TR11                      ((u32)0x00000800)        /* Falling trigger event configuration bit of line 11 */
02754 #define  EXTI_FTSR_TR12                      ((u32)0x00001000)        /* Falling trigger event configuration bit of line 12 */
02755 #define  EXTI_FTSR_TR13                      ((u32)0x00002000)        /* Falling trigger event configuration bit of line 13 */
02756 #define  EXTI_FTSR_TR14                      ((u32)0x00004000)        /* Falling trigger event configuration bit of line 14 */
02757 #define  EXTI_FTSR_TR15                      ((u32)0x00008000)        /* Falling trigger event configuration bit of line 15 */
02758 #define  EXTI_FTSR_TR16                      ((u32)0x00010000)        /* Falling trigger event configuration bit of line 16 */
02759 #define  EXTI_FTSR_TR17                      ((u32)0x00020000)        /* Falling trigger event configuration bit of line 17 */
02760 #define  EXTI_FTSR_TR18                      ((u32)0x00040000)        /* Falling trigger event configuration bit of line 18 */
02761
02762
02763 /******************  Bit definition for EXTI_SWIER register  ******************/
02764 #define  EXTI_SWIER_SWIER0                   ((u32)0x00000001)        /* Software Interrupt on line 0 */
02765 #define  EXTI_SWIER_SWIER1                   ((u32)0x00000002)        /* Software Interrupt on line 1 */
02766 #define  EXTI_SWIER_SWIER2                   ((u32)0x00000004)        /* Software Interrupt on line 2 */
02767 #define  EXTI_SWIER_SWIER3                   ((u32)0x00000008)        /* Software Interrupt on line 3 */
02768 #define  EXTI_SWIER_SWIER4                   ((u32)0x00000010)        /* Software Interrupt on line 4 */
02769 #define  EXTI_SWIER_SWIER5                   ((u32)0x00000020)        /* Software Interrupt on line 5 */
02770 #define  EXTI_SWIER_SWIER6                   ((u32)0x00000040)        /* Software Interrupt on line 6 */
02771 #define  EXTI_SWIER_SWIER7                   ((u32)0x00000080)        /* Software Interrupt on line 7 */
02772 #define  EXTI_SWIER_SWIER8                   ((u32)0x00000100)        /* Software Interrupt on line 8 */
02773 #define  EXTI_SWIER_SWIER9                   ((u32)0x00000200)        /* Software Interrupt on line 9 */
02774 #define  EXTI_SWIER_SWIER10                  ((u32)0x00000400)        /* Software Interrupt on line 10 */
02775 #define  EXTI_SWIER_SWIER11                  ((u32)0x00000800)        /* Software Interrupt on line 11 */
02776 #define  EXTI_SWIER_SWIER12                  ((u32)0x00001000)        /* Software Interrupt on line 12 */
02777 #define  EXTI_SWIER_SWIER13                  ((u32)0x00002000)        /* Software Interrupt on line 13 */
02778 #define  EXTI_SWIER_SWIER14                  ((u32)0x00004000)        /* Software Interrupt on line 14 */
02779 #define  EXTI_SWIER_SWIER15                  ((u32)0x00008000)        /* Software Interrupt on line 15 */
02780 #define  EXTI_SWIER_SWIER16                  ((u32)0x00010000)        /* Software Interrupt on line 16 */
02781 #define  EXTI_SWIER_SWIER17                  ((u32)0x00020000)        /* Software Interrupt on line 17 */
02782 #define  EXTI_SWIER_SWIER18                  ((u32)0x00040000)        /* Software Interrupt on line 18 */
02783
02784
02785 /*******************  Bit definition for EXTI_PR register  ********************/
02786 #define  EXTI_PR_PR0                         ((u32)0x00000001)        /* Pending bit 0 */
02787 #define  EXTI_PR_PR1                         ((u32)0x00000002)        /* Pending bit 1 */
02788 #define  EXTI_PR_PR2                         ((u32)0x00000004)        /* Pending bit 2 */
02789 #define  EXTI_PR_PR3                         ((u32)0x00000008)        /* Pending bit 3 */
02790 #define  EXTI_PR_PR4                         ((u32)0x00000010)        /* Pending bit 4 */
02791 #define  EXTI_PR_PR5                         ((u32)0x00000020)        /* Pending bit 5 */
02792 #define  EXTI_PR_PR6                         ((u32)0x00000040)        /* Pending bit 6 */
02793 #define  EXTI_PR_PR7                         ((u32)0x00000080)        /* Pending bit 7 */
02794 #define  EXTI_PR_PR8                         ((u32)0x00000100)        /* Pending bit 8 */
02795 #define  EXTI_PR_PR9                         ((u32)0x00000200)        /* Pending bit 9 */
02796 #define  EXTI_PR_PR10                        ((u32)0x00000400)        /* Pending bit 10 */
02797 #define  EXTI_PR_PR11                        ((u32)0x00000800)        /* Pending bit 11 */
02798 #define  EXTI_PR_PR12                        ((u32)0x00001000)        /* Pending bit 12 */
02799 #define  EXTI_PR_PR13                        ((u32)0x00002000)        /* Pending bit 13 */
02800 #define  EXTI_PR_PR14                        ((u32)0x00004000)        /* Pending bit 14 */
02801 #define  EXTI_PR_PR15                        ((u32)0x00008000)        /* Pending bit 15 */
02802 #define  EXTI_PR_PR16                        ((u32)0x00010000)        /* Pending bit 16 */
02803 #define  EXTI_PR_PR17                        ((u32)0x00020000)        /* Pending bit 17 */
02804 #define  EXTI_PR_PR18                        ((u32)0x00040000)        /* Trigger request occurred on the external interrupt line 18 */
02805
02806
02807
02808 /******************************************************************************/
02809 /*                                                                            */
02810 /*                             DMA Controller                                 */
02811 /*                                                                            */
02812 /******************************************************************************/
02813
02814 /*******************  Bit definition for DMA_ISR register  ********************/
02815 #define  DMA_ISR_GIF1                        ((u32)0x00000001)        /* Channel 1 Global interrupt flag */
02816 #define  DMA_ISR_TCIF1                       ((u32)0x00000002)        /* Channel 1 Transfer Complete flag */
02817 #define  DMA_ISR_HTIF1                       ((u32)0x00000004)        /* Channel 1 Half Transfer flag */
02818 #define  DMA_ISR_TEIF1                       ((u32)0x00000008)        /* Channel 1 Transfer Error flag */
02819 #define  DMA_ISR_GIF2                        ((u32)0x00000010)        /* Channel 2 Global interrupt flag */
02820 #define  DMA_ISR_TCIF2                       ((u32)0x00000020)        /* Channel 2 Transfer Complete flag */
02821 #define  DMA_ISR_HTIF2                       ((u32)0x00000040)        /* Channel 2 Half Transfer flag */
02822 #define  DMA_ISR_TEIF2                       ((u32)0x00000080)        /* Channel 2 Transfer Error flag */
02823 #define  DMA_ISR_GIF3                        ((u32)0x00000100)        /* Channel 3 Global interrupt flag */
02824 #define  DMA_ISR_TCIF3                       ((u32)0x00000200)        /* Channel 3 Transfer Complete flag */
02825 #define  DMA_ISR_HTIF3                       ((u32)0x00000400)        /* Channel 3 Half Transfer flag */
02826 #define  DMA_ISR_TEIF3                       ((u32)0x00000800)        /* Channel 3 Transfer Error flag */
02827 #define  DMA_ISR_GIF4                        ((u32)0x00001000)        /* Channel 4 Global interrupt flag */
02828 #define  DMA_ISR_TCIF4                       ((u32)0x00002000)        /* Channel 4 Transfer Complete flag */
02829 #define  DMA_ISR_HTIF4                       ((u32)0x00004000)        /* Channel 4 Half Transfer flag */
02830 #define  DMA_ISR_TEIF4                       ((u32)0x00008000)        /* Channel 4 Transfer Error flag */
02831 #define  DMA_ISR_GIF5                        ((u32)0x00010000)        /* Channel 5 Global interrupt flag */
02832 #define  DMA_ISR_TCIF5                       ((u32)0x00020000)        /* Channel 5 Transfer Complete flag */
02833 #define  DMA_ISR_HTIF5                       ((u32)0x00040000)        /* Channel 5 Half Transfer flag */
02834 #define  DMA_ISR_TEIF5                       ((u32)0x00080000)        /* Channel 5 Transfer Error flag */
02835 #define  DMA_ISR_GIF6                        ((u32)0x00100000)        /* Channel 6 Global interrupt flag */
02836 #define  DMA_ISR_TCIF6                       ((u32)0x00200000)        /* Channel 6 Transfer Complete flag */
02837 #define  DMA_ISR_HTIF6                       ((u32)0x00400000)        /* Channel 6 Half Transfer flag */
02838 #define  DMA_ISR_TEIF6                       ((u32)0x00800000)        /* Channel 6 Transfer Error flag */
02839 #define  DMA_ISR_GIF7                        ((u32)0x01000000)        /* Channel 7 Global interrupt flag */
02840 #define  DMA_ISR_TCIF7                       ((u32)0x02000000)        /* Channel 7 Transfer Complete flag */
02841 #define  DMA_ISR_HTIF7                       ((u32)0x04000000)        /* Channel 7 Half Transfer flag */
02842 #define  DMA_ISR_TEIF7                       ((u32)0x08000000)        /* Channel 7 Transfer Error flag */
02843
02844
02845 /*******************  Bit definition for DMA_IFCR register  *******************/
02846 #define  DMA_IFCR_CGIF1                      ((u32)0x00000001)        /* Channel 1 Global interrupt clearr */
02847 #define  DMA_IFCR_CTCIF1                     ((u32)0x00000002)        /* Channel 1 Transfer Complete clear */
02848 #define  DMA_IFCR_CHTIF1                     ((u32)0x00000004)        /* Channel 1 Half Transfer clear */
02849 #define  DMA_IFCR_CTEIF1                     ((u32)0x00000008)        /* Channel 1 Transfer Error clear */
02850 #define  DMA_IFCR_CGIF2                      ((u32)0x00000010)        /* Channel 2 Global interrupt clear */
02851 #define  DMA_IFCR_CTCIF2                     ((u32)0x00000020)        /* Channel 2 Transfer Complete clear */
02852 #define  DMA_IFCR_CHTIF2                     ((u32)0x00000040)        /* Channel 2 Half Transfer clear */
02853 #define  DMA_IFCR_CTEIF2                     ((u32)0x00000080)        /* Channel 2 Transfer Error clear */
02854 #define  DMA_IFCR_CGIF3                      ((u32)0x00000100)        /* Channel 3 Global interrupt clear */
02855 #define  DMA_IFCR_CTCIF3                     ((u32)0x00000200)        /* Channel 3 Transfer Complete clear */
02856 #define  DMA_IFCR_CHTIF3                     ((u32)0x00000400)        /* Channel 3 Half Transfer clear */
02857 #define  DMA_IFCR_CTEIF3                     ((u32)0x00000800)        /* Channel 3 Transfer Error clear */
02858 #define  DMA_IFCR_CGIF4                      ((u32)0x00001000)        /* Channel 4 Global interrupt clear */
02859 #define  DMA_IFCR_CTCIF4                     ((u32)0x00002000)        /* Channel 4 Transfer Complete clear */
02860 #define  DMA_IFCR_CHTIF4                     ((u32)0x00004000)        /* Channel 4 Half Transfer clear */
02861 #define  DMA_IFCR_CTEIF4                     ((u32)0x00008000)        /* Channel 4 Transfer Error clear */
02862 #define  DMA_IFCR_CGIF5                      ((u32)0x00010000)        /* Channel 5 Global interrupt clear */
02863 #define  DMA_IFCR_CTCIF5                     ((u32)0x00020000)        /* Channel 5 Transfer Complete clear */
02864 #define  DMA_IFCR_CHTIF5                     ((u32)0x00040000)        /* Channel 5 Half Transfer clear */
02865 #define  DMA_IFCR_CTEIF5                     ((u32)0x00080000)        /* Channel 5 Transfer Error clear */
02866 #define  DMA_IFCR_CGIF6                      ((u32)0x00100000)        /* Channel 6 Global interrupt clear */
02867 #define  DMA_IFCR_CTCIF6                     ((u32)0x00200000)        /* Channel 6 Transfer Complete clear */
02868 #define  DMA_IFCR_CHTIF6                     ((u32)0x00400000)        /* Channel 6 Half Transfer clear */
02869 #define  DMA_IFCR_CTEIF6                     ((u32)0x00800000)        /* Channel 6 Transfer Error clear */
02870 #define  DMA_IFCR_CGIF7                      ((u32)0x01000000)        /* Channel 7 Global interrupt clear */
02871 #define  DMA_IFCR_CTCIF7                     ((u32)0x02000000)        /* Channel 7 Transfer Complete clear */
02872 #define  DMA_IFCR_CHTIF7                     ((u32)0x04000000)        /* Channel 7 Half Transfer clear */
02873 #define  DMA_IFCR_CTEIF7                     ((u32)0x08000000)        /* Channel 7 Transfer Error clear */
02874
02875
02876 /*******************  Bit definition for DMA_CCR1 register  *******************/
02877 #define  DMA_CCR1_EN                         ((u16)0x0001)            /* Channel enable*/
02878 #define  DMA_CCR1_TCIE                       ((u16)0x0002)            /* Transfer complete interrupt enable */
02879 #define  DMA_CCR1_HTIE                       ((u16)0x0004)            /* Half Transfer interrupt enable */
02880 #define  DMA_CCR1_TEIE                       ((u16)0x0008)            /* Transfer error interrupt enable */
02881 #define  DMA_CCR1_DIR                        ((u16)0x0010)            /* Data transfer direction */
02882 #define  DMA_CCR1_CIRC                       ((u16)0x0020)            /* Circular mode */
02883 #define  DMA_CCR1_PINC                       ((u16)0x0040)            /* Peripheral increment mode */
02884 #define  DMA_CCR1_MINC                       ((u16)0x0080)            /* Memory increment mode */
02885
02886 #define  DMA_CCR1_PSIZE                      ((u16)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
02887 #define  DMA_CCR1_PSIZE_0                    ((u16)0x0100)            /* Bit 0 */
02888 #define  DMA_CCR1_PSIZE_1                    ((u16)0x0200)            /* Bit 1 */
02889
02890 #define  DMA_CCR1_MSIZE                      ((u16)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
02891 #define  DMA_CCR1_MSIZE_0                    ((u16)0x0400)            /* Bit 0 */
02892 #define  DMA_CCR1_MSIZE_1                    ((u16)0x0800)            /* Bit 1 */
02893
02894 #define  DMA_CCR1_PL                         ((u16)0x3000)            /* PL[1:0] bits(Channel Priority level) */
02895 #define  DMA_CCR1_PL_0                       ((u16)0x1000)            /* Bit 0 */
02896 #define  DMA_CCR1_PL_1                       ((u16)0x2000)            /* Bit 1 */
02897
02898 #define  DMA_CCR1_MEM2MEM                    ((u16)0x4000)            /* Memory to memory mode */
02899
02900
02901 /*******************  Bit definition for DMA_CCR2 register  *******************/
02902 #define  DMA_CCR2_EN                         ((u16)0x0001)            /* Channel enable */
02903 #define  DMA_CCR2_TCIE                       ((u16)0x0002)            /* ransfer complete interrupt enable */
02904 #define  DMA_CCR2_HTIE                       ((u16)0x0004)            /* Half Transfer interrupt enable */
02905 #define  DMA_CCR2_TEIE                       ((u16)0x0008)            /* Transfer error interrupt enable */
02906 #define  DMA_CCR2_DIR                        ((u16)0x0010)            /* Data transfer direction */
02907 #define  DMA_CCR2_CIRC                       ((u16)0x0020)            /* Circular mode */
02908 #define  DMA_CCR2_PINC                       ((u16)0x0040)            /* Peripheral increment mode */
02909 #define  DMA_CCR2_MINC                       ((u16)0x0080)            /* Memory increment mode */
02910
02911 #define  DMA_CCR2_PSIZE                      ((u16)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
02912 #define  DMA_CCR2_PSIZE_0                    ((u16)0x0100)            /* Bit 0 */
02913 #define  DMA_CCR2_PSIZE_1                    ((u16)0x0200)            /* Bit 1 */
02914
02915 #define  DMA_CCR2_MSIZE                      ((u16)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
02916 #define  DMA_CCR2_MSIZE_0                    ((u16)0x0400)            /* Bit 0 */
02917 #define  DMA_CCR2_MSIZE_1                    ((u16)0x0800)            /* Bit 1 */
02918
02919 #define  DMA_CCR2_PL                         ((u16)0x3000)            /* PL[1:0] bits (Channel Priority level) */
02920 #define  DMA_CCR2_PL_0                       ((u16)0x1000)            /* Bit 0 */
02921 #define  DMA_CCR2_PL_1                       ((u16)0x2000)            /* Bit 1 */
02922
02923 #define  DMA_CCR2_MEM2MEM                    ((u16)0x4000)            /* Memory to memory mode */
02924
02925
02926 /*******************  Bit definition for DMA_CCR3 register  *******************/
02927 #define  DMA_CCR3_EN                         ((u16)0x0001)            /* Channel enable */
02928 #define  DMA_CCR3_TCIE                       ((u16)0x0002)            /* Transfer complete interrupt enable */
02929 #define  DMA_CCR3_HTIE                       ((u16)0x0004)            /* Half Transfer interrupt enable */
02930 #define  DMA_CCR3_TEIE                       ((u16)0x0008)            /* Transfer error interrupt enable */
02931 #define  DMA_CCR3_DIR                        ((u16)0x0010)            /* Data transfer direction */
02932 #define  DMA_CCR3_CIRC                       ((u16)0x0020)            /* Circular mode */
02933 #define  DMA_CCR3_PINC                       ((u16)0x0040)            /* Peripheral increment mode */
02934 #define  DMA_CCR3_MINC                       ((u16)0x0080)            /* Memory increment mode */
02935
02936 #define  DMA_CCR3_PSIZE                      ((u16)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
02937 #define  DMA_CCR3_PSIZE_0                    ((u16)0x0100)            /* Bit 0 */
02938 #define  DMA_CCR3_PSIZE_1                    ((u16)0x0200)            /* Bit 1 */
02939
02940 #define  DMA_CCR3_MSIZE                      ((u16)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
02941 #define  DMA_CCR3_MSIZE_0                    ((u16)0x0400)            /* Bit 0 */
02942 #define  DMA_CCR3_MSIZE_1                    ((u16)0x0800)            /* Bit 1 */
02943
02944 #define  DMA_CCR3_PL                         ((u16)0x3000)            /* PL[1:0] bits (Channel Priority level) */
02945 #define  DMA_CCR3_PL_0                       ((u16)0x1000)            /* Bit 0 */
02946 #define  DMA_CCR3_PL_1                       ((u16)0x2000)            /* Bit 1 */
02947
02948 #define  DMA_CCR3_MEM2MEM                    ((u16)0x4000)            /* Memory to memory mode */
02949
02950
02951 /*******************  Bit definition for DMA_CCR4 register  *******************/
02952 #define  DMA_CCR4_EN                         ((u16)0x0001)            /* Channel enable */
02953 #define  DMA_CCR4_TCIE                       ((u16)0x0002)            /* Transfer complete interrupt enable */
02954 #define  DMA_CCR4_HTIE                       ((u16)0x0004)            /* Half Transfer interrupt enable */
02955 #define  DMA_CCR4_TEIE                       ((u16)0x0008)            /* Transfer error interrupt enable */
02956 #define  DMA_CCR4_DIR                        ((u16)0x0010)            /* Data transfer direction */
02957 #define  DMA_CCR4_CIRC                       ((u16)0x0020)            /* Circular mode */
02958 #define  DMA_CCR4_PINC                       ((u16)0x0040)            /* Peripheral increment mode */
02959 #define  DMA_CCR4_MINC                       ((u16)0x0080)            /* Memory increment mode */
02960
02961 #define  DMA_CCR4_PSIZE                      ((u16)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
02962 #define  DMA_CCR4_PSIZE_0                    ((u16)0x0100)            /* Bit 0 */
02963 #define  DMA_CCR4_PSIZE_1                    ((u16)0x0200)            /* Bit 1 */
02964
02965 #define  DMA_CCR4_MSIZE                      ((u16)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
02966 #define  DMA_CCR4_MSIZE_0                    ((u16)0x0400)            /* Bit 0 */
02967 #define  DMA_CCR4_MSIZE_1                    ((u16)0x0800)            /* Bit 1 */
02968
02969 #define  DMA_CCR4_PL                         ((u16)0x3000)            /* PL[1:0] bits (Channel Priority level) */
02970 #define  DMA_CCR4_PL_0                       ((u16)0x1000)            /* Bit 0 */
02971 #define  DMA_CCR4_PL_1                       ((u16)0x2000)            /* Bit 1 */
02972
02973 #define  DMA_CCR4_MEM2MEM                    ((u16)0x4000)            /* Memory to memory mode */
02974
02975
02976 /******************  Bit definition for DMA_CCR5 register  *******************/
02977 #define  DMA_CCR5_EN                         ((u16)0x0001)            /* Channel enable */
02978 #define  DMA_CCR5_TCIE                       ((u16)0x0002)            /* Transfer complete interrupt enable */
02979 #define  DMA_CCR5_HTIE                       ((u16)0x0004)            /* Half Transfer interrupt enable */
02980 #define  DMA_CCR5_TEIE                       ((u16)0x0008)            /* Transfer error interrupt enable */
02981 #define  DMA_CCR5_DIR                        ((u16)0x0010)            /* Data transfer direction */
02982 #define  DMA_CCR5_CIRC                       ((u16)0x0020)            /* Circular mode */
02983 #define  DMA_CCR5_PINC                       ((u16)0x0040)            /* Peripheral increment mode */
02984 #define  DMA_CCR5_MINC                       ((u16)0x0080)            /* Memory increment mode */
02985
02986 #define  DMA_CCR5_PSIZE                      ((u16)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
02987 #define  DMA_CCR5_PSIZE_0                    ((u16)0x0100)            /* Bit 0 */
02988 #define  DMA_CCR5_PSIZE_1                    ((u16)0x0200)            /* Bit 1 */
02989
02990 #define  DMA_CCR5_MSIZE                      ((u16)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
02991 #define  DMA_CCR5_MSIZE_0                    ((u16)0x0400)            /* Bit 0 */
02992 #define  DMA_CCR5_MSIZE_1                    ((u16)0x0800)            /* Bit 1 */
02993
02994 #define  DMA_CCR5_PL                         ((u16)0x3000)            /* PL[1:0] bits (Channel Priority level) */
02995 #define  DMA_CCR5_PL_0                       ((u16)0x1000)            /* Bit 0 */
02996 #define  DMA_CCR5_PL_1                       ((u16)0x2000)            /* Bit 1 */
02997
02998 #define  DMA_CCR5_MEM2MEM                    ((u16)0x4000)            /* Memory to memory mode enable */
02999
03000
03001 /*******************  Bit definition for DMA_CCR6 register  *******************/
03002 #define  DMA_CCR6_EN                         ((u16)0x0001)            /* Channel enable */
03003 #define  DMA_CCR6_TCIE                       ((u16)0x0002)            /* Transfer complete interrupt enable */
03004 #define  DMA_CCR6_HTIE                       ((u16)0x0004)            /* Half Transfer interrupt enable */
03005 #define  DMA_CCR6_TEIE                       ((u16)0x0008)            /* Transfer error interrupt enable */
03006 #define  DMA_CCR6_DIR                        ((u16)0x0010)            /* Data transfer direction */
03007 #define  DMA_CCR6_CIRC                       ((u16)0x0020)            /* Circular mode */
03008 #define  DMA_CCR6_PINC                       ((u16)0x0040)            /* Peripheral increment mode */
03009 #define  DMA_CCR6_MINC                       ((u16)0x0080)            /* Memory increment mode */
03010
03011 #define  DMA_CCR6_PSIZE                      ((u16)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
03012 #define  DMA_CCR6_PSIZE_0                    ((u16)0x0100)            /* Bit 0 */
03013 #define  DMA_CCR6_PSIZE_1                    ((u16)0x0200)            /* Bit 1 */
03014
03015 #define  DMA_CCR6_MSIZE                      ((u16)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
03016 #define  DMA_CCR6_MSIZE_0                    ((u16)0x0400)            /* Bit 0 */
03017 #define  DMA_CCR6_MSIZE_1                    ((u16)0x0800)            /* Bit 1 */
03018
03019 #define  DMA_CCR6_PL                         ((u16)0x3000)            /* PL[1:0] bits (Channel Priority level) */
03020 #define  DMA_CCR6_PL_0                       ((u16)0x1000)            /* Bit 0 */
03021 #define  DMA_CCR6_PL_1                       ((u16)0x2000)            /* Bit 1 */
03022
03023 #define  DMA_CCR6_MEM2MEM                    ((u16)0x4000)            /* Memory to memory mode */
03024
03025
03026 /*******************  Bit definition for DMA_CCR7 register  *******************/
03027 #define  DMA_CCR7_EN                         ((u16)0x0001)            /* Channel enable */
03028 #define  DMA_CCR7_TCIE                       ((u16)0x0002)            /* Transfer complete interrupt enable */
03029 #define  DMA_CCR7_HTIE                       ((u16)0x0004)            /* Half Transfer interrupt enable */
03030 #define  DMA_CCR7_TEIE                       ((u16)0x0008)            /* Transfer error interrupt enable */
03031 #define  DMA_CCR7_DIR                        ((u16)0x0010)            /* Data transfer direction */
03032 #define  DMA_CCR7_CIRC                       ((u16)0x0020)            /* Circular mode */
03033 #define  DMA_CCR7_PINC                       ((u16)0x0040)            /* Peripheral increment mode */
03034 #define  DMA_CCR7_MINC                       ((u16)0x0080)            /* Memory increment mode */
03035
03036 #define  DMA_CCR7_PSIZE            ,         ((u16)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
03037 #define  DMA_CCR7_PSIZE_0                    ((u16)0x0100)            /* Bit 0 */
03038 #define  DMA_CCR7_PSIZE_1                    ((u16)0x0200)            /* Bit 1 */
03039
03040 #define  DMA_CCR7_MSIZE                      ((u16)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
03041 #define  DMA_CCR7_MSIZE_0                    ((u16)0x0400)            /* Bit 0 */
03042 #define  DMA_CCR7_MSIZE_1                    ((u16)0x0800)            /* Bit 1 */
03043
03044 #define  DMA_CCR7_PL                         ((u16)0x3000)            /* PL[1:0] bits (Channel Priority level) */
03045 #define  DMA_CCR7_PL_0                       ((u16)0x1000)            /* Bit 0 */
03046 #define  DMA_CCR7_PL_1                       ((u16)0x2000)            /* Bit 1 */
03047
03048 #define  DMA_CCR7_MEM2MEM                    ((u16)0x4000)            /* Memory to memory mode enable */
03049
03050
03051 /******************  Bit definition for DMA_CNDTR1 register  ******************/
03052 #define  DMA_CNDTR1_NDT                      ((u16)0xFFFF)            /* Number of data to Transfer */
03053
03054
03055 /******************  Bit definition for DMA_CNDTR2 register  ******************/
03056 #define  DMA_CNDTR2_NDT                      ((u16)0xFFFF)            /* Number of data to Transfer */
03057
03058
03059 /******************  Bit definition for DMA_CNDTR3 register  ******************/
03060 #define  DMA_CNDTR3_NDT                      ((u16)0xFFFF)            /* Number of data to Transfer */
03061
03062
03063 /******************  Bit definition for DMA_CNDTR4 register  ******************/
03064 #define  DMA_CNDTR4_NDT                      ((u16)0xFFFF)            /* Number of data to Transfer */
03065
03066
03067 /******************  Bit definition for DMA_CNDTR5 register  ******************/
03068 #define  DMA_CNDTR5_NDT                      ((u16)0xFFFF)            /* Number of data to Transfer */
03069
03070
03071 /******************  Bit definition for DMA_CNDTR6 register  ******************/
03072 #define  DMA_CNDTR6_NDT                      ((u16)0xFFFF)            /* Number of data to Transfer */
03073
03074
03075 /******************  Bit definition for DMA_CNDTR7 register  ******************/
03076 #define  DMA_CNDTR7_NDT                      ((u16)0xFFFF)            /* Number of data to Transfer */
03077
03078
03079 /******************  Bit definition for DMA_CPAR1 register  *******************/
03080 #define  DMA_CPAR1_PA                        ((u32)0xFFFFFFFF)        /* Peripheral Address */
03081
03082
03083 /******************  Bit definition for DMA_CPAR2 register  *******************/
03084 #define  DMA_CPAR2_PA                        ((u32)0xFFFFFFFF)        /* Peripheral Address */
03085
03086
03087 /******************  Bit definition for DMA_CPAR3 register  *******************/
03088 #define  DMA_CPAR3_PA                        ((u32)0xFFFFFFFF)        /* Peripheral Address */
03089
03090
03091 /******************  Bit definition for DMA_CPAR4 register  *******************/
03092 #define  DMA_CPAR4_PA                        ((u32)0xFFFFFFFF)        /* Peripheral Address */
03093
03094
03095 /******************  Bit definition for DMA_CPAR5 register  *******************/
03096 #define  DMA_CPAR5_PA                        ((u32)0xFFFFFFFF)        /* Peripheral Address */
03097
03098
03099 /******************  Bit definition for DMA_CPAR6 register  *******************/
03100 #define  DMA_CPAR6_PA                        ((u32)0xFFFFFFFF)        /* Peripheral Address */
03101
03102
03103 /******************  Bit definition for DMA_CPAR7 register  *******************/
03104 #define  DMA_CPAR7_PA                        ((u32)0xFFFFFFFF)        /* Peripheral Address */
03105
03106
03107 /******************  Bit definition for DMA_CMAR1 register  *******************/
03108 #define  DMA_CMAR1_MA                        ((u32)0xFFFFFFFF)        /* Memory Address */
03109
03110
03111 /******************  Bit definition for DMA_CMAR2 register  *******************/
03112 #define  DMA_CMAR2_MA                        ((u32)0xFFFFFFFF)        /* Memory Address */
03113
03114
03115 /******************  Bit definition for DMA_CMAR3 register  *******************/
03116 #define  DMA_CMAR3_MA                        ((u32)0xFFFFFFFF)        /* Memory Address */
03117
03118
03119 /******************  Bit definition for DMA_CMAR4 register  *******************/
03120 #define  DMA_CMAR4_MA                        ((u32)0xFFFFFFFF)        /* Memory Address */
03121
03122
03123 /******************  Bit definition for DMA_CMAR5 register  *******************/
03124 #define  DMA_CMAR5_MA                        ((u32)0xFFFFFFFF)        /* Memory Address */
03125
03126
03127 /******************  Bit definition for DMA_CMAR6 register  *******************/
03128 #define  DMA_CMAR6_MA                        ((u32)0xFFFFFFFF)        /* Memory Address */
03129
03130
03131 /******************  Bit definition for DMA_CMAR7 register  *******************/
03132 #define  DMA_CMAR7_MA                        ((u32)0xFFFFFFFF)        /* Memory Address */
03133
03134
03135
03136 /******************************************************************************/
03137 /*                                                                            */
03138 /*                        Analog to Digital Converter                         */
03139 /*                                                                            */
03140 /******************************************************************************/
03141
03142 /********************  Bit definition for ADC_SR register  ********************/
03143 #define  ADC_SR_AWD                          ((u8)0x01)               /* Analog watchdog flag */
03144 #define  ADC_SR_EOC                          ((u8)0x02)               /* End of conversion */
03145 #define  ADC_SR_JEOC                         ((u8)0x04)               /* Injected channel end of conversion */
03146 #define  ADC_SR_JSTRT                        ((u8)0x08)               /* Injected channel Start flag */
03147 #define  ADC_SR_STRT                         ((u8)0x10)               /* Regular channel Start flag */
03148
03149
03150 /*******************  Bit definition for ADC_CR1 register  ********************/
03151 #define  ADC_CR1_AWDCH                       ((u32)0x0000001F)        /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
03152 #define  ADC_CR1_AWDCH_0                     ((u32)0x00000001)        /* Bit 0 */
03153 #define  ADC_CR1_AWDCH_1                     ((u32)0x00000002)        /* Bit 1 */
03154 #define  ADC_CR1_AWDCH_2                     ((u32)0x00000004)        /* Bit 2 */
03155 #define  ADC_CR1_AWDCH_3                     ((u32)0x00000008)        /* Bit 3 */
03156 #define  ADC_CR1_AWDCH_4                     ((u32)0x00000010)        /* Bit 4 */
03157
03158 #define  ADC_CR1_EOCIE                       ((u32)0x00000020)        /* Interrupt enable for EOC */
03159 #define  ADC_CR1_AWDIE                       ((u32)0x00000040)        /* AAnalog Watchdog interrupt enable */
03160 #define  ADC_CR1_JEOCIE                      ((u32)0x00000080)        /* Interrupt enable for injected channels */
03161 #define  ADC_CR1_SCAN                        ((u32)0x00000100)        /* Scan mode */
03162 #define  ADC_CR1_AWDSGL                      ((u32)0x00000200)        /* Enable the watchdog on a single channel in scan mode */
03163 #define  ADC_CR1_JAUTO                       ((u32)0x00000400)        /* Automatic injected group conversion */
03164 #define  ADC_CR1_DISCEN                      ((u32)0x00000800)        /* Discontinuous mode on regular channels */
03165 #define  ADC_CR1_JDISCEN                     ((u32)0x00001000)        /* Discontinuous mode on injected channels */
03166
03167 #define  ADC_CR1_DISCNUM                     ((u32)0x0000E000)        /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
03168 #define  ADC_CR1_DISCNUM_0                   ((u32)0x00002000)        /* Bit 0 */
03169 #define  ADC_CR1_DISCNUM_1                   ((u32)0x00004000)        /* Bit 1 */
03170 #define  ADC_CR1_DISCNUM_2                   ((u32)0x00008000)        /* Bit 2 */
03171
03172 #define  ADC_CR1_DUALMOD                     ((u32)0x000F0000)        /* DUALMOD[3:0] bits (Dual mode selection) */
03173 #define  ADC_CR1_DUALMOD_0                   ((u32)0x00010000)        /* Bit 0 */
03174 #define  ADC_CR1_DUALMOD_1                   ((u32)0x00020000)        /* Bit 1 */
03175 #define  ADC_CR1_DUALMOD_2                   ((u32)0x00040000)        /* Bit 2 */
03176 #define  ADC_CR1_DUALMOD_3                   ((u32)0x00080000)        /* Bit 3 */
03177
03178 #define  ADC_CR1_JAWDEN                      ((u32)0x00400000)        /* Analog watchdog enable on injected channels */
03179 #define  ADC_CR1_AWDEN                       ((u32)0x00800000)        /* Analog watchdog enable on regular channels */
03180
03181
03182 /*******************  Bit definition for ADC_CR2 register  ********************/
03183 #define  ADC_CR2_ADON                        ((u32)0x00000001)        /* A/D Converter ON / OFF */
03184 #define  ADC_CR2_CONT                        ((u32)0x00000002)        /* Continuous Conversion */
03185 #define  ADC_CR2_CAL                         ((u32)0x00000004)        /* A/D Calibration */
03186 #define  ADC_CR2_RSTCAL                      ((u32)0x00000008)        /* Reset Calibration */
03187 #define  ADC_CR2_DMA                         ((u32)0x00000100)        /* Direct Memory access mode */
03188 #define  ADC_CR2_ALIGN                       ((u32)0x00000800)        /* Data Alignment */
03189
03190 #define  ADC_CR2_JEXTSEL                     ((u32)0x00007000)        /* JEXTSEL[2:0] bits (External event select for injected group) */
03191 #define  ADC_CR2_JEXTSEL_0                   ((u32)0x00001000)        /* Bit 0 */
03192 #define  ADC_CR2_JEXTSEL_1                   ((u32)0x00002000)        /* Bit 1 */
03193 #define  ADC_CR2_JEXTSEL_2                   ((u32)0x00004000)        /* Bit 2 */
03194
03195 #define  ADC_CR2_JEXTTRIG                    ((u32)0x00008000)        /* External Trigger Conversion mode for injected channels */
03196
03197 #define  ADC_CR2_EXTSEL                      ((u32)0x000E0000)        /* EXTSEL[2:0] bits (External Event Select for regular group) */
03198 #define  ADC_CR2_EXTSEL_0                    ((u32)0x00020000)        /* Bit 0 */
03199 #define  ADC_CR2_EXTSEL_1                    ((u32)0x00040000)        /* Bit 1 */
03200 #define  ADC_CR2_EXTSEL_2                    ((u32)0x00080000)        /* Bit 2 */
03201
03202 #define  ADC_CR2_EXTTRIG                     ((u32)0x00100000)        /* External Trigger Conversion mode for regular channels */
03203 #define  ADC_CR2_JSWSTART                    ((u32)0x00200000)        /* Start Conversion of injected channels */
03204 #define  ADC_CR2_SWSTART                     ((u32)0x00400000)        /* Start Conversion of regular channels */
03205 #define  ADC_CR2_TSVREFE                     ((u32)0x00800000)        /* Temperature Sensor and VREFINT Enable */
03206
03207
03208 /******************  Bit definition for ADC_SMPR1 register  *******************/
03209 #define  ADC_SMPR1_SMP10                     ((u32)0x00000007)        /* SMP10[2:0] bits (Channel 10 Sample time selection) */
03210 #define  ADC_SMPR1_SMP10_0                   ((u32)0x00000001)        /* Bit 0 */
03211 #define  ADC_SMPR1_SMP10_1                   ((u32)0x00000002)        /* Bit 1 */
03212 #define  ADC_SMPR1_SMP10_2                   ((u32)0x00000004)        /* Bit 2 */
03213
03214 #define  ADC_SMPR1_SMP11                     ((u32)0x00000038)        /* SMP11[2:0] bits (Channel 11 Sample time selection) */
03215 #define  ADC_SMPR1_SMP11_0                   ((u32)0x00000008)        /* Bit 0 */
03216 #define  ADC_SMPR1_SMP11_1                   ((u32)0x00000010)        /* Bit 1 */
03217 #define  ADC_SMPR1_SMP11_2                   ((u32)0x00000020)        /* Bit 2 */
03218
03219 #define  ADC_SMPR1_SMP12                     ((u32)0x000001C0)        /* SMP12[2:0] bits (Channel 12 Sample time selection) */
03220 #define  ADC_SMPR1_SMP12_0                   ((u32)0x00000040)        /* Bit 0 */
03221 #define  ADC_SMPR1_SMP12_1                   ((u32)0x00000080)        /* Bit 1 */
03222 #define  ADC_SMPR1_SMP12_2                   ((u32)0x00000100)        /* Bit 2 */
03223
03224 #define  ADC_SMPR1_SMP13                     ((u32)0x00000E00)        /* SMP13[2:0] bits (Channel 13 Sample time selection) */
03225 #define  ADC_SMPR1_SMP13_0                   ((u32)0x00000200)        /* Bit 0 */
03226 #define  ADC_SMPR1_SMP13_1                   ((u32)0x00000400)        /* Bit 1 */
03227 #define  ADC_SMPR1_SMP13_2                   ((u32)0x00000800)        /* Bit 2 */
03228
03229 #define  ADC_SMPR1_SMP14                     ((u32)0x00007000)        /* SMP14[2:0] bits (Channel 14 Sample time selection) */
03230 #define  ADC_SMPR1_SMP14_0                   ((u32)0x00001000)        /* Bit 0 */
03231 #define  ADC_SMPR1_SMP14_1                   ((u32)0x00002000)        /* Bit 1 */
03232 #define  ADC_SMPR1_SMP14_2                   ((u32)0x00004000)        /* Bit 2 */
03233
03234 #define  ADC_SMPR1_SMP15                     ((u32)0x00038000)        /* SMP15[2:0] bits (Channel 15 Sample time selection) */
03235 #define  ADC_SMPR1_SMP15_0                   ((u32)0x00008000)        /* Bit 0 */
03236 #define  ADC_SMPR1_SMP15_1                   ((u32)0x00010000)        /* Bit 1 */
03237 #define  ADC_SMPR1_SMP15_2                   ((u32)0x00020000)        /* Bit 2 */
03238
03239 #define  ADC_SMPR1_SMP16                     ((u32)0x001C0000)        /* SMP16[2:0] bits (Channel 16 Sample time selection) */
03240 #define  ADC_SMPR1_SMP16_0                   ((u32)0x00040000)        /* Bit 0 */
03241 #define  ADC_SMPR1_SMP16_1                   ((u32)0x00080000)        /* Bit 1 */
03242 #define  ADC_SMPR1_SMP16_2                   ((u32)0x00100000)        /* Bit 2 */
03243
03244 #define  ADC_SMPR1_SMP17                     ((u32)0x00E00000)        /* SMP17[2:0] bits (Channel 17 Sample time selection) */
03245 #define  ADC_SMPR1_SMP17_0                   ((u32)0x00200000)        /* Bit 0 */
03246 #define  ADC_SMPR1_SMP17_1                   ((u32)0x00400000)        /* Bit 1 */
03247 #define  ADC_SMPR1_SMP17_2                   ((u32)0x00800000)        /* Bit 2 */
03248
03249
03250 /******************  Bit definition for ADC_SMPR2 register  *******************/
03251 #define  ADC_SMPR2_SMP0                      ((u32)0x00000007)        /* SMP0[2:0] bits (Channel 0 Sample time selection) */
03252 #define  ADC_SMPR2_SMP0_0                    ((u32)0x00000001)        /* Bit 0 */
03253 #define  ADC_SMPR2_SMP0_1                    ((u32)0x00000002)        /* Bit 1 */
03254 #define  ADC_SMPR2_SMP0_2                    ((u32)0x00000004)        /* Bit 2 */
03255
03256 #define  ADC_SMPR2_SMP1                      ((u32)0x00000038)        /* SMP1[2:0] bits (Channel 1 Sample time selection) */
03257 #define  ADC_SMPR2_SMP1_0                    ((u32)0x00000008)        /* Bit 0 */
03258 #define  ADC_SMPR2_SMP1_1                    ((u32)0x00000010)        /* Bit 1 */
03259 #define  ADC_SMPR2_SMP1_2                    ((u32)0x00000020)        /* Bit 2 */
03260
03261 #define  ADC_SMPR2_SMP2                      ((u32)0x000001C0)        /* SMP2[2:0] bits (Channel 2 Sample time selection) */
03262 #define  ADC_SMPR2_SMP2_0                    ((u32)0x00000040)        /* Bit 0 */
03263 #define  ADC_SMPR2_SMP2_1                    ((u32)0x00000080)        /* Bit 1 */
03264 #define  ADC_SMPR2_SMP2_2                    ((u32)0x00000100)        /* Bit 2 */
03265
03266 #define  ADC_SMPR2_SMP3                      ((u32)0x00000E00)        /* SMP3[2:0] bits (Channel 3 Sample time selection) */
03267 #define  ADC_SMPR2_SMP3_0                    ((u32)0x00000200)        /* Bit 0 */
03268 #define  ADC_SMPR2_SMP3_1                    ((u32)0x00000400)        /* Bit 1 */
03269 #define  ADC_SMPR2_SMP3_2                    ((u32)0x00000800)        /* Bit 2 */
03270
03271 #define  ADC_SMPR2_SMP4                      ((u32)0x00007000)        /* SMP4[2:0] bits (Channel 4 Sample time selection) */
03272 #define  ADC_SMPR2_SMP4_0                    ((u32)0x00001000)        /* Bit 0 */
03273 #define  ADC_SMPR2_SMP4_1                    ((u32)0x00002000)        /* Bit 1 */
03274 #define  ADC_SMPR2_SMP4_2                    ((u32)0x00004000)        /* Bit 2 */
03275
03276 #define  ADC_SMPR2_SMP5                      ((u32)0x00038000)        /* SMP5[2:0] bits (Channel 5 Sample time selection) */
03277 #define  ADC_SMPR2_SMP5_0                    ((u32)0x00008000)        /* Bit 0 */
03278 #define  ADC_SMPR2_SMP5_1                    ((u32)0x00010000)        /* Bit 1 */
03279 #define  ADC_SMPR2_SMP5_2                    ((u32)0x00020000)        /* Bit 2 */
03280
03281 #define  ADC_SMPR2_SMP6                      ((u32)0x001C0000)        /* SMP6[2:0] bits (Channel 6 Sample time selection) */
03282 #define  ADC_SMPR2_SMP6_0                    ((u32)0x00040000)        /* Bit 0 */
03283 #define  ADC_SMPR2_SMP6_1                    ((u32)0x00080000)        /* Bit 1 */
03284 #define  ADC_SMPR2_SMP6_2                    ((u32)0x00100000)        /* Bit 2 */
03285
03286 #define  ADC_SMPR2_SMP7                      ((u32)0x00E00000)        /* SMP7[2:0] bits (Channel 7 Sample time selection) */
03287 #define  ADC_SMPR2_SMP7_0                    ((u32)0x00200000)        /* Bit 0 */
03288 #define  ADC_SMPR2_SMP7_1                    ((u32)0x00400000)        /* Bit 1 */
03289 #define  ADC_SMPR2_SMP7_2                    ((u32)0x00800000)        /* Bit 2 */
03290
03291 #define  ADC_SMPR2_SMP8                      ((u32)0x07000000)        /* SMP8[2:0] bits (Channel 8 Sample time selection) */
03292 #define  ADC_SMPR2_SMP8_0                    ((u32)0x01000000)        /* Bit 0 */
03293 #define  ADC_SMPR2_SMP8_1                    ((u32)0x02000000)        /* Bit 1 */
03294 #define  ADC_SMPR2_SMP8_2                    ((u32)0x04000000)        /* Bit 2 */
03295
03296 #define  ADC_SMPR2_SMP9                      ((u32)0x38000000)        /* SMP9[2:0] bits (Channel 9 Sample time selection) */
03297 #define  ADC_SMPR2_SMP9_0                    ((u32)0x08000000)        /* Bit 0 */
03298 #define  ADC_SMPR2_SMP9_1                    ((u32)0x10000000)        /* Bit 1 */
03299 #define  ADC_SMPR2_SMP9_2                    ((u32)0x20000000)        /* Bit 2 */
03300
03301
03302 /******************  Bit definition for ADC_JOFR1 register  *******************/
03303 #define  ADC_JOFR1_JOFFSET1                  ((u16)0x0FFF)            /* Data offset for injected channel 1 */
03304
03305
03306 /******************  Bit definition for ADC_JOFR2 register  *******************/
03307 #define  ADC_JOFR2_JOFFSET2                  ((u16)0x0FFF)            /* Data offset for injected channel 2 */
03308
03309
03310 /******************  Bit definition for ADC_JOFR3 register  *******************/
03311 #define  ADC_JOFR3_JOFFSET3                  ((u16)0x0FFF)            /* Data offset for injected channel 3 */
03312
03313
03314 /******************  Bit definition for ADC_JOFR4 register  *******************/
03315 #define  ADC_JOFR4_JOFFSET4                  ((u16)0x0FFF)            /* Data offset for injected channel 4 */
03316
03317
03318 /*******************  Bit definition for ADC_HTR register  ********************/
03319 #define  ADC_HTR_HT                          ((u16)0x0FFF)            /* Analog watchdog high threshold */
03320
03321
03322 /*******************  Bit definition for ADC_LTR register  ********************/
03323 #define  ADC_LTR_LT                          ((u16)0x0FFF)            /* Analog watchdog low threshold */
03324
03325
03326 /*******************  Bit definition for ADC_SQR1 register  *******************/
03327 #define  ADC_SQR1_SQ13                       ((u32)0x0000001F)        /* SQ13[4:0] bits (13th conversion in regular sequence) */
03328 #define  ADC_SQR1_SQ13_0                     ((u32)0x00000001)        /* Bit 0 */
03329 #define  ADC_SQR1_SQ13_1                     ((u32)0x00000002)        /* Bit 1 */
03330 #define  ADC_SQR1_SQ13_2                     ((u32)0x00000004)        /* Bit 2 */
03331 #define  ADC_SQR1_SQ13_3                     ((u32)0x00000008)        /* Bit 3 */
03332 #define  ADC_SQR1_SQ13_4                     ((u32)0x00000010)        /* Bit 4 */
03333
03334 #define  ADC_SQR1_SQ14                       ((u32)0x000003E0)        /* SQ14[4:0] bits (14th conversion in regular sequence) */
03335 #define  ADC_SQR1_SQ14_0                     ((u32)0x00000020)        /* Bit 0 */
03336 #define  ADC_SQR1_SQ14_1                     ((u32)0x00000040)        /* Bit 1 */
03337 #define  ADC_SQR1_SQ14_2                     ((u32)0x00000080)        /* Bit 2 */
03338 #define  ADC_SQR1_SQ14_3                     ((u32)0x00000100)        /* Bit 3 */
03339 #define  ADC_SQR1_SQ14_4                     ((u32)0x00000200)        /* Bit 4 */
03340
03341 #define  ADC_SQR1_SQ15                       ((u32)0x00007C00)        /* SQ15[4:0] bits (15th conversion in regular sequence) */
03342 #define  ADC_SQR1_SQ15_0                     ((u32)0x00000400)        /* Bit 0 */
03343 #define  ADC_SQR1_SQ15_1                     ((u32)0x00000800)        /* Bit 1 */
03344 #define  ADC_SQR1_SQ15_2                     ((u32)0x00001000)        /* Bit 2 */
03345 #define  ADC_SQR1_SQ15_3                     ((u32)0x00002000)        /* Bit 3 */
03346 #define  ADC_SQR1_SQ15_4                     ((u32)0x00004000)        /* Bit 4 */
03347
03348 #define  ADC_SQR1_SQ16                       ((u32)0x000F8000)        /* SQ16[4:0] bits (16th conversion in regular sequence) */
03349 #define  ADC_SQR1_SQ16_0                     ((u32)0x00008000)        /* Bit 0 */
03350 #define  ADC_SQR1_SQ16_1                     ((u32)0x00010000)        /* Bit 1 */
03351 #define  ADC_SQR1_SQ16_2                     ((u32)0x00020000)        /* Bit 2 */
03352 #define  ADC_SQR1_SQ16_3                     ((u32)0x00040000)        /* Bit 3 */
03353 #define  ADC_SQR1_SQ16_4                     ((u32)0x00080000)        /* Bit 4 */
03354
03355 #define  ADC_SQR1_L                          ((u32)0x00F00000)        /* L[3:0] bits (Regular channel sequence length) */
03356 #define  ADC_SQR1_L_0                        ((u32)0x00100000)        /* Bit 0 */
03357 #define  ADC_SQR1_L_1                        ((u32)0x00200000)        /* Bit 1 */
03358 #define  ADC_SQR1_L_2                        ((u32)0x00400000)        /* Bit 2 */
03359 #define  ADC_SQR1_L_3                        ((u32)0x00800000)        /* Bit 3 */
03360
03361
03362 /*******************  Bit definition for ADC_SQR2 register  *******************/
03363 #define  ADC_SQR2_SQ7                        ((u32)0x0000001F)        /* SQ7[4:0] bits (7th conversion in regular sequence) */
03364 #define  ADC_SQR2_SQ7_0                      ((u32)0x00000001)        /* Bit 0 */
03365 #define  ADC_SQR2_SQ7_1                      ((u32)0x00000002)        /* Bit 1 */
03366 #define  ADC_SQR2_SQ7_2                      ((u32)0x00000004)        /* Bit 2 */
03367 #define  ADC_SQR2_SQ7_3                      ((u32)0x00000008)        /* Bit 3 */
03368 #define  ADC_SQR2_SQ7_4                      ((u32)0x00000010)        /* Bit 4 */
03369
03370 #define  ADC_SQR2_SQ8                        ((u32)0x000003E0)        /* SQ8[4:0] bits (8th conversion in regular sequence) */
03371 #define  ADC_SQR2_SQ8_0                      ((u32)0x00000020)        /* Bit 0 */
03372 #define  ADC_SQR2_SQ8_1                      ((u32)0x00000040)        /* Bit 1 */
03373 #define  ADC_SQR2_SQ8_2                      ((u32)0x00000080)        /* Bit 2 */
03374 #define  ADC_SQR2_SQ8_3                      ((u32)0x00000100)        /* Bit 3 */
03375 #define  ADC_SQR2_SQ8_4                      ((u32)0x00000200)        /* Bit 4 */
03376
03377 #define  ADC_SQR2_SQ9                        ((u32)0x00007C00)        /* SQ9[4:0] bits (9th conversion in regular sequence) */
03378 #define  ADC_SQR2_SQ9_0                      ((u32)0x00000400)        /* Bit 0 */
03379 #define  ADC_SQR2_SQ9_1                      ((u32)0x00000800)        /* Bit 1 */
03380 #define  ADC_SQR2_SQ9_2                      ((u32)0x00001000)        /* Bit 2 */
03381 #define  ADC_SQR2_SQ9_3                      ((u32)0x00002000)        /* Bit 3 */
03382 #define  ADC_SQR2_SQ9_4                      ((u32)0x00004000)        /* Bit 4 */
03383
03384 #define  ADC_SQR2_SQ10                       ((u32)0x000F8000)        /* SQ10[4:0] bits (10th conversion in regular sequence) */
03385 #define  ADC_SQR2_SQ10_0                     ((u32)0x00008000)        /* Bit 0 */
03386 #define  ADC_SQR2_SQ10_1                     ((u32)0x00010000)        /* Bit 1 */
03387 #define  ADC_SQR2_SQ10_2                     ((u32)0x00020000)        /* Bit 2 */
03388 #define  ADC_SQR2_SQ10_3                     ((u32)0x00040000)        /* Bit 3 */
03389 #define  ADC_SQR2_SQ10_4                     ((u32)0x00080000)        /* Bit 4 */
03390
03391 #define  ADC_SQR2_SQ11                       ((u32)0x01F00000)        /* SQ11[4:0] bits (11th conversion in regular sequence) */
03392 #define  ADC_SQR2_SQ11_0                     ((u32)0x00100000)        /* Bit 0 */
03393 #define  ADC_SQR2_SQ11_1                     ((u32)0x00200000)        /* Bit 1 */
03394 #define  ADC_SQR2_SQ11_2                     ((u32)0x00400000)        /* Bit 2 */
03395 #define  ADC_SQR2_SQ11_3                     ((u32)0x00800000)        /* Bit 3 */
03396 #define  ADC_SQR2_SQ11_4                     ((u32)0x01000000)        /* Bit 4 */
03397
03398 #define  ADC_SQR2_SQ12                       ((u32)0x3E000000)        /* SQ12[4:0] bits (12th conversion in regular sequence) */
03399 #define  ADC_SQR2_SQ12_0                     ((u32)0x02000000)        /* Bit 0 */
03400 #define  ADC_SQR2_SQ12_1                     ((u32)0x04000000)        /* Bit 1 */
03401 #define  ADC_SQR2_SQ12_2                     ((u32)0x08000000)        /* Bit 2 */
03402 #define  ADC_SQR2_SQ12_3                     ((u32)0x10000000)        /* Bit 3 */
03403 #define  ADC_SQR2_SQ12_4                     ((u32)0x20000000)        /* Bit 4 */
03404
03405
03406 /*******************  Bit definition for ADC_SQR3 register  *******************/
03407 #define  ADC_SQR3_SQ1                        ((u32)0x0000001F)        /* SQ1[4:0] bits (1st conversion in regular sequence) */
03408 #define  ADC_SQR3_SQ1_0                      ((u32)0x00000001)        /* Bit 0 */
03409 #define  ADC_SQR3_SQ1_1                      ((u32)0x00000002)        /* Bit 1 */
03410 #define  ADC_SQR3_SQ1_2                      ((u32)0x00000004)        /* Bit 2 */
03411 #define  ADC_SQR3_SQ1_3                      ((u32)0x00000008)        /* Bit 3 */
03412 #define  ADC_SQR3_SQ1_4                      ((u32)0x00000010)        /* Bit 4 */
03413
03414 #define  ADC_SQR3_SQ2                        ((u32)0x000003E0)        /* SQ2[4:0] bits (2nd conversion in regular sequence) */
03415 #define  ADC_SQR3_SQ2_0                      ((u32)0x00000020)        /* Bit 0 */
03416 #define  ADC_SQR3_SQ2_1                      ((u32)0x00000040)        /* Bit 1 */
03417 #define  ADC_SQR3_SQ2_2                      ((u32)0x00000080)        /* Bit 2 */
03418 #define  ADC_SQR3_SQ2_3                      ((u32)0x00000100)        /* Bit 3 */
03419 #define  ADC_SQR3_SQ2_4                      ((u32)0x00000200)        /* Bit 4 */
03420
03421 #define  ADC_SQR3_SQ3                        ((u32)0x00007C00)        /* SQ3[4:0] bits (3rd conversion in regular sequence) */
03422 #define  ADC_SQR3_SQ3_0                      ((u32)0x00000400)        /* Bit 0 */
03423 #define  ADC_SQR3_SQ3_1                      ((u32)0x00000800)        /* Bit 1 */
03424 #define  ADC_SQR3_SQ3_2                      ((u32)0x00001000)        /* Bit 2 */
03425 #define  ADC_SQR3_SQ3_3                      ((u32)0x00002000)        /* Bit 3 */
03426 #define  ADC_SQR3_SQ3_4                      ((u32)0x00004000)        /* Bit 4 */
03427
03428 #define  ADC_SQR3_SQ4                        ((u32)0x000F8000)        /* SQ4[4:0] bits (4th conversion in regular sequence) */
03429 #define  ADC_SQR3_SQ4_0                      ((u32)0x00008000)        /* Bit 0 */
03430 #define  ADC_SQR3_SQ4_1                      ((u32)0x00010000)        /* Bit 1 */
03431 #define  ADC_SQR3_SQ4_2                      ((u32)0x00020000)        /* Bit 2 */
03432 #define  ADC_SQR3_SQ4_3                      ((u32)0x00040000)        /* Bit 3 */
03433 #define  ADC_SQR3_SQ4_4                      ((u32)0x00080000)        /* Bit 4 */
03434
03435 #define  ADC_SQR3_SQ5                        ((u32)0x01F00000)        /* SQ5[4:0] bits (5th conversion in regular sequence) */
03436 #define  ADC_SQR3_SQ5_0                      ((u32)0x00100000)        /* Bit 0 */
03437 #define  ADC_SQR3_SQ5_1                      ((u32)0x00200000)        /* Bit 1 */
03438 #define  ADC_SQR3_SQ5_2                      ((u32)0x00400000)        /* Bit 2 */
03439 #define  ADC_SQR3_SQ5_3                      ((u32)0x00800000)        /* Bit 3 */
03440 #define  ADC_SQR3_SQ5_4                      ((u32)0x01000000)        /* Bit 4 */
03441
03442 #define  ADC_SQR3_SQ6                        ((u32)0x3E000000)        /* SQ6[4:0] bits (6th conversion in regular sequence) */
03443 #define  ADC_SQR3_SQ6_0                      ((u32)0x02000000)        /* Bit 0 */
03444 #define  ADC_SQR3_SQ6_1                      ((u32)0x04000000)        /* Bit 1 */
03445 #define  ADC_SQR3_SQ6_2                      ((u32)0x08000000)        /* Bit 2 */
03446 #define  ADC_SQR3_SQ6_3                      ((u32)0x10000000)        /* Bit 3 */
03447 #define  ADC_SQR3_SQ6_4                      ((u32)0x20000000)        /* Bit 4 */
03448
03449
03450 /*******************  Bit definition for ADC_JSQR register  *******************/
03451 #define  ADC_JSQR_JSQ1                       ((u32)0x0000001F)        /* JSQ1[4:0] bits (1st conversion in injected sequence) */
03452 #define  ADC_JSQR_JSQ1_0                     ((u32)0x00000001)        /* Bit 0 */
03453 #define  ADC_JSQR_JSQ1_1                     ((u32)0x00000002)        /* Bit 1 */
03454 #define  ADC_JSQR_JSQ1_2                     ((u32)0x00000004)        /* Bit 2 */
03455 #define  ADC_JSQR_JSQ1_3                     ((u32)0x00000008)        /* Bit 3 */
03456 #define  ADC_JSQR_JSQ1_4                     ((u32)0x00000010)        /* Bit 4 */
03457
03458 #define  ADC_JSQR_JSQ2                       ((u32)0x000003E0)        /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
03459 #define  ADC_JSQR_JSQ2_0                     ((u32)0x00000020)        /* Bit 0 */
03460 #define  ADC_JSQR_JSQ2_1                     ((u32)0x00000040)        /* Bit 1 */
03461 #define  ADC_JSQR_JSQ2_2                     ((u32)0x00000080)        /* Bit 2 */
03462 #define  ADC_JSQR_JSQ2_3                     ((u32)0x00000100)        /* Bit 3 */
03463 #define  ADC_JSQR_JSQ2_4                     ((u32)0x00000200)        /* Bit 4 */
03464
03465 #define  ADC_JSQR_JSQ3                       ((u32)0x00007C00)        /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
03466 #define  ADC_JSQR_JSQ3_0                     ((u32)0x00000400)        /* Bit 0 */
03467 #define  ADC_JSQR_JSQ3_1                     ((u32)0x00000800)        /* Bit 1 */
03468 #define  ADC_JSQR_JSQ3_2                     ((u32)0x00001000)        /* Bit 2 */
03469 #define  ADC_JSQR_JSQ3_3                     ((u32)0x00002000)        /* Bit 3 */
03470 #define  ADC_JSQR_JSQ3_4                     ((u32)0x00004000)        /* Bit 4 */
03471
03472 #define  ADC_JSQR_JSQ4                       ((u32)0x000F8000)        /* JSQ4[4:0] bits (4th conversion in injected sequence) */
03473 #define  ADC_JSQR_JSQ4_0                     ((u32)0x00008000)        /* Bit 0 */
03474 #define  ADC_JSQR_JSQ4_1                     ((u32)0x00010000)        /* Bit 1 */
03475 #define  ADC_JSQR_JSQ4_2                     ((u32)0x00020000)        /* Bit 2 */
03476 #define  ADC_JSQR_JSQ4_3                     ((u32)0x00040000)        /* Bit 3 */
03477 #define  ADC_JSQR_JSQ4_4                     ((u32)0x00080000)        /* Bit 4 */
03478
03479 #define  ADC_JSQR_JL                         ((u32)0x00300000)        /* JL[1:0] bits (Injected Sequence length) */
03480 #define  ADC_JSQR_JL_0                       ((u32)0x00100000)        /* Bit 0 */
03481 #define  ADC_JSQR_JL_1                       ((u32)0x00200000)        /* Bit 1 */
03482
03483
03484 /*******************  Bit definition for ADC_JDR1 register  *******************/
03485 #define  ADC_JDR1_JDATA                      ((u16)0xFFFF)            /* Injected data */
03486
03487
03488 /*******************  Bit definition for ADC_JDR2 register  *******************/
03489 #define  ADC_JDR2_JDATA                      ((u16)0xFFFF)            /* Injected data */
03490
03491
03492 /*******************  Bit definition for ADC_JDR3 register  *******************/
03493 #define  ADC_JDR3_JDATA                      ((u16)0xFFFF)            /* Injected data */
03494
03495
03496 /*******************  Bit definition for ADC_JDR4 register  *******************/
03497 #define  ADC_JDR4_JDATA                      ((u16)0xFFFF)            /* Injected data */
03498
03499
03500 /********************  Bit definition for ADC_DR register  ********************/
03501 #define  ADC_DR_DATA                         ((u32)0x0000FFFF)        /* Regular data */
03502 #define  ADC_DR_ADC2DATA                     ((u32)0xFFFF0000)        /* ADC2 data */
03503
03504
03505
03506 /******************************************************************************/
03507 /*                                                                            */
03508 /*                      Digital to Analog Converter                           */
03509 /*                                                                            */
03510 /******************************************************************************/
03511
03512 /********************  Bit definition for DAC_CR register  ********************/
03513 #define  DAC_CR_EN1                          ((u32)0x00000001)        /* DAC channel1 enable */
03514 #define  DAC_CR_BOFF1                        ((u32)0x00000002)        /* DAC channel1 output buffer disable */
03515 #define  DAC_CR_TEN1                         ((u32)0x00000004)        /* DAC channel1 Trigger enable */
03516
03517 #define  DAC_CR_TSEL1                        ((u32)0x00000038)        /* TSEL1[2:0] (DAC channel1 Trigger selection) */
03518 #define  DAC_CR_TSEL1_0                      ((u32)0x00000008)        /* Bit 0 */
03519 #define  DAC_CR_TSEL1_1                      ((u32)0x00000010)        /* Bit 1 */
03520 #define  DAC_CR_TSEL1_2                      ((u32)0x00000020)        /* Bit 2 */
03521
03522 #define  DAC_CR_WAVE1                        ((u32)0x000000C0)        /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
03523 #define  DAC_CR_WAVE1_0                      ((u32)0x00000040)        /* Bit 0 */
03524 #define  DAC_CR_WAVE1_1                      ((u32)0x00000080)        /* Bit 1 */
03525
03526 #define  DAC_CR_MAMP1                        ((u32)0x00000F00)        /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
03527 #define  DAC_CR_MAMP1_0                      ((u32)0x00000100)        /* Bit 0 */
03528 #define  DAC_CR_MAMP1_1                      ((u32)0x00000200)        /* Bit 1 */
03529 #define  DAC_CR_MAMP1_2                      ((u32)0x00000400)        /* Bit 2 */
03530 #define  DAC_CR_MAMP1_3                      ((u32)0x00000800)        /* Bit 3 */
03531
03532 #define  DAC_CR_DMAEN1                       ((u32)0x00001000)        /* DAC channel1 DMA enable */
03533 #define  DAC_CR_EN2                          ((u32)0x00010000)        /* DAC channel2 enable */
03534 #define  DAC_CR_BOFF2                        ((u32)0x00020000)        /* DAC channel2 output buffer disable */
03535 #define  DAC_CR_TEN2                         ((u32)0x00040000)        /* DAC channel2 Trigger enable */
03536
03537 #define  DAC_CR_TSEL2                        ((u32)0x00380000)        /* TSEL2[2:0] (DAC channel2 Trigger selection) */
03538 #define  DAC_CR_TSEL2_0                      ((u32)0x00080000)        /* Bit 0 */
03539 #define  DAC_CR_TSEL2_1                      ((u32)0x00100000)        /* Bit 1 */
03540 #define  DAC_CR_TSEL2_2                      ((u32)0x00200000)        /* Bit 2 */
03541
03542 #define  DAC_CR_WAVE2                        ((u32)0x00C00000)        /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
03543 #define  DAC_CR_WAVE2_0                      ((u32)0x00400000)        /* Bit 0 */
03544 #define  DAC_CR_WAVE2_1                      ((u32)0x00800000)        /* Bit 1 */
03545
03546 #define  DAC_CR_MAMP2                        ((u32)0x0F000000)        /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
03547 #define  DAC_CR_MAMP2_0                      ((u32)0x01000000)        /* Bit 0 */
03548 #define  DAC_CR_MAMP2_1                      ((u32)0x02000000)        /* Bit 1 */
03549 #define  DAC_CR_MAMP2_2                      ((u32)0x04000000)        /* Bit 2 */
03550 #define  DAC_CR_MAMP2_3                      ((u32)0x08000000)        /* Bit 3 */
03551
03552 #define  DAC_CR_DMAEN2                       ((u32)0x10000000)        /* DAC channel2 DMA enabled */
03553
03554
03555 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
03556 #define  DAC_SWTRIGR_SWTRIG1                 ((u8)0x01)               /* DAC channel1 software trigger */
03557 #define  DAC_SWTRIGR_SWTRIG2                 ((u8)0x02)               /* DAC channel2 software trigger */
03558
03559
03560 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
03561 #define  DAC_DHR12R1_DACC1DHR                ((u16)0x0FFF)            /* DAC channel1 12-bit Right aligned data */
03562
03563
03564 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
03565 #define  DAC_DHR12L1_DACC1DHR                ((u16)0xFFF0)            /* DAC channel1 12-bit Left aligned data */
03566
03567
03568 /******************  Bit definition for DAC_DHR8R1 register  ******************/
03569 #define  DAC_DHR8R1_DACC1DHR                 ((u8)0xFF)               /* DAC channel1 8-bit Right aligned data */
03570
03571
03572 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
03573 #define  DAC_DHR12R2_DACC2DHR                ((u16)0x0FFF)            /* DAC channel2 12-bit Right aligned data */
03574
03575
03576 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
03577 #define  DAC_DHR12L2_DACC2DHR                ((u16)0xFFF0)            /* DAC channel2 12-bit Left aligned data */
03578
03579
03580 /******************  Bit definition for DAC_DHR8R2 register  ******************/
03581 #define  DAC_DHR8R2_DACC2DHR                 ((u8)0xFF)               /* DAC channel2 8-bit Right aligned data */
03582
03583
03584 /*****************  Bit definition for DAC_DHR12RD register  ******************/
03585 #define  DAC_DHR12RD_DACC1DHR                ((u32)0x00000FFF)        /* DAC channel1 12-bit Right aligned data */
03586 #define  DAC_DHR12RD_DACC2DHR                ((u32)0x0FFF0000)        /* DAC channel2 12-bit Right aligned data */
03587
03588
03589 /*****************  Bit definition for DAC_DHR12LD register  ******************/
03590 #define  DAC_DHR12LD_DACC1DHR                ((u32)0x0000FFF0)        /* DAC channel1 12-bit Left aligned data */
03591 #define  DAC_DHR12LD_DACC2DHR                ((u32)0xFFF00000)        /* DAC channel2 12-bit Left aligned data */
03592
03593
03594 /******************  Bit definition for DAC_DHR8RD register  ******************/
03595 #define  DAC_DHR8RD_DACC1DHR                 ((u16)0x00FF)            /* DAC channel1 8-bit Right aligned data */
03596 #define  DAC_DHR8RD_DACC2DHR                 ((u16)0xFF00)            /* DAC channel2 8-bit Right aligned data */
03597
03598
03599 /*******************  Bit definition for DAC_DOR1 register  *******************/
03600 #define  DAC_DOR1_DACC1DOR                   ((u16)0x0FFF)            /* DAC channel1 data output */
03601
03602
03603 /*******************  Bit definition for DAC_DOR2 register  *******************/
03604 #define  DAC_DOR2_DACC2DOR                   ((u16)0x0FFF)            /* DAC channel2 data output */
03605
03606
03607
03608 /******************************************************************************/
03609 /*                                                                            */
03610 /*                                    TIM                                     */
03611 /*                                                                            */
03612 /******************************************************************************/
03613
03614 /*******************  Bit definition for TIM_CR1 register  ********************/
03615 #define  TIM_CR1_CEN                         ((u16)0x0001)            /* Counter enable */
03616 #define  TIM_CR1_UDIS                        ((u16)0x0002)            /* Update disable */
03617 #define  TIM_CR1_URS                         ((u16)0x0004)            /* Update request source */
03618 #define  TIM_CR1_OPM                         ((u16)0x0008)            /* One pulse mode */
03619 #define  TIM_CR1_DIR                         ((u16)0x0010)            /* Direction */
03620
03621 #define  TIM_CR1_CMS                         ((u16)0x0060)            /* CMS[1:0] bits (Center-aligned mode selection) */
03622 #define  TIM_CR1_CMS_0                       ((u16)0x0020)            /* Bit 0 */
03623 #define  TIM_CR1_CMS_1                       ((u16)0x0040)            /* Bit 1 */
03624
03625 #define  TIM_CR1_ARPE                        ((u16)0x0080)            /* Auto-reload preload enable */
03626
03627 #define  TIM_CR1_CKD                         ((u16)0x0300)            /* CKD[1:0] bits (clock division) */
03628 #define  TIM_CR1_CKD_0                       ((u16)0x0100)            /* Bit 0 */
03629 #define  TIM_CR1_CKD_1                       ((u16)0x0200)            /* Bit 1 */
03630
03631
03632 /*******************  Bit definition for TIM_CR2 register  ********************/
03633 #define  TIM_CR2_CCPC                        ((u16)0x0001)            /* Capture/Compare Preloaded Control */
03634 #define  TIM_CR2_CCUS                        ((u16)0x0004)            /* Capture/Compare Control Update Selection */
03635 #define  TIM_CR2_CCDS                        ((u16)0x0008)            /* Capture/Compare DMA Selection */
03636
03637 #define  TIM_CR2_MMS                         ((u16)0x0070)            /* MMS[2:0] bits (Master Mode Selection) */
03638 #define  TIM_CR2_MMS_0                       ((u16)0x0010)            /* Bit 0 */
03639 #define  TIM_CR2_MMS_1                       ((u16)0x0020)            /* Bit 1 */
03640 #define  TIM_CR2_MMS_2                       ((u16)0x0040)            /* Bit 2 */
03641
03642 #define  TIM_CR2_TI1S                        ((u16)0x0080)            /* TI1 Selection */
03643 #define  TIM_CR2_OIS1                        ((u16)0x0100)            /* Output Idle state 1 (OC1 output) */
03644 #define  TIM_CR2_OIS1N                       ((u16)0x0200)            /* Output Idle state 1 (OC1N output) */
03645 #define  TIM_CR2_OIS2                        ((u16)0x0400)            /* Output Idle state 2 (OC2 output) */
03646 #define  TIM_CR2_OIS2N                       ((u16)0x0800)            /* Output Idle state 2 (OC2N output) */
03647 #define  TIM_CR2_OIS3                        ((u16)0x1000)            /* Output Idle state 3 (OC3 output) */
03648 #define  TIM_CR2_OIS3N                       ((u16)0x2000)            /* Output Idle state 3 (OC3N output) */
03649 #define  TIM_CR2_OIS4                        ((u16)0x4000)            /* Output Idle state 4 (OC4 output) */
03650
03651
03652 /*******************  Bit definition for TIM_SMCR register  *******************/
03653 #define  TIM_SMCR_SMS                        ((u16)0x0007)            /* SMS[2:0] bits (Slave mode selection) */
03654 #define  TIM_SMCR_SMS_0                      ((u16)0x0001)            /* Bit 0 */
03655 #define  TIM_SMCR_SMS_1                      ((u16)0x0002)            /* Bit 1 */
03656 #define  TIM_SMCR_SMS_2                      ((u16)0x0004)            /* Bit 2 */
03657
03658 #define  TIM_SMCR_TS                         ((u16)0x0070)            /* TS[2:0] bits (Trigger selection) */
03659 #define  TIM_SMCR_TS_0                       ((u16)0x0010)            /* Bit 0 */
03660 #define  TIM_SMCR_TS_1                       ((u16)0x0020)            /* Bit 1 */
03661 #define  TIM_SMCR_TS_2                       ((u16)0x0040)            /* Bit 2 */
03662
03663 #define  TIM_SMCR_MSM                        ((u16)0x0080)            /* Master/slave mode */
03664
03665 #define  TIM_SMCR_ETF                        ((u16)0x0F00)            /* ETF[3:0] bits (External trigger filter) */
03666 #define  TIM_SMCR_ETF_0                      ((u16)0x0100)            /* Bit 0 */
03667 #define  TIM_SMCR_ETF_1                      ((u16)0x0200)            /* Bit 1 */
03668 #define  TIM_SMCR_ETF_2                      ((u16)0x0400)            /* Bit 2 */
03669 #define  TIM_SMCR_ETF_3                      ((u16)0x0800)            /* Bit 3 */
03670
03671 #define  TIM_SMCR_ETPS                       ((u16)0x3000)            /* ETPS[1:0] bits (External trigger prescaler) */
03672 #define  TIM_SMCR_ETPS_0                     ((u16)0x1000)            /* Bit 0 */
03673 #define  TIM_SMCR_ETPS_1                     ((u16)0x2000)            /* Bit 1 */
03674
03675 #define  TIM_SMCR_ECE                        ((u16)0x4000)            /* External clock enable */
03676 #define  TIM_SMCR_ETP                        ((u16)0x8000)            /* External trigger polarity */
03677
03678
03679 /*******************  Bit definition for TIM_DIER register  *******************/
03680 #define  TIM_DIER_UIE                        ((u16)0x0001)            /* Update interrupt enable */
03681 #define  TIM_DIER_CC1IE                      ((u16)0x0002)            /* Capture/Compare 1 interrupt enable */
03682 #define  TIM_DIER_CC2IE                      ((u16)0x0004)            /* Capture/Compare 2 interrupt enable */
03683 #define  TIM_DIER_CC3IE                      ((u16)0x0008)            /* Capture/Compare 3 interrupt enable */
03684 #define  TIM_DIER_CC4IE                      ((u16)0x0010)            /* Capture/Compare 4 interrupt enable */
03685 #define  TIM_DIER_COMIE                      ((u16)0x0020)            /* COM interrupt enable */
03686 #define  TIM_DIER_TIE                        ((u16)0x0040)            /* Trigger interrupt enable */
03687 #define  TIM_DIER_BIE                        ((u16)0x0080)            /* Break interrupt enable */
03688 #define  TIM_DIER_UDE                        ((u16)0x0100)            /* Update DMA request enable */
03689 #define  TIM_DIER_CC1DE                      ((u16)0x0200)            /* Capture/Compare 1 DMA request enable */
03690 #define  TIM_DIER_CC2DE                      ((u16)0x0400)            /* Capture/Compare 2 DMA request enable */
03691 #define  TIM_DIER_CC3DE                      ((u16)0x0800)            /* Capture/Compare 3 DMA request enable */
03692 #define  TIM_DIER_CC4DE                      ((u16)0x1000)            /* Capture/Compare 4 DMA request enable */
03693 #define  TIM_DIER_COMDE                      ((u16)0x2000)            /* COM DMA request enable */
03694 #define  TIM_DIER_TDE                        ((u16)0x4000)            /* Trigger DMA request enable */
03695
03696
03697 /********************  Bit definition for TIM_SR register  ********************/
03698 #define  TIM_SR_UIF                          ((u16)0x0001)            /* Update interrupt Flag */
03699 #define  TIM_SR_CC1IF                        ((u16)0x0002)            /* Capture/Compare 1 interrupt Flag */
03700 #define  TIM_SR_CC2IF                        ((u16)0x0004)            /* Capture/Compare 2 interrupt Flag */
03701 #define  TIM_SR_CC3IF                        ((u16)0x0008)            /* Capture/Compare 3 interrupt Flag */
03702 #define  TIM_SR_CC4IF                        ((u16)0x0010)            /* Capture/Compare 4 interrupt Flag */
03703 #define  TIM_SR_COMIF                        ((u16)0x0020)            /* COM interrupt Flag */
03704 #define  TIM_SR_TIF                          ((u16)0x0040)            /* Trigger interrupt Flag */
03705 #define  TIM_SR_BIF                          ((u16)0x0080)            /* Break interrupt Flag */
03706 #define  TIM_SR_CC1OF                        ((u16)0x0200)            /* Capture/Compare 1 Overcapture Flag */
03707 #define  TIM_SR_CC2OF                        ((u16)0x0400)            /* Capture/Compare 2 Overcapture Flag */
03708 #define  TIM_SR_CC3OF                        ((u16)0x0800)            /* Capture/Compare 3 Overcapture Flag */
03709 #define  TIM_SR_CC4OF                        ((u16)0x1000)            /* Capture/Compare 4 Overcapture Flag */
03710
03711
03712 /*******************  Bit definition for TIM_EGR register  ********************/
03713 #define  TIM_EGR_UG                          ((u8)0x01)               /* Update Generation */
03714 #define  TIM_EGR_CC1G                        ((u8)0x02)               /* Capture/Compare 1 Generation */
03715 #define  TIM_EGR_CC2G                        ((u8)0x04)               /* Capture/Compare 2 Generation */
03716 #define  TIM_EGR_CC3G                        ((u8)0x08)               /* Capture/Compare 3 Generation */
03717 #define  TIM_EGR_CC4G                        ((u8)0x10)               /* Capture/Compare 4 Generation */
03718 #define  TIM_EGR_COMG                        ((u8)0x20)               /* Capture/Compare Control Update Generation */
03719 #define  TIM_EGR_TG                          ((u8)0x40)               /* Trigger Generation */
03720 #define  TIM_EGR_BG                          ((u8)0x80)               /* Break Generation */
03721
03722
03723 /******************  Bit definition for TIM_CCMR1 register  *******************/
03724 #define  TIM_CCMR1_CC1S                      ((u16)0x0003)            /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
03725 #define  TIM_CCMR1_CC1S_0                    ((u16)0x0001)            /* Bit 0 */
03726 #define  TIM_CCMR1_CC1S_1                    ((u16)0x0002)            /* Bit 1 */
03727
03728 #define  TIM_CCMR1_OC1FE                     ((u16)0x0004)            /* Output Compare 1 Fast enable */
03729 #define  TIM_CCMR1_OC1PE                     ((u16)0x0008)            /* Output Compare 1 Preload enable */
03730
03731 #define  TIM_CCMR1_OC1M                      ((u16)0x0070)            /* OC1M[2:0] bits (Output Compare 1 Mode) */
03732 #define  TIM_CCMR1_OC1M_0                    ((u16)0x0010)            /* Bit 0 */
03733 #define  TIM_CCMR1_OC1M_1                    ((u16)0x0020)            /* Bit 1 */
03734 #define  TIM_CCMR1_OC1M_2                    ((u16)0x0040)            /* Bit 2 */
03735
03736 #define  TIM_CCMR1_OC1CE                     ((u16)0x0080)            /* Output Compare 1Clear Enable */
03737
03738 #define  TIM_CCMR1_CC2S                      ((u16)0x0300)            /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
03739 #define  TIM_CCMR1_CC2S_0                    ((u16)0x0100)            /* Bit 0 */
03740 #define  TIM_CCMR1_CC2S_1                    ((u16)0x0200)            /* Bit 1 */
03741
03742 #define  TIM_CCMR1_OC2FE                     ((u16)0x0400)            /* Output Compare 2 Fast enable */
03743 #define  TIM_CCMR1_OC2PE                     ((u16)0x0800)            /* Output Compare 2 Preload enable */
03744
03745 #define  TIM_CCMR1_OC2M                      ((u16)0x7000)            /* OC2M[2:0] bits (Output Compare 2 Mode) */
03746 #define  TIM_CCMR1_OC2M_0                    ((u16)0x1000)            /* Bit 0 */
03747 #define  TIM_CCMR1_OC2M_1                    ((u16)0x2000)            /* Bit 1 */
03748 #define  TIM_CCMR1_OC2M_2                    ((u16)0x4000)            /* Bit 2 */
03749
03750 #define  TIM_CCMR1_OC2CE                     ((u16)0x8000)            /* Output Compare 2 Clear Enable */
03751
03752 /*----------------------------------------------------------------------------*/
03753
03754 #define  TIM_CCMR1_IC1PSC                    ((u16)0x000C)            /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
03755 #define  TIM_CCMR1_IC1PSC_0                  ((u16)0x0004)            /* Bit 0 */
03756 #define  TIM_CCMR1_IC1PSC_1                  ((u16)0x0008)            /* Bit 1 */
03757
03758 #define  TIM_CCMR1_IC1F                      ((u16)0x00F0)            /* IC1F[3:0] bits (Input Capture 1 Filter) */
03759 #define  TIM_CCMR1_IC1F_0                    ((u16)0x0010)            /* Bit 0 */
03760 #define  TIM_CCMR1_IC1F_1                    ((u16)0x0020)            /* Bit 1 */
03761 #define  TIM_CCMR1_IC1F_2                    ((u16)0x0040)            /* Bit 2 */
03762 #define  TIM_CCMR1_IC1F_3                    ((u16)0x0080)            /* Bit 3 */
03763
03764 #define  TIM_CCMR1_IC2PSC                    ((u16)0x0C00)            /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
03765 #define  TIM_CCMR1_IC2PSC_0                  ((u16)0x0400)            /* Bit 0 */
03766 #define  TIM_CCMR1_IC2PSC_1                  ((u16)0x0800)            /* Bit 1 */
03767
03768 #define  TIM_CCMR1_IC2F                      ((u16)0xF000)            /* IC2F[3:0] bits (Input Capture 2 Filter) */
03769 #define  TIM_CCMR1_IC2F_0                    ((u16)0x1000)            /* Bit 0 */
03770 #define  TIM_CCMR1_IC2F_1                    ((u16)0x2000)            /* Bit 1 */
03771 #define  TIM_CCMR1_IC2F_2                    ((u16)0x4000)            /* Bit 2 */
03772 #define  TIM_CCMR1_IC2F_3                    ((u16)0x8000)            /* Bit 3 */
03773
03774
03775 /******************  Bit definition for TIM_CCMR2 register  *******************/
03776 #define  TIM_CCMR2_CC3S                      ((u16)0x0003)            /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
03777 #define  TIM_CCMR2_CC3S_0                    ((u16)0x0001)            /* Bit 0 */
03778 #define  TIM_CCMR2_CC3S_1                    ((u16)0x0002)            /* Bit 1 */
03779
03780 #define  TIM_CCMR2_OC3FE                     ((u16)0x0004)            /* Output Compare 3 Fast enable */
03781 #define  TIM_CCMR2_OC3PE                     ((u16)0x0008)            /* Output Compare 3 Preload enable */
03782
03783 #define  TIM_CCMR2_OC3M                      ((u16)0x0070)            /* OC3M[2:0] bits (Output Compare 3 Mode) */
03784 #define  TIM_CCMR2_OC3M_0                    ((u16)0x0010)            /* Bit 0 */
03785 #define  TIM_CCMR2_OC3M_1                    ((u16)0x0020)            /* Bit 1 */
03786 #define  TIM_CCMR2_OC3M_2                    ((u16)0x0040)            /* Bit 2 */
03787
03788 #define  TIM_CCMR2_OC3CE                     ((u16)0x0080)            /* Output Compare 3 Clear Enable */
03789
03790 #define  TIM_CCMR2_CC4S                      ((u16)0x0300)            /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
03791 #define  TIM_CCMR2_CC4S_0                    ((u16)0x0100)            /* Bit 0 */
03792 #define  TIM_CCMR2_CC4S_1                    ((u16)0x0200)            /* Bit 1 */
03793
03794 #define  TIM_CCMR2_OC4FE                     ((u16)0x0400)            /* Output Compare 4 Fast enable */
03795 #define  TIM_CCMR2_OC4PE                     ((u16)0x0800)            /* Output Compare 4 Preload enable */
03796
03797 #define  TIM_CCMR2_OC4M                      ((u16)0x7000)            /* OC4M[2:0] bits (Output Compare 4 Mode) */
03798 #define  TIM_CCMR2_OC4M_0                    ((u16)0x1000)            /* Bit 0 */
03799 #define  TIM_CCMR2_OC4M_1                    ((u16)0x2000)            /* Bit 1 */
03800 #define  TIM_CCMR2_OC4M_2                    ((u16)0x4000)            /* Bit 2 */
03801
03802 #define  TIM_CCMR2_OC4CE                     ((u16)0x8000)            /* Output Compare 4 Clear Enable */
03803
03804 /*----------------------------------------------------------------------------*/
03805
03806 #define  TIM_CCMR2_IC3PSC                    ((u16)0x000C)            /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
03807 #define  TIM_CCMR2_IC3PSC_0                  ((u16)0x0004)            /* Bit 0 */
03808 #define  TIM_CCMR2_IC3PSC_1                  ((u16)0x0008)            /* Bit 1 */
03809
03810 #define  TIM_CCMR2_IC3F                      ((u16)0x00F0)            /* IC3F[3:0] bits (Input Capture 3 Filter) */
03811 #define  TIM_CCMR2_IC3F_0                    ((u16)0x0010)            /* Bit 0 */
03812 #define  TIM_CCMR2_IC3F_1                    ((u16)0x0020)            /* Bit 1 */
03813 #define  TIM_CCMR2_IC3F_2                    ((u16)0x0040)            /* Bit 2 */
03814 #define  TIM_CCMR2_IC3F_3                    ((u16)0x0080)            /* Bit 3 */
03815
03816 #define  TIM_CCMR2_IC4PSC                    ((u16)0x0C00)            /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
03817 #define  TIM_CCMR2_IC4PSC_0                  ((u16)0x0400)            /* Bit 0 */
03818 #define  TIM_CCMR2_IC4PSC_1                  ((u16)0x0800)            /* Bit 1 */
03819
03820 #define  TIM_CCMR2_IC4F                      ((u16)0xF000)            /* IC4F[3:0] bits (Input Capture 4 Filter) */
03821 #define  TIM_CCMR2_IC4F_0                    ((u16)0x1000)            /* Bit 0 */
03822 #define  TIM_CCMR2_IC4F_1                    ((u16)0x2000)            /* Bit 1 */
03823 #define  TIM_CCMR2_IC4F_2                    ((u16)0x4000)            /* Bit 2 */
03824 #define  TIM_CCMR2_IC4F_3                    ((u16)0x8000)            /* Bit 3 */
03825
03826
03827 /*******************  Bit definition for TIM_CCER register  *******************/
03828 #define  TIM_CCER_CC1E                       ((u16)0x0001)            /* Capture/Compare 1 output enable */
03829 #define  TIM_CCER_CC1P                       ((u16)0x0002)            /* Capture/Compare 1 output Polarity */
03830 #define  TIM_CCER_CC1NE                      ((u16)0x0004)            /* Capture/Compare 1 Complementary output enable */
03831 #define  TIM_CCER_CC1NP                      ((u16)0x0008)            /* Capture/Compare 1 Complementary output Polarity */
03832 #define  TIM_CCER_CC2E                       ((u16)0x0010)            /* Capture/Compare 2 output enable */
03833 #define  TIM_CCER_CC2P                       ((u16)0x0020)            /* Capture/Compare 2 output Polarity */
03834 #define  TIM_CCER_CC2NE                      ((u16)0x0040)            /* Capture/Compare 2 Complementary output enable */
03835 #define  TIM_CCER_CC2NP                      ((u16)0x0080)            /* Capture/Compare 2 Complementary output Polarity */
03836 #define  TIM_CCER_CC3E                       ((u16)0x0100)            /* Capture/Compare 3 output enable */
03837 #define  TIM_CCER_CC3P                       ((u16)0x0200)            /* Capture/Compare 3 output Polarity */
03838 #define  TIM_CCER_CC3NE                      ((u16)0x0400)            /* Capture/Compare 3 Complementary output enable */
03839 #define  TIM_CCER_CC3NP                      ((u16)0x0800)            /* Capture/Compare 3 Complementary output Polarity */
03840 #define  TIM_CCER_CC4E                       ((u16)0x1000)            /* Capture/Compare 4 output enable */
03841 #define  TIM_CCER_CC4P                       ((u16)0x2000)            /* Capture/Compare 4 output Polarity */
03842
03843
03844 /*******************  Bit definition for TIM_CNT register  ********************/
03845 #define  TIM_CNT_CNT                         ((u16)0xFFFF)            /* Counter Value */
03846
03847
03848 /*******************  Bit definition for TIM_PSC register  ********************/
03849 #define  TIM_PSC_PSC                         ((u16)0xFFFF)            /* Prescaler Value */
03850
03851
03852 /*******************  Bit definition for TIM_ARR register  ********************/
03853 #define  TIM_ARR_ARR                         ((u16)0xFFFF)            /* actual auto-reload Value */
03854
03855
03856 /*******************  Bit definition for TIM_RCR register  ********************/
03857 #define  TIM_RCR_REP                         ((u8)0xFF)               /* Repetition Counter Value */
03858
03859
03860 /*******************  Bit definition for TIM_CCR1 register  *******************/
03861 #define  TIM_CCR1_CCR1                       ((u16)0xFFFF)            /* Capture/Compare 1 Value */
03862
03863
03864 /*******************  Bit definition for TIM_CCR2 register  *******************/
03865 #define  TIM_CCR2_CCR2                       ((u16)0xFFFF)            /* Capture/Compare 2 Value */
03866
03867
03868 /*******************  Bit definition for TIM_CCR3 register  *******************/
03869 #define  TIM_CCR3_CCR3                       ((u16)0xFFFF)            /* Capture/Compare 3 Value */
03870
03871
03872 /*******************  Bit definition for TIM_CCR4 register  *******************/
03873 #define  TIM_CCR4_CCR4                       ((u16)0xFFFF)            /* Capture/Compare 4 Value */
03874
03875
03876 /*******************  Bit definition for TIM_BDTR register  *******************/
03877 #define  TIM_BDTR_DTG                        ((u16)0x00FF)            /* DTG[0:7] bits (Dead-Time Generator set-up) */
03878 #define  TIM_BDTR_DTG_0                      ((u16)0x0001)            /* Bit 0 */
03879 #define  TIM_BDTR_DTG_1                      ((u16)0x0002)            /* Bit 1 */
03880 #define  TIM_BDTR_DTG_2                      ((u16)0x0004)            /* Bit 2 */
03881 #define  TIM_BDTR_DTG_3                      ((u16)0x0008)            /* Bit 3 */
03882 #define  TIM_BDTR_DTG_4                      ((u16)0x0010)            /* Bit 4 */
03883 #define  TIM_BDTR_DTG_5                      ((u16)0x0020)            /* Bit 5 */
03884 #define  TIM_BDTR_DTG_6                      ((u16)0x0040)            /* Bit 6 */
03885 #define  TIM_BDTR_DTG_7                      ((u16)0x0080)            /* Bit 7 */
03886
03887 #define  TIM_BDTR_LOCK                       ((u16)0x0300)            /* LOCK[1:0] bits (Lock Configuration) */
03888 #define  TIM_BDTR_LOCK_0                     ((u16)0x0100)            /* Bit 0 */
03889 #define  TIM_BDTR_LOCK_1                     ((u16)0x0200)            /* Bit 1 */
03890
03891 #define  TIM_BDTR_OSSI                       ((u16)0x0400)            /* Off-State Selection for Idle mode */
03892 #define  TIM_BDTR_OSSR                       ((u16)0x0800)            /* Off-State Selection for Run mode */
03893 #define  TIM_BDTR_BKE                        ((u16)0x1000)            /* Break enable */
03894 #define  TIM_BDTR_BKP                        ((u16)0x2000)            /* Break Polarity */
03895 #define  TIM_BDTR_AOE                        ((u16)0x4000)            /* Automatic Output enable */
03896 #define  TIM_BDTR_MOE                        ((u16)0x8000)            /* Main Output enable */
03897
03898
03899 /*******************  Bit definition for TIM_DCR register  ********************/
03900 #define  TIM_DCR_DBA                         ((u16)0x001F)            /* DBA[4:0] bits (DMA Base Address) */
03901 #define  TIM_DCR_DBA_0                       ((u16)0x0001)            /* Bit 0 */
03902 #define  TIM_DCR_DBA_1                       ((u16)0x0002)            /* Bit 1 */
03903 #define  TIM_DCR_DBA_2                       ((u16)0x0004)            /* Bit 2 */
03904 #define  TIM_DCR_DBA_3                       ((u16)0x0008)            /* Bit 3 */
03905 #define  TIM_DCR_DBA_4                       ((u16)0x0010)            /* Bit 4 */
03906
03907 #define  TIM_DCR_DBL                         ((u16)0x1F00)            /* DBL[4:0] bits (DMA Burst Length) */
03908 #define  TIM_DCR_DBL_0                       ((u16)0x0100)            /* Bit 0 */
03909 #define  TIM_DCR_DBL_1                       ((u16)0x0200)            /* Bit 1 */
03910 #define  TIM_DCR_DBL_2                       ((u16)0x0400)            /* Bit 2 */
03911 #define  TIM_DCR_DBL_3                       ((u16)0x0800)            /* Bit 3 */
03912 #define  TIM_DCR_DBL_4                       ((u16)0x1000)            /* Bit 4 */
03913
03914
03915 /*******************  Bit definition for TIM_DMAR register  *******************/
03916 #define  TIM_DMAR_DMAB                       ((u16)0xFFFF)            /* DMA register for burst accesses */
03917
03918
03919
03920 /******************************************************************************/
03921 /*                                                                            */
03922 /*                             Real-Time Clock                                */
03923 /*                                                                            */
03924 /******************************************************************************/
03925
03926 /*******************  Bit definition for RTC_CRH register  ********************/
03927 #define  RTC_CRH_SECIE                       ((u8)0x01)               /* Second Interrupt Enable */
03928 #define  RTC_CRH_ALRIE                       ((u8)0x02)               /* Alarm Interrupt Enable */
03929 #define  RTC_CRH_OWIE                        ((u8)0x04)               /* OverfloW Interrupt Enable */
03930
03931
03932 /*******************  Bit definition for RTC_CRL register  ********************/
03933 #define  RTC_CRL_SECF                        ((u8)0x01)               /* Second Flag */
03934 #define  RTC_CRL_ALRF                        ((u8)0x02)               /* Alarm Flag */
03935 #define  RTC_CRL_OWF                         ((u8)0x04)               /* OverfloW Flag */
03936 #define  RTC_CRL_RSF                         ((u8)0x08)               /* Registers Synchronized Flag */
03937 #define  RTC_CRL_CNF                         ((u8)0x10)               /* Configuration Flag */
03938 #define  RTC_CRL_RTOFF                       ((u8)0x20)               /* RTC operation OFF */
03939
03940
03941 /*******************  Bit definition for RTC_PRLH register  *******************/
03942 #define  RTC_PRLH_PRL                        ((u16)0x000F)            /* RTC Prescaler Reload Value High */
03943
03944
03945 /*******************  Bit definition for RTC_PRLL register  *******************/
03946 #define  RTC_PRLL_PRL                        ((u16)0xFFFF)            /* RTC Prescaler Reload Value Low */
03947
03948
03949 /*******************  Bit definition for RTC_DIVH register  *******************/
03950 #define  RTC_DIVH_RTC_DIV                    ((u16)0x000F)            /* RTC Clock Divider High */
03951
03952
03953 /*******************  Bit definition for RTC_DIVL register  *******************/
03954 #define  RTC_DIVL_RTC_DIV                    ((u16)0xFFFF)            /* RTC Clock Divider Low */
03955
03956
03957 /*******************  Bit definition for RTC_CNTH register  *******************/
03958 #define  RTC_CNTH_RTC_CNT                    ((u16)0xFFFF)            /* RTC Counter High */
03959
03960
03961 /*******************  Bit definition for RTC_CNTL register  *******************/
03962 #define  RTC_CNTL_RTC_CNT                    ((u16)0xFFFF)            /* RTC Counter Low */
03963
03964
03965 /*******************  Bit definition for RTC_ALRH register  *******************/
03966 #define  RTC_ALRH_RTC_ALR                    ((u16)0xFFFF)            /* RTC Alarm High */
03967
03968
03969 /*******************  Bit definition for RTC_ALRL register  *******************/
03970 #define  RTC_ALRL_RTC_ALR                    ((u16)0xFFFF)            /* RTC Alarm Low */
03971
03972
03973
03974 /******************************************************************************/
03975 /*                                                                            */
03976 /*                           Independent WATCHDOG                             */
03977 /*                                                                            */
03978 /******************************************************************************/
03979
03980 /*******************  Bit definition for IWDG_KR register  ********************/
03981 #define  IWDG_KR_KEY                         ((u16)0xFFFF)            /* Key value (write only, read 0000h) */
03982
03983
03984 /*******************  Bit definition for IWDG_PR register  ********************/
03985 #define  IWDG_PR_PR                          ((u8)0x07)               /* PR[2:0] (Prescaler divider) */
03986 #define  IWDG_PR_PR_0                        ((u8)0x01)               /* Bit 0 */
03987 #define  IWDG_PR_PR_1                        ((u8)0x02)               /* Bit 1 */
03988 #define  IWDG_PR_PR_2                        ((u8)0x04)               /* Bit 2 */
03989
03990
03991 /*******************  Bit definition for IWDG_RLR register  *******************/
03992 #define  IWDG_RLR_RL                         ((u16)0x0FFF)            /* Watchdog counter reload value */
03993
03994
03995 /*******************  Bit definition for IWDG_SR register  ********************/
03996 #define  IWDG_SR_PVU                         ((u8)0x01)               /* Watchdog prescaler value update */
03997 #define  IWDG_SR_RVU                         ((u8)0x02)               /* Watchdog counter reload value update */
03998
03999
04000
04001 /******************************************************************************/
04002 /*                                                                            */
04003 /*                            Window WATCHDOG                                 */
04004 /*                                                                            */
04005 /******************************************************************************/
04006
04007 /*******************  Bit definition for WWDG_CR register  ********************/
04008 #define  WWDG_CR_T                           ((u8)0x7F)               /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
04009 #define  WWDG_CR_T0                          ((u8)0x01)               /* Bit 0 */
04010 #define  WWDG_CR_T1                          ((u8)0x02)               /* Bit 1 */
04011 #define  WWDG_CR_T2                          ((u8)0x04)               /* Bit 2 */
04012 #define  WWDG_CR_T3                          ((u8)0x08)               /* Bit 3 */
04013 #define  WWDG_CR_T4                          ((u8)0x10)               /* Bit 4 */
04014 #define  WWDG_CR_T5                          ((u8)0x20)               /* Bit 5 */
04015 #define  WWDG_CR_T6                          ((u8)0x40)               /* Bit 6 */
04016
04017 #define  WWDG_CR_WDGA                        ((u8)0x80)               /* Activation bit */
04018
04019
04020 /*******************  Bit definition for WWDG_CFR register  *******************/
04021 #define  WWDG_CFR_W                          ((u16)0x007F)            /* W[6:0] bits (7-bit window value) */
04022 #define  WWDG_CFR_W0                         ((u16)0x0001)            /* Bit 0 */
04023 #define  WWDG_CFR_W1                         ((u16)0x0002)            /* Bit 1 */
04024 #define  WWDG_CFR_W2                         ((u16)0x0004)            /* Bit 2 */
04025 #define  WWDG_CFR_W3                         ((u16)0x0008)            /* Bit 3 */
04026 #define  WWDG_CFR_W4                         ((u16)0x0010)            /* Bit 4 */
04027 #define  WWDG_CFR_W5                         ((u16)0x0020)            /* Bit 5 */
04028 #define  WWDG_CFR_W6                         ((u16)0x0040)            /* Bit 6 */
04029
04030 #define  WWDG_CFR_WDGTB                      ((u16)0x0180)            /* WDGTB[1:0] bits (Timer Base) */
04031 #define  WWDG_CFR_WDGTB0                     ((u16)0x0080)            /* Bit 0 */
04032 #define  WWDG_CFR_WDGTB1                     ((u16)0x0100)            /* Bit 1 */
04033
04034 #define  WWDG_CFR_EWI                        ((u16)0x0200)            /* Early Wakeup Interrupt */
04035
04036
04037 /*******************  Bit definition for WWDG_SR register  ********************/
04038 #define  WWDG_SR_EWIF                        ((u8)0x01)               /* Early Wakeup Interrupt Flag */
04039
04040
04041
04042 /******************************************************************************/
04043 /*                                                                            */
04044 /*                       Flexible Static Memory Controller                    */
04045 /*                                                                            */
04046 /******************************************************************************/
04047
04048 /******************  Bit definition for FSMC_BCR1 register  *******************/
04049 #define  FSMC_BCR1_MBKEN                     ((u32)0x00000001)        /* Memory bank enable bit */
04050 #define  FSMC_BCR1_MUXEN                     ((u32)0x00000002)        /* Address/data multiplexing enable bit */
04051
04052 #define  FSMC_BCR1_MTYP                      ((u32)0x0000000C)        /* MTYP[1:0] bits (Memory type) */
04053 #define  FSMC_BCR1_MTYP_0                    ((u32)0x00000004)        /* Bit 0 */
04054 #define  FSMC_BCR1_MTYP_1                    ((u32)0x00000008)        /* Bit 1 */
04055
04056 #define  FSMC_BCR1_MWID                      ((u32)0x00000030)        /* MWID[1:0] bits (Memory data bus width) */
04057 #define  FSMC_BCR1_MWID_0                    ((u32)0x00000010)        /* Bit 0 */
04058 #define  FSMC_BCR1_MWID_1                    ((u32)0x00000020)        /* Bit 1 */
04059
04060 #define  FSMC_BCR1_FACCEN                    ((u32)0x00000040)        /* Flash access enable */
04061 #define  FSMC_BCR1_BURSTEN                   ((u32)0x00000100)        /* Burst enable bit */
04062 #define  FSMC_BCR1_WAITPOL                   ((u32)0x00000200)        /* Wait signal polarity bit */
04063 #define  FSMC_BCR1_WRAPMOD                   ((u32)0x00000400)        /* Wrapped burst mode support */
04064 #define  FSMC_BCR1_WAITCFG                   ((u32)0x00000800)        /* Wait timing configuration */
04065 #define  FSMC_BCR1_WREN                      ((u32)0x00001000)        /* Write enable bit */
04066 #define  FSMC_BCR1_WAITEN                    ((u32)0x00002000)        /* Wait enable bit */
04067 #define  FSMC_BCR1_EXTMOD                    ((u32)0x00004000)        /* Extended mode enable */
04068 #define  FSMC_BCR1_CBURSTRW                  ((u32)0x00080000)        /* Write burst enable */
04069
04070
04071 /******************  Bit definition for FSMC_BCR2 register  *******************/
04072 #define  FSMC_BCR2_MBKEN                     ((u32)0x00000001)        /* Memory bank enable bit */
04073 #define  FSMC_BCR2_MUXEN                     ((u32)0x00000002)        /* Address/data multiplexing enable bit */
04074
04075 #define  FSMC_BCR2_MTYP                      ((u32)0x0000000C)        /* MTYP[1:0] bits (Memory type) */
04076 #define  FSMC_BCR2_MTYP_0                    ((u32)0x00000004)        /* Bit 0 */
04077 #define  FSMC_BCR2_MTYP_1                    ((u32)0x00000008)        /* Bit 1 */
04078
04079 #define  FSMC_BCR2_MWID                      ((u32)0x00000030)        /* MWID[1:0] bits (Memory data bus width) */
04080 #define  FSMC_BCR2_MWID_0                    ((u32)0x00000010)        /* Bit 0 */
04081 #define  FSMC_BCR2_MWID_1                    ((u32)0x00000020)        /* Bit 1 */
04082
04083 #define  FSMC_BCR2_FACCEN                    ((u32)0x00000040)        /* Flash access enable */
04084 #define  FSMC_BCR2_BURSTEN                   ((u32)0x00000100)        /* Burst enable bit */
04085 #define  FSMC_BCR2_WAITPOL                   ((u32)0x00000200)        /* Wait signal polarity bit */
04086 #define  FSMC_BCR2_WRAPMOD                   ((u32)0x00000400)        /* Wrapped burst mode support */
04087 #define  FSMC_BCR2_WAITCFG                   ((u32)0x00000800)        /* Wait timing configuration */
04088 #define  FSMC_BCR2_WREN                      ((u32)0x00001000)        /* Write enable bit */
04089 #define  FSMC_BCR2_WAITEN                    ((u32)0x00002000)        /* Wait enable bit */
04090 #define  FSMC_BCR2_EXTMOD                    ((u32)0x00004000)        /* Extended mode enable */
04091 #define  FSMC_BCR2_CBURSTRW                  ((u32)0x00080000)        /* Write burst enable */
04092
04093
04094 /******************  Bit definition for FSMC_BCR3 register  *******************/
04095 #define  FSMC_BCR3_MBKEN                     ((u32)0x00000001)        /* Memory bank enable bit */
04096 #define  FSMC_BCR3_MUXEN                     ((u32)0x00000002)        /* Address/data multiplexing enable bit */
04097
04098 #define  FSMC_BCR3_MTYP                      ((u32)0x0000000C)        /* MTYP[1:0] bits (Memory type) */
04099 #define  FSMC_BCR3_MTYP_0                    ((u32)0x00000004)        /* Bit 0 */
04100 #define  FSMC_BCR3_MTYP_1                    ((u32)0x00000008)        /* Bit 1 */
04101
04102 #define  FSMC_BCR3_MWID                      ((u32)0x00000030)        /* MWID[1:0] bits (Memory data bus width) */
04103 #define  FSMC_BCR3_MWID_0                    ((u32)0x00000010)        /* Bit 0 */
04104 #define  FSMC_BCR3_MWID_1                    ((u32)0x00000020)        /* Bit 1 */
04105
04106 #define  FSMC_BCR3_FACCEN                    ((u32)0x00000040)        /* Flash access enable */
04107 #define  FSMC_BCR3_BURSTEN                   ((u32)0x00000100)        /* Burst enable bit */
04108 #define  FSMC_BCR3_WAITPOL                   ((u32)0x00000200)        /* Wait signal polarity bit. */
04109 #define  FSMC_BCR3_WRAPMOD                   ((u32)0x00000400)        /* Wrapped burst mode support */
04110 #define  FSMC_BCR3_WAITCFG                   ((u32)0x00000800)        /* Wait timing configuration */
04111 #define  FSMC_BCR3_WREN                      ((u32)0x00001000)        /* Write enable bit */
04112 #define  FSMC_BCR3_WAITEN                    ((u32)0x00002000)        /* Wait enable bit */
04113 #define  FSMC_BCR3_EXTMOD                    ((u32)0x00004000)        /* Extended mode enable */
04114 #define  FSMC_BCR3_CBURSTRW                  ((u32)0x00080000)        /* Write burst enable */
04115
04116
04117 /******************  Bit definition for FSMC_BCR4 register  *******************/
04118 #define  FSMC_BCR4_MBKEN                     ((u32)0x00000001)        /* Memory bank enable bit */
04119 #define  FSMC_BCR4_MUXEN                     ((u32)0x00000002)        /* Address/data multiplexing enable bit */
04120
04121 #define  FSMC_BCR4_MTYP                      ((u32)0x0000000C)        /* MTYP[1:0] bits (Memory type) */
04122 #define  FSMC_BCR4_MTYP_0                    ((u32)0x00000004)        /* Bit 0 */
04123 #define  FSMC_BCR4_MTYP_1                    ((u32)0x00000008)        /* Bit 1 */
04124
04125 #define  FSMC_BCR4_MWID                      ((u32)0x00000030)        /* MWID[1:0] bits (Memory data bus width) */
04126 #define  FSMC_BCR4_MWID_0                    ((u32)0x00000010)        /* Bit 0 */
04127 #define  FSMC_BCR4_MWID_1                    ((u32)0x00000020)        /* Bit 1 */
04128
04129 #define  FSMC_BCR4_FACCEN                    ((u32)0x00000040)        /* Flash access enable */
04130 #define  FSMC_BCR4_BURSTEN                   ((u32)0x00000100)        /* Burst enable bit */
04131 #define  FSMC_BCR4_WAITPOL                   ((u32)0x00000200)        /* Wait signal polarity bit */
04132 #define  FSMC_BCR4_WRAPMOD                   ((u32)0x00000400)        /* Wrapped burst mode support */
04133 #define  FSMC_BCR4_WAITCFG                   ((u32)0x00000800)        /* Wait timing configuration */
04134 #define  FSMC_BCR4_WREN                      ((u32)0x00001000)        /* Write enable bit */
04135 #define  FSMC_BCR4_WAITEN                    ((u32)0x00002000)        /* Wait enable bit */
04136 #define  FSMC_BCR4_EXTMOD                    ((u32)0x00004000)        /* Extended mode enable */
04137 #define  FSMC_BCR4_CBURSTRW                  ((u32)0x00080000)        /* Write burst enable */
04138
04139
04140 /******************  Bit definition for FSMC_BTR1 register  ******************/
04141 #define  FSMC_BTR1_ADDSET                    ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04142 #define  FSMC_BTR1_ADDSET_0                  ((u32)0x00000001)        /* Bit 0 */
04143 #define  FSMC_BTR1_ADDSET_1                  ((u32)0x00000002)        /* Bit 1 */
04144 #define  FSMC_BTR1_ADDSET_2                  ((u32)0x00000004)        /* Bit 2 */
04145 #define  FSMC_BTR1_ADDSET_3                  ((u32)0x00000008)        /* Bit 3 */
04146
04147 #define  FSMC_BTR1_ADDHLD                    ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04148 #define  FSMC_BTR1_ADDHLD_0                  ((u32)0x00000010)        /* Bit 0 */
04149 #define  FSMC_BTR1_ADDHLD_1                  ((u32)0x00000020)        /* Bit 1 */
04150 #define  FSMC_BTR1_ADDHLD_2                  ((u32)0x00000040)        /* Bit 2 */
04151 #define  FSMC_BTR1_ADDHLD_3                  ((u32)0x00000080)        /* Bit 3 */
04152
04153 #define  FSMC_BTR1_DATAST                    ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04154 #define  FSMC_BTR1_DATAST_0                  ((u32)0x00000100)        /* Bit 0 */
04155 #define  FSMC_BTR1_DATAST_1                  ((u32)0x00000200)        /* Bit 1 */
04156 #define  FSMC_BTR1_DATAST_2                  ((u32)0x00000400)        /* Bit 2 */
04157 #define  FSMC_BTR1_DATAST_3                  ((u32)0x00000800)        /* Bit 3 */
04158
04159 #define  FSMC_BTR1_BUSTURN                   ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04160 #define  FSMC_BTR1_BUSTURN_0                 ((u32)0x00010000)        /* Bit 0 */
04161 #define  FSMC_BTR1_BUSTURN_1                 ((u32)0x00020000)        /* Bit 1 */
04162 #define  FSMC_BTR1_BUSTURN_2                 ((u32)0x00040000)        /* Bit 2 */
04163 #define  FSMC_BTR1_BUSTURN_3                 ((u32)0x00080000)        /* Bit 3 */
04164
04165 #define  FSMC_BTR1_CLKDIV                    ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04166 #define  FSMC_BTR1_CLKDIV_0                  ((u32)0x00100000)        /* Bit 0 */
04167 #define  FSMC_BTR1_CLKDIV_1                  ((u32)0x00200000)        /* Bit 1 */
04168 #define  FSMC_BTR1_CLKDIV_2                  ((u32)0x00400000)        /* Bit 2 */
04169 #define  FSMC_BTR1_CLKDIV_3                  ((u32)0x00800000)        /* Bit 3 */
04170
04171 #define  FSMC_BTR1_DATLAT                    ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04172 #define  FSMC_BTR1_DATLAT_0                  ((u32)0x01000000)        /* Bit 0 */
04173 #define  FSMC_BTR1_DATLAT_1                  ((u32)0x02000000)        /* Bit 1 */
04174 #define  FSMC_BTR1_DATLAT_2                  ((u32)0x04000000)        /* Bit 2 */
04175 #define  FSMC_BTR1_DATLAT_3                  ((u32)0x08000000)        /* Bit 3 */
04176
04177 #define  FSMC_BTR1_ACCMOD                    ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04178 #define  FSMC_BTR1_ACCMOD_0                  ((u32)0x10000000)        /* Bit 0 */
04179 #define  FSMC_BTR1_ACCMOD_1                  ((u32)0x20000000)        /* Bit 1 */
04180
04181
04182 /******************  Bit definition for FSMC_BTR2 register  *******************/
04183 #define  FSMC_BTR2_ADDSET                    ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04184 #define  FSMC_BTR2_ADDSET_0                  ((u32)0x00000001)        /* Bit 0 */
04185 #define  FSMC_BTR2_ADDSET_1                  ((u32)0x00000002)        /* Bit 1 */
04186 #define  FSMC_BTR2_ADDSET_2                  ((u32)0x00000004)        /* Bit 2 */
04187 #define  FSMC_BTR2_ADDSET_3                  ((u32)0x00000008)        /* Bit 3 */
04188
04189 #define  FSMC_BTR2_ADDHLD                    ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04190 #define  FSMC_BTR2_ADDHLD_0                  ((u32)0x00000010)        /* Bit 0 */
04191 #define  FSMC_BTR2_ADDHLD_1                  ((u32)0x00000020)        /* Bit 1 */
04192 #define  FSMC_BTR2_ADDHLD_2                  ((u32)0x00000040)        /* Bit 2 */
04193 #define  FSMC_BTR2_ADDHLD_3                  ((u32)0x00000080)        /* Bit 3 */
04194
04195 #define  FSMC_BTR2_DATAST                    ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04196 #define  FSMC_BTR2_DATAST_0                  ((u32)0x00000100)        /* Bit 0 */
04197 #define  FSMC_BTR2_DATAST_1                  ((u32)0x00000200)        /* Bit 1 */
04198 #define  FSMC_BTR2_DATAST_2                  ((u32)0x00000400)        /* Bit 2 */
04199 #define  FSMC_BTR2_DATAST_3                  ((u32)0x00000800)        /* Bit 3 */
04200
04201 #define  FSMC_BTR2_BUSTURN                   ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04202 #define  FSMC_BTR2_BUSTURN_0                 ((u32)0x00010000)        /* Bit 0 */
04203 #define  FSMC_BTR2_BUSTURN_1                 ((u32)0x00020000)        /* Bit 1 */
04204 #define  FSMC_BTR2_BUSTURN_2                 ((u32)0x00040000)        /* Bit 2 */
04205 #define  FSMC_BTR2_BUSTURN_3                 ((u32)0x00080000)        /* Bit 3 */
04206
04207 #define  FSMC_BTR2_CLKDIV                    ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04208 #define  FSMC_BTR2_CLKDIV_0                  ((u32)0x00100000)        /* Bit 0 */
04209 #define  FSMC_BTR2_CLKDIV_1                  ((u32)0x00200000)        /* Bit 1 */
04210 #define  FSMC_BTR2_CLKDIV_2                  ((u32)0x00400000)        /* Bit 2 */
04211 #define  FSMC_BTR2_CLKDIV_3                  ((u32)0x00800000)        /* Bit 3 */
04212
04213 #define  FSMC_BTR2_DATLAT                    ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04214 #define  FSMC_BTR2_DATLAT_0                  ((u32)0x01000000)        /* Bit 0 */
04215 #define  FSMC_BTR2_DATLAT_1                  ((u32)0x02000000)        /* Bit 1 */
04216 #define  FSMC_BTR2_DATLAT_2                  ((u32)0x04000000)        /* Bit 2 */
04217 #define  FSMC_BTR2_DATLAT_3                  ((u32)0x08000000)        /* Bit 3 */
04218
04219 #define  FSMC_BTR2_ACCMOD                    ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04220 #define  FSMC_BTR2_ACCMOD_0                  ((u32)0x10000000)        /* Bit 0 */
04221 #define  FSMC_BTR2_ACCMOD_1                  ((u32)0x20000000)        /* Bit 1 */
04222
04223
04224 /*******************  Bit definition for FSMC_BTR3 register  *******************/
04225 #define  FSMC_BTR3_ADDSET                    ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04226 #define  FSMC_BTR3_ADDSET_0                  ((u32)0x00000001)        /* Bit 0 */
04227 #define  FSMC_BTR3_ADDSET_1                  ((u32)0x00000002)        /* Bit 1 */
04228 #define  FSMC_BTR3_ADDSET_2                  ((u32)0x00000004)        /* Bit 2 */
04229 #define  FSMC_BTR3_ADDSET_3                  ((u32)0x00000008)        /* Bit 3 */
04230
04231 #define  FSMC_BTR3_ADDHLD                    ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04232 #define  FSMC_BTR3_ADDHLD_0                  ((u32)0x00000010)        /* Bit 0 */
04233 #define  FSMC_BTR3_ADDHLD_1                  ((u32)0x00000020)        /* Bit 1 */
04234 #define  FSMC_BTR3_ADDHLD_2                  ((u32)0x00000040)        /* Bit 2 */
04235 #define  FSMC_BTR3_ADDHLD_3                  ((u32)0x00000080)        /* Bit 3 */
04236
04237 #define  FSMC_BTR3_DATAST                    ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04238 #define  FSMC_BTR3_DATAST_0                  ((u32)0x00000100)        /* Bit 0 */
04239 #define  FSMC_BTR3_DATAST_1                  ((u32)0x00000200)        /* Bit 1 */
04240 #define  FSMC_BTR3_DATAST_2                  ((u32)0x00000400)        /* Bit 2 */
04241 #define  FSMC_BTR3_DATAST_3                  ((u32)0x00000800)        /* Bit 3 */
04242
04243 #define  FSMC_BTR3_BUSTURN                   ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04244 #define  FSMC_BTR3_BUSTURN_0                 ((u32)0x00010000)        /* Bit 0 */
04245 #define  FSMC_BTR3_BUSTURN_1                 ((u32)0x00020000)        /* Bit 1 */
04246 #define  FSMC_BTR3_BUSTURN_2                 ((u32)0x00040000)        /* Bit 2 */
04247 #define  FSMC_BTR3_BUSTURN_3                 ((u32)0x00080000)        /* Bit 3 */
04248
04249 #define  FSMC_BTR3_CLKDIV                    ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04250 #define  FSMC_BTR3_CLKDIV_0                  ((u32)0x00100000)        /* Bit 0 */
04251 #define  FSMC_BTR3_CLKDIV_1                  ((u32)0x00200000)        /* Bit 1 */
04252 #define  FSMC_BTR3_CLKDIV_2                  ((u32)0x00400000)        /* Bit 2 */
04253 #define  FSMC_BTR3_CLKDIV_3                  ((u32)0x00800000)        /* Bit 3 */
04254
04255 #define  FSMC_BTR3_DATLAT                    ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04256 #define  FSMC_BTR3_DATLAT_0                  ((u32)0x01000000)        /* Bit 0 */
04257 #define  FSMC_BTR3_DATLAT_1                  ((u32)0x02000000)        /* Bit 1 */
04258 #define  FSMC_BTR3_DATLAT_2                  ((u32)0x04000000)        /* Bit 2 */
04259 #define  FSMC_BTR3_DATLAT_3                  ((u32)0x08000000)        /* Bit 3 */
04260
04261 #define  FSMC_BTR3_ACCMOD                    ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04262 #define  FSMC_BTR3_ACCMOD_0                  ((u32)0x10000000)        /* Bit 0 */
04263 #define  FSMC_BTR3_ACCMOD_1                  ((u32)0x20000000)        /* Bit 1 */
04264
04265
04266 /******************  Bit definition for FSMC_BTR4 register  *******************/
04267 #define  FSMC_BTR4_ADDSET                    ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04268 #define  FSMC_BTR4_ADDSET_0                  ((u32)0x00000001)        /* Bit 0 */
04269 #define  FSMC_BTR4_ADDSET_1                  ((u32)0x00000002)        /* Bit 1 */
04270 #define  FSMC_BTR4_ADDSET_2                  ((u32)0x00000004)        /* Bit 2 */
04271 #define  FSMC_BTR4_ADDSET_3                  ((u32)0x00000008)        /* Bit 3 */
04272
04273 #define  FSMC_BTR4_ADDHLD                    ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04274 #define  FSMC_BTR4_ADDHLD_0                  ((u32)0x00000010)        /* Bit 0 */
04275 #define  FSMC_BTR4_ADDHLD_1                  ((u32)0x00000020)        /* Bit 1 */
04276 #define  FSMC_BTR4_ADDHLD_2                  ((u32)0x00000040)        /* Bit 2 */
04277 #define  FSMC_BTR4_ADDHLD_3                  ((u32)0x00000080)        /* Bit 3 */
04278
04279 #define  FSMC_BTR4_DATAST                    ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04280 #define  FSMC_BTR4_DATAST_0                  ((u32)0x00000100)        /* Bit 0 */
04281 #define  FSMC_BTR4_DATAST_1                  ((u32)0x00000200)        /* Bit 1 */
04282 #define  FSMC_BTR4_DATAST_2                  ((u32)0x00000400)        /* Bit 2 */
04283 #define  FSMC_BTR4_DATAST_3                  ((u32)0x00000800)        /* Bit 3 */
04284
04285 #define  FSMC_BTR4_BUSTURN                   ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04286 #define  FSMC_BTR4_BUSTURN_0                 ((u32)0x00010000)        /* Bit 0 */
04287 #define  FSMC_BTR4_BUSTURN_1                 ((u32)0x00020000)        /* Bit 1 */
04288 #define  FSMC_BTR4_BUSTURN_2                 ((u32)0x00040000)        /* Bit 2 */
04289 #define  FSMC_BTR4_BUSTURN_3                 ((u32)0x00080000)        /* Bit 3 */
04290
04291 #define  FSMC_BTR4_CLKDIV                    ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04292 #define  FSMC_BTR4_CLKDIV_0                  ((u32)0x00100000)        /* Bit 0 */
04293 #define  FSMC_BTR4_CLKDIV_1                  ((u32)0x00200000)        /* Bit 1 */
04294 #define  FSMC_BTR4_CLKDIV_2                  ((u32)0x00400000)        /* Bit 2 */
04295 #define  FSMC_BTR4_CLKDIV_3                  ((u32)0x00800000)        /* Bit 3 */
04296
04297 #define  FSMC_BTR4_DATLAT                    ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04298 #define  FSMC_BTR4_DATLAT_0                  ((u32)0x01000000)        /* Bit 0 */
04299 #define  FSMC_BTR4_DATLAT_1                  ((u32)0x02000000)        /* Bit 1 */
04300 #define  FSMC_BTR4_DATLAT_2                  ((u32)0x04000000)        /* Bit 2 */
04301 #define  FSMC_BTR4_DATLAT_3                  ((u32)0x08000000)        /* Bit 3 */
04302
04303 #define  FSMC_BTR4_ACCMOD                    ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04304 #define  FSMC_BTR4_ACCMOD_0                  ((u32)0x10000000)        /* Bit 0 */
04305 #define  FSMC_BTR4_ACCMOD_1                  ((u32)0x20000000)        /* Bit 1 */
04306
04307
04308 /******************  Bit definition for FSMC_BWTR1 register  ******************/
04309 #define  FSMC_BWTR1_ADDSET                   ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04310 #define  FSMC_BWTR1_ADDSET_0                 ((u32)0x00000001)        /* Bit 0 */
04311 #define  FSMC_BWTR1_ADDSET_1                 ((u32)0x00000002)        /* Bit 1 */
04312 #define  FSMC_BWTR1_ADDSET_2                 ((u32)0x00000004)        /* Bit 2 */
04313 #define  FSMC_BWTR1_ADDSET_3                 ((u32)0x00000008)        /* Bit 3 */
04314
04315 #define  FSMC_BWTR1_ADDHLD                   ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04316 #define  FSMC_BWTR1_ADDHLD_0                 ((u32)0x00000010)        /* Bit 0 */
04317 #define  FSMC_BWTR1_ADDHLD_1                 ((u32)0x00000020)        /* Bit 1 */
04318 #define  FSMC_BWTR1_ADDHLD_2                 ((u32)0x00000040)        /* Bit 2 */
04319 #define  FSMC_BWTR1_ADDHLD_3                 ((u32)0x00000080)        /* Bit 3 */
04320
04321 #define  FSMC_BWTR1_DATAST                   ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04322 #define  FSMC_BWTR1_DATAST_0                 ((u32)0x00000100)        /* Bit 0 */
04323 #define  FSMC_BWTR1_DATAST_1                 ((u32)0x00000200)        /* Bit 1 */
04324 #define  FSMC_BWTR1_DATAST_2                 ((u32)0x00000400)        /* Bit 2 */
04325 #define  FSMC_BWTR1_DATAST_3                 ((u32)0x00000800)        /* Bit 3 */
04326
04327 #define  FSMC_BWTR1_BUSTURN                  ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04328 #define  FSMC_BWTR1_BUSTURN_0                ((u32)0x00010000)        /* Bit 0 */
04329 #define  FSMC_BWTR1_BUSTURN_1                ((u32)0x00020000)        /* Bit 1 */
04330 #define  FSMC_BWTR1_BUSTURN_2                ((u32)0x00040000)        /* Bit 2 */
04331 #define  FSMC_BWTR1_BUSTURN_3                ((u32)0x00080000)        /* Bit 3 */
04332
04333 #define  FSMC_BWTR1_CLKDIV                   ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04334 #define  FSMC_BWTR1_CLKDIV_0                 ((u32)0x00100000)        /* Bit 0 */
04335 #define  FSMC_BWTR1_CLKDIV_1                 ((u32)0x00200000)        /* Bit 1 */
04336 #define  FSMC_BWTR1_CLKDIV_2                 ((u32)0x00400000)        /* Bit 2 */
04337 #define  FSMC_BWTR1_CLKDIV_3                 ((u32)0x00800000)        /* Bit 3 */
04338
04339 #define  FSMC_BWTR1_DATLAT                   ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04340 #define  FSMC_BWTR1_DATLAT_0                 ((u32)0x01000000)        /* Bit 0 */
04341 #define  FSMC_BWTR1_DATLAT_1                 ((u32)0x02000000)        /* Bit 1 */
04342 #define  FSMC_BWTR1_DATLAT_2                 ((u32)0x04000000)        /* Bit 2 */
04343 #define  FSMC_BWTR1_DATLAT_3                 ((u32)0x08000000)        /* Bit 3 */
04344
04345 #define  FSMC_BWTR1_ACCMOD                   ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04346 #define  FSMC_BWTR1_ACCMOD_0                 ((u32)0x10000000)        /* Bit 0 */
04347 #define  FSMC_BWTR1_ACCMOD_1                 ((u32)0x20000000)        /* Bit 1 */
04348
04349
04350 /******************  Bit definition for FSMC_BWTR2 register  ******************/
04351 #define  FSMC_BWTR2_ADDSET                   ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04352 #define  FSMC_BWTR2_ADDSET_0                 ((u32)0x00000001)        /* Bit 0 */
04353 #define  FSMC_BWTR2_ADDSET_1                 ((u32)0x00000002)        /* Bit 1 */
04354 #define  FSMC_BWTR2_ADDSET_2                 ((u32)0x00000004)        /* Bit 2 */
04355 #define  FSMC_BWTR2_ADDSET_3                 ((u32)0x00000008)        /* Bit 3 */
04356
04357 #define  FSMC_BWTR2_ADDHLD                   ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04358 #define  FSMC_BWTR2_ADDHLD_0                 ((u32)0x00000010)        /* Bit 0 */
04359 #define  FSMC_BWTR2_ADDHLD_1                 ((u32)0x00000020)        /* Bit 1 */
04360 #define  FSMC_BWTR2_ADDHLD_2                 ((u32)0x00000040)        /* Bit 2 */
04361 #define  FSMC_BWTR2_ADDHLD_3                 ((u32)0x00000080)        /* Bit 3 */
04362
04363 #define  FSMC_BWTR2_DATAST                   ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04364 #define  FSMC_BWTR2_DATAST_0                 ((u32)0x00000100)        /* Bit 0 */
04365 #define  FSMC_BWTR2_DATAST_1                 ((u32)0x00000200)        /* Bit 1 */
04366 #define  FSMC_BWTR2_DATAST_2                 ((u32)0x00000400)        /* Bit 2 */
04367 #define  FSMC_BWTR2_DATAST_3                 ((u32)0x00000800)        /* Bit 3 */
04368
04369 #define  FSMC_BWTR2_BUSTURN                  ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04370 #define  FSMC_BWTR2_BUSTURN_0                ((u32)0x00010000)        /* Bit 0 */
04371 #define  FSMC_BWTR2_BUSTURN_1                ((u32)0x00020000)        /* Bit 1 */
04372 #define  FSMC_BWTR2_BUSTURN_2                ((u32)0x00040000)        /* Bit 2 */
04373 #define  FSMC_BWTR2_BUSTURN_3                ((u32)0x00080000)        /* Bit 3 */
04374
04375 #define  FSMC_BWTR2_CLKDIV                   ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04376 #define  FSMC_BWTR2_CLKDIV_0                 ((u32)0x00100000)        /* Bit 0 */
04377 #define  FSMC_BWTR2_CLKDIV_1                 ((u32)0x00200000)        /* Bit 1*/
04378 #define  FSMC_BWTR2_CLKDIV_2                 ((u32)0x00400000)        /* Bit 2 */
04379 #define  FSMC_BWTR2_CLKDIV_3                 ((u32)0x00800000)        /* Bit 3 */
04380
04381 #define  FSMC_BWTR2_DATLAT                   ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04382 #define  FSMC_BWTR2_DATLAT_0                 ((u32)0x01000000)        /* Bit 0 */
04383 #define  FSMC_BWTR2_DATLAT_1                 ((u32)0x02000000)        /* Bit 1 */
04384 #define  FSMC_BWTR2_DATLAT_2                 ((u32)0x04000000)        /* Bit 2 */
04385 #define  FSMC_BWTR2_DATLAT_3                 ((u32)0x08000000)        /* Bit 3 */
04386
04387 #define  FSMC_BWTR2_ACCMOD                   ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04388 #define  FSMC_BWTR2_ACCMOD_0                 ((u32)0x10000000)        /* Bit 0 */
04389 #define  FSMC_BWTR2_ACCMOD_1                 ((u32)0x20000000)        /* Bit 1 */
04390
04391
04392 /******************  Bit definition for FSMC_BWTR3 register  ******************/
04393 #define  FSMC_BWTR3_ADDSET                   ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04394 #define  FSMC_BWTR3_ADDSET_0                 ((u32)0x00000001)        /* Bit 0 */
04395 #define  FSMC_BWTR3_ADDSET_1                 ((u32)0x00000002)        /* Bit 1 */
04396 #define  FSMC_BWTR3_ADDSET_2                 ((u32)0x00000004)        /* Bit 2 */
04397 #define  FSMC_BWTR3_ADDSET_3                 ((u32)0x00000008)        /* Bit 3 */
04398
04399 #define  FSMC_BWTR3_ADDHLD                   ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04400 #define  FSMC_BWTR3_ADDHLD_0                 ((u32)0x00000010)        /* Bit 0 */
04401 #define  FSMC_BWTR3_ADDHLD_1                 ((u32)0x00000020)        /* Bit 1 */
04402 #define  FSMC_BWTR3_ADDHLD_2                 ((u32)0x00000040)        /* Bit 2 */
04403 #define  FSMC_BWTR3_ADDHLD_3                 ((u32)0x00000080)        /* Bit 3 */
04404
04405 #define  FSMC_BWTR3_DATAST                   ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04406 #define  FSMC_BWTR3_DATAST_0                 ((u32)0x00000100)        /* Bit 0 */
04407 #define  FSMC_BWTR3_DATAST_1                 ((u32)0x00000200)        /* Bit 1 */
04408 #define  FSMC_BWTR3_DATAST_2                 ((u32)0x00000400)        /* Bit 2 */
04409 #define  FSMC_BWTR3_DATAST_3                 ((u32)0x00000800)        /* Bit 3 */
04410
04411 #define  FSMC_BWTR3_BUSTURN                  ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04412 #define  FSMC_BWTR3_BUSTURN_0                ((u32)0x00010000)        /* Bit 0 */
04413 #define  FSMC_BWTR3_BUSTURN_1                ((u32)0x00020000)        /* Bit 1 */
04414 #define  FSMC_BWTR3_BUSTURN_2                ((u32)0x00040000)        /* Bit 2 */
04415 #define  FSMC_BWTR3_BUSTURN_3                ((u32)0x00080000)        /* Bit 3 */
04416
04417 #define  FSMC_BWTR3_CLKDIV                   ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04418 #define  FSMC_BWTR3_CLKDIV_0                 ((u32)0x00100000)        /* Bit 0 */
04419 #define  FSMC_BWTR3_CLKDIV_1                 ((u32)0x00200000)        /* Bit 1 */
04420 #define  FSMC_BWTR3_CLKDIV_2                 ((u32)0x00400000)        /* Bit 2 */
04421 #define  FSMC_BWTR3_CLKDIV_3                 ((u32)0x00800000)        /* Bit 3 */
04422
04423 #define  FSMC_BWTR3_DATLAT                   ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04424 #define  FSMC_BWTR3_DATLAT_0                 ((u32)0x01000000)        /* Bit 0 */
04425 #define  FSMC_BWTR3_DATLAT_1                 ((u32)0x02000000)        /* Bit 1 */
04426 #define  FSMC_BWTR3_DATLAT_2                 ((u32)0x04000000)        /* Bit 2 */
04427 #define  FSMC_BWTR3_DATLAT_3                 ((u32)0x08000000)        /* Bit 3 */
04428
04429 #define  FSMC_BWTR3_ACCMOD                   ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04430 #define  FSMC_BWTR3_ACCMOD_0                 ((u32)0x10000000)        /* Bit 0 */
04431 #define  FSMC_BWTR3_ACCMOD_1                 ((u32)0x20000000)        /* Bit 1 */
04432
04433
04434 /******************  Bit definition for FSMC_BWTR4 register  ******************/
04435 #define  FSMC_BWTR4_ADDSET                   ((u32)0x0000000F)        /* ADDSET[3:0] bits (Address setup phase duration) */
04436 #define  FSMC_BWTR4_ADDSET_0                 ((u32)0x00000001)        /* Bit 0 */
04437 #define  FSMC_BWTR4_ADDSET_1                 ((u32)0x00000002)        /* Bit 1 */
04438 #define  FSMC_BWTR4_ADDSET_2                 ((u32)0x00000004)        /* Bit 2 */
04439 #define  FSMC_BWTR4_ADDSET_3                 ((u32)0x00000008)        /* Bit 3 */
04440
04441 #define  FSMC_BWTR4_ADDHLD                   ((u32)0x000000F0)        /* ADDHLD[3:0] bits (Address-hold phase duration) */
04442 #define  FSMC_BWTR4_ADDHLD_0                 ((u32)0x00000010)        /* Bit 0 */
04443 #define  FSMC_BWTR4_ADDHLD_1                 ((u32)0x00000020)        /* Bit 1 */
04444 #define  FSMC_BWTR4_ADDHLD_2                 ((u32)0x00000040)        /* Bit 2 */
04445 #define  FSMC_BWTR4_ADDHLD_3                 ((u32)0x00000080)        /* Bit 3 */
04446
04447 #define  FSMC_BWTR4_DATAST                   ((u32)0x0000FF00)        /* DATAST [3:0] bits (Data-phase duration) */
04448 #define  FSMC_BWTR4_DATAST_0                 ((u32)0x00000100)        /* Bit 0 */
04449 #define  FSMC_BWTR4_DATAST_1                 ((u32)0x00000200)        /* Bit 1 */
04450 #define  FSMC_BWTR4_DATAST_2                 ((u32)0x00000400)        /* Bit 2 */
04451 #define  FSMC_BWTR4_DATAST_3                 ((u32)0x00000800)        /* Bit 3 */
04452
04453 #define  FSMC_BWTR4_BUSTURN                  ((u32)0x000F0000)        /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
04454 #define  FSMC_BWTR4_BUSTURN_0                ((u32)0x00010000)        /* Bit 0 */
04455 #define  FSMC_BWTR4_BUSTURN_1                ((u32)0x00020000)        /* Bit 1 */
04456 #define  FSMC_BWTR4_BUSTURN_2                ((u32)0x00040000)        /* Bit 2 */
04457 #define  FSMC_BWTR4_BUSTURN_3                ((u32)0x00080000)        /* Bit 3 */
04458
04459 #define  FSMC_BWTR4_CLKDIV                   ((u32)0x00F00000)        /* CLKDIV[3:0] bits (Clock divide ratio) */
04460 #define  FSMC_BWTR4_CLKDIV_0                 ((u32)0x00100000)        /* Bit 0 */
04461 #define  FSMC_BWTR4_CLKDIV_1                 ((u32)0x00200000)        /* Bit 1 */
04462 #define  FSMC_BWTR4_CLKDIV_2                 ((u32)0x00400000)        /* Bit 2 */
04463 #define  FSMC_BWTR4_CLKDIV_3                 ((u32)0x00800000)        /* Bit 3 */
04464
04465 #define  FSMC_BWTR4_DATLAT                   ((u32)0x0F000000)        /* DATLA[3:0] bits (Data latency) */
04466 #define  FSMC_BWTR4_DATLAT_0                 ((u32)0x01000000)        /* Bit 0 */
04467 #define  FSMC_BWTR4_DATLAT_1                 ((u32)0x02000000)        /* Bit 1 */
04468 #define  FSMC_BWTR4_DATLAT_2                 ((u32)0x04000000)        /* Bit 2 */
04469 #define  FSMC_BWTR4_DATLAT_3                 ((u32)0x08000000)        /* Bit 3 */
04470
04471 #define  FSMC_BWTR4_ACCMOD                   ((u32)0x30000000)        /* ACCMOD[1:0] bits (Access mode) */
04472 #define  FSMC_BWTR4_ACCMOD_0                 ((u32)0x10000000)        /* Bit 0 */
04473 #define  FSMC_BWTR4_ACCMOD_1                 ((u32)0x20000000)        /* Bit 1 */
04474
04475
04476 /******************  Bit definition for FSMC_PCR2 register  *******************/
04477 #define  FSMC_PCR2_PWAITEN                   ((u32)0x00000002)        /* Wait feature enable bit */
04478 #define  FSMC_PCR2_PBKEN                     ((u32)0x00000004)        /* PC Card/NAND Flash memory bank enable bit */
04479 #define  FSMC_PCR2_PTYP                      ((u32)0x00000008)        /* Memory type */
04480
04481 #define  FSMC_PCR2_PWID                      ((u32)0x00000030)        /* PWID[1:0] bits (NAND Flash databus width) */
04482 #define  FSMC_PCR2_PWID_0                    ((u32)0x00000010)        /* Bit 0 */
04483 #define  FSMC_PCR2_PWID_1                    ((u32)0x00000020)        /* Bit 1 */
04484
04485 #define  FSMC_PCR2_ECCEN                     ((u32)0x00000040)        /* ECC computation logic enable bit */
04486 #define  FSMC_PCR2_ADLOW                     ((u32)0x00000100)        /* Address low bit delivery */
04487
04488 #define  FSMC_PCR2_TCLR                      ((u32)0x00001E00)        /* TCLR[3:0] bits (CLE to RE delay) */
04489 #define  FSMC_PCR2_TCLR_0                    ((u32)0x00000200)        /* Bit 0 */
04490 #define  FSMC_PCR2_TCLR_1                    ((u32)0x00000400)        /* Bit 1 */
04491 #define  FSMC_PCR2_TCLR_2                    ((u32)0x00000800)        /* Bit 2 */
04492 #define  FSMC_PCR2_TCLR_3                    ((u32)0x00001000)        /* Bit 3 */
04493
04494 #define  FSMC_PCR2_TAR                       ((u32)0x0001E000)        /* TAR[3:0] bits (ALE to RE delay) */
04495 #define  FSMC_PCR2_TAR_0                     ((u32)0x00002000)        /* Bit 0 */
04496 #define  FSMC_PCR2_TAR_1                     ((u32)0x00004000)        /* Bit 1 */
04497 #define  FSMC_PCR2_TAR_2                     ((u32)0x00008000)        /* Bit 2 */
04498 #define  FSMC_PCR2_TAR_3                     ((u32)0x00010000)        /* Bit 3 */
04499
04500 #define  FSMC_PCR2_ECCPS                     ((u32)0x000E0000)        /* ECCPS[1:0] bits (ECC page size) */
04501 #define  FSMC_PCR2_ECCPS_0                   ((u32)0x00020000)        /* Bit 0 */
04502 #define  FSMC_PCR2_ECCPS_1                   ((u32)0x00040000)        /* Bit 1 */
04503 #define  FSMC_PCR2_ECCPS_2                   ((u32)0x00080000)        /* Bit 2 */
04504
04505
04506 /******************  Bit definition for FSMC_PCR3 register  *******************/
04507 #define  FSMC_PCR3_PWAITEN                   ((u32)0x00000002)        /* Wait feature enable bit */
04508 #define  FSMC_PCR3_PBKEN                     ((u32)0x00000004)        /* PC Card/NAND Flash memory bank enable bit */
04509 #define  FSMC_PCR3_PTYP                      ((u32)0x00000008)        /* Memory type */
04510
04511 #define  FSMC_PCR3_PWID                      ((u32)0x00000030)        /* PWID[1:0] bits (NAND Flash databus width) */
04512 #define  FSMC_PCR3_PWID_0                    ((u32)0x00000010)        /* Bit 0 */
04513 #define  FSMC_PCR3_PWID_1                    ((u32)0x00000020)        /* Bit 1 */
04514
04515 #define  FSMC_PCR3_ECCEN                     ((u32)0x00000040)        /* ECC computation logic enable bit */
04516 #define  FSMC_PCR3_ADLOW                     ((u32)0x00000100)        /* Address low bit delivery */
04517
04518 #define  FSMC_PCR3_TCLR                      ((u32)0x00001E00)        /* TCLR[3:0] bits (CLE to RE delay) */
04519 #define  FSMC_PCR3_TCLR_0                    ((u32)0x00000200)        /* Bit 0 */
04520 #define  FSMC_PCR3_TCLR_1                    ((u32)0x00000400)        /* Bit 1 */
04521 #define  FSMC_PCR3_TCLR_2                    ((u32)0x00000800)        /* Bit 2 */
04522 #define  FSMC_PCR3_TCLR_3                    ((u32)0x00001000)        /* Bit 3 */
04523
04524 #define  FSMC_PCR3_TAR                       ((u32)0x0001E000)        /* TAR[3:0] bits (ALE to RE delay) */
04525 #define  FSMC_PCR3_TAR_0                     ((u32)0x00002000)        /* Bit 0 */
04526 #define  FSMC_PCR3_TAR_1                     ((u32)0x00004000)        /* Bit 1 */
04527 #define  FSMC_PCR3_TAR_2                     ((u32)0x00008000)        /* Bit 2 */
04528 #define  FSMC_PCR3_TAR_3                     ((u32)0x00010000)        /* Bit 3 */
04529
04530 #define  FSMC_PCR3_ECCPS                     ((u32)0x000E0000)        /* ECCPS[2:0] bits (ECC page size) */
04531 #define  FSMC_PCR3_ECCPS_0                   ((u32)0x00020000)        /* Bit 0 */
04532 #define  FSMC_PCR3_ECCPS_1                   ((u32)0x00040000)        /* Bit 1 */
04533 #define  FSMC_PCR3_ECCPS_2                   ((u32)0x00080000)        /* Bit 2 */
04534
04535
04536 /******************  Bit definition for FSMC_PCR4 register  *******************/
04537 #define  FSMC_PCR4_PWAITEN                   ((u32)0x00000002)        /* Wait feature enable bit */
04538 #define  FSMC_PCR4_PBKEN                     ((u32)0x00000004)        /* PC Card/NAND Flash memory bank enable bit */
04539 #define  FSMC_PCR4_PTYP                      ((u32)0x00000008)        /* Memory type */
04540
04541 #define  FSMC_PCR4_PWID                      ((u32)0x00000030)        /* PWID[1:0] bits (NAND Flash databus width) */
04542 #define  FSMC_PCR4_PWID_0                    ((u32)0x00000010)        /* Bit 0 */
04543 #define  FSMC_PCR4_PWID_1                    ((u32)0x00000020)        /* Bit 1 */
04544
04545 #define  FSMC_PCR4_ECCEN                     ((u32)0x00000040)        /* ECC computation logic enable bit */
04546 #define  FSMC_PCR4_ADLOW                     ((u32)0x00000100)        /* Address low bit delivery */
04547
04548 #define  FSMC_PCR4_TCLR                      ((u32)0x00001E00)        /* TCLR[3:0] bits (CLE to RE delay) */
04549 #define  FSMC_PCR4_TCLR_0                    ((u32)0x00000200)        /* Bit 0 */
04550 #define  FSMC_PCR4_TCLR_1                    ((u32)0x00000400)        /* Bit 1 */
04551 #define  FSMC_PCR4_TCLR_2                    ((u32)0x00000800)        /* Bit 2 */
04552 #define  FSMC_PCR4_TCLR_3                    ((u32)0x00001000)        /* Bit 3 */
04553
04554 #define  FSMC_PCR4_TAR                       ((u32)0x0001E000)        /* TAR[3:0] bits (ALE to RE delay) */
04555 #define  FSMC_PCR4_TAR_0                     ((u32)0x00002000)        /* Bit 0 */
04556 #define  FSMC_PCR4_TAR_1                     ((u32)0x00004000)        /* Bit 1 */
04557 #define  FSMC_PCR4_TAR_2                     ((u32)0x00008000)        /* Bit 2 */
04558 #define  FSMC_PCR4_TAR_3                     ((u32)0x00010000)        /* Bit 3 */
04559
04560 #define  FSMC_PCR4_ECCPS                     ((u32)0x000E0000)        /* ECCPS[2:0] bits (ECC page size) */
04561 #define  FSMC_PCR4_ECCPS_0                   ((u32)0x00020000)        /* Bit 0 */
04562 #define  FSMC_PCR4_ECCPS_1                   ((u32)0x00040000)        /* Bit 1 */
04563 #define  FSMC_PCR4_ECCPS_2                   ((u32)0x00080000)        /* Bit 2 */
04564
04565
04566 /*******************  Bit definition for FSMC_SR2 register  *******************/
04567 #define  FSMC_SR2_IRS                        ((u8)0x01)               /* Interrupt Rising Edge status */
04568 #define  FSMC_SR2_ILS                        ((u8)0x02)               /* Interrupt Level status */
04569 #define  FSMC_SR2_IFS                        ((u8)0x04)               /* Interrupt Falling Edge status */
04570 #define  FSMC_SR2_IREN                       ((u8)0x08)               /* Interrupt Rising Edge detection Enable bit */
04571 #define  FSMC_SR2_ILEN                       ((u8)0x10)               /* Interrupt Level detection Enable bit */
04572 #define  FSMC_SR2_IFEN                       ((u8)0x20)               /* Interrupt Falling Edge detection Enable bit */
04573 #define  FSMC_SR2_FEMPT                      ((u8)0x40)               /* FIFO empty */
04574
04575
04576 /*******************  Bit definition for FSMC_SR3 register  *******************/
04577 #define  FSMC_SR3_IRS                        ((u8)0x01)               /* Interrupt Rising Edge status */
04578 #define  FSMC_SR3_ILS                        ((u8)0x02)               /* Interrupt Level status */
04579 #define  FSMC_SR3_IFS                        ((u8)0x04)               /* Interrupt Falling Edge status */
04580 #define  FSMC_SR3_IREN                       ((u8)0x08)               /* Interrupt Rising Edge detection Enable bit */
04581 #define  FSMC_SR3_ILEN                       ((u8)0x10)               /* Interrupt Level detection Enable bit */
04582 #define  FSMC_SR3_IFEN                       ((u8)0x20)               /* Interrupt Falling Edge detection Enable bit */
04583 #define  FSMC_SR3_FEMPT                      ((u8)0x40)               /* FIFO empty */
04584
04585
04586 /*******************  Bit definition for FSMC_SR4 register  *******************/
04587 #define  FSMC_SR4_IRS                        ((u8)0x01)               /* Interrupt Rising Edge status */
04588 #define  FSMC_SR4_ILS                        ((u8)0x02)               /* Interrupt Level status */
04589 #define  FSMC_SR4_IFS                        ((u8)0x04)               /* Interrupt Falling Edge status */
04590 #define  FSMC_SR4_IREN                       ((u8)0x08)               /* Interrupt Rising Edge detection Enable bit */
04591 #define  FSMC_SR4_ILEN                       ((u8)0x10)               /* Interrupt Level detection Enable bit */
04592 #define  FSMC_SR4_IFEN                       ((u8)0x20)               /* Interrupt Falling Edge detection Enable bit */
04593 #define  FSMC_SR4_FEMPT                      ((u8)0x40)               /* FIFO empty */
04594
04595
04596 /******************  Bit definition for FSMC_PMEM2 register  ******************/
04597 #define  FSMC_PMEM2_MEMSET2                  ((u32)0x000000FF)        /* MEMSET2[7:0] bits (Common memory 2 setup time) */
04598 #define  FSMC_PMEM2_MEMSET2_0                ((u32)0x00000001)        /* Bit 0 */
04599 #define  FSMC_PMEM2_MEMSET2_1                ((u32)0x00000002)        /* Bit 1 */
04600 #define  FSMC_PMEM2_MEMSET2_2                ((u32)0x00000004)        /* Bit 2 */
04601 #define  FSMC_PMEM2_MEMSET2_3                ((u32)0x00000008)        /* Bit 3 */
04602 #define  FSMC_PMEM2_MEMSET2_4                ((u32)0x00000010)        /* Bit 4 */
04603 #define  FSMC_PMEM2_MEMSET2_5                ((u32)0x00000020)        /* Bit 5 */
04604 #define  FSMC_PMEM2_MEMSET2_6                ((u32)0x00000040)        /* Bit 6 */
04605 #define  FSMC_PMEM2_MEMSET2_7                ((u32)0x00000080)        /* Bit 7 */
04606
04607 #define  FSMC_PMEM2_MEMWAIT2                 ((u32)0x0000FF00)        /* MEMWAIT2[7:0] bits (Common memory 2 wait time) */
04608 #define  FSMC_PMEM2_MEMWAIT2_0               ((u32)0x00000100)        /* Bit 0 */
04609 #define  FSMC_PMEM2_MEMWAIT2_1               ((u32)0x00000200)        /* Bit 1 */
04610 #define  FSMC_PMEM2_MEMWAIT2_2               ((u32)0x00000400)        /* Bit 2 */
04611 #define  FSMC_PMEM2_MEMWAIT2_3               ((u32)0x00000800)        /* Bit 3 */
04612 #define  FSMC_PMEM2_MEMWAIT2_4               ((u32)0x00001000)        /* Bit 4 */
04613 #define  FSMC_PMEM2_MEMWAIT2_5               ((u32)0x00002000)        /* Bit 5 */
04614 #define  FSMC_PMEM2_MEMWAIT2_6               ((u32)0x00004000)        /* Bit 6 */
04615 #define  FSMC_PMEM2_MEMWAIT2_7               ((u32)0x00008000)        /* Bit 7 */
04616
04617 #define  FSMC_PMEM2_MEMHOLD2                 ((u32)0x00FF0000)        /* MEMHOLD2[7:0] bits (Common memory 2 hold time) */
04618 #define  FSMC_PMEM2_MEMHOLD2_0               ((u32)0x00010000)        /* Bit 0 */
04619 #define  FSMC_PMEM2_MEMHOLD2_1               ((u32)0x00020000)        /* Bit 1 */
04620 #define  FSMC_PMEM2_MEMHOLD2_2               ((u32)0x00040000)        /* Bit 2 */
04621 #define  FSMC_PMEM2_MEMHOLD2_3               ((u32)0x00080000)        /* Bit 3 */
04622 #define  FSMC_PMEM2_MEMHOLD2_4               ((u32)0x00100000)        /* Bit 4 */
04623 #define  FSMC_PMEM2_MEMHOLD2_5               ((u32)0x00200000)        /* Bit 5 */
04624 #define  FSMC_PMEM2_MEMHOLD2_6               ((u32)0x00400000)        /* Bit 6 */
04625 #define  FSMC_PMEM2_MEMHOLD2_7               ((u32)0x00800000)        /* Bit 7 */
04626
04627 #define  FSMC_PMEM2_MEMHIZ2                  ((u32)0xFF000000)        /* MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
04628 #define  FSMC_PMEM2_MEMHIZ2_0                ((u32)0x01000000)        /* Bit 0 */
04629 #define  FSMC_PMEM2_MEMHIZ2_1                ((u32)0x02000000)        /* Bit 1 */
04630 #define  FSMC_PMEM2_MEMHIZ2_2                ((u32)0x04000000)        /* Bit 2 */
04631 #define  FSMC_PMEM2_MEMHIZ2_3                ((u32)0x08000000)        /* Bit 3 */
04632 #define  FSMC_PMEM2_MEMHIZ2_4                ((u32)0x10000000)        /* Bit 4 */
04633 #define  FSMC_PMEM2_MEMHIZ2_5                ((u32)0x20000000)        /* Bit 5 */
04634 #define  FSMC_PMEM2_MEMHIZ2_6                ((u32)0x40000000)        /* Bit 6 */
04635 #define  FSMC_PMEM2_MEMHIZ2_7                ((u32)0x80000000)        /* Bit 7 */
04636
04637
04638 /******************  Bit definition for FSMC_PMEM3 register  ******************/
04639 #define  FSMC_PMEM3_MEMSET3                  ((u32)0x000000FF)        /* MEMSET3[7:0] bits (Common memory 3 setup time) */
04640 #define  FSMC_PMEM3_MEMSET3_0                ((u32)0x00000001)        /* Bit 0 */
04641 #define  FSMC_PMEM3_MEMSET3_1                ((u32)0x00000002)        /* Bit 1 */
04642 #define  FSMC_PMEM3_MEMSET3_2                ((u32)0x00000004)        /* Bit 2 */
04643 #define  FSMC_PMEM3_MEMSET3_3                ((u32)0x00000008)        /* Bit 3 */
04644 #define  FSMC_PMEM3_MEMSET3_4                ((u32)0x00000010)        /* Bit 4 */
04645 #define  FSMC_PMEM3_MEMSET3_5                ((u32)0x00000020)        /* Bit 5 */
04646 #define  FSMC_PMEM3_MEMSET3_6                ((u32)0x00000040)        /* Bit 6 */
04647 #define  FSMC_PMEM3_MEMSET3_7                ((u32)0x00000080)        /* Bit 7 */
04648
04649 #define  FSMC_PMEM3_MEMWAIT3                 ((u32)0x0000FF00)        /* MEMWAIT3[7:0] bits (Common memory 3 wait time) */
04650 #define  FSMC_PMEM3_MEMWAIT3_0               ((u32)0x00000100)        /* Bit 0 */
04651 #define  FSMC_PMEM3_MEMWAIT3_1               ((u32)0x00000200)        /* Bit 1 */
04652 #define  FSMC_PMEM3_MEMWAIT3_2               ((u32)0x00000400)        /* Bit 2 */
04653 #define  FSMC_PMEM3_MEMWAIT3_3               ((u32)0x00000800)        /* Bit 3 */
04654 #define  FSMC_PMEM3_MEMWAIT3_4               ((u32)0x00001000)        /* Bit 4 */
04655 #define  FSMC_PMEM3_MEMWAIT3_5               ((u32)0x00002000)        /* Bit 5 */
04656 #define  FSMC_PMEM3_MEMWAIT3_6               ((u32)0x00004000)        /* Bit 6 */
04657 #define  FSMC_PMEM3_MEMWAIT3_7               ((u32)0x00008000)        /* Bit 7 */
04658
04659 #define  FSMC_PMEM3_MEMHOLD3                 ((u32)0x00FF0000)        /* MEMHOLD3[7:0] bits (Common memory 3 hold time) */
04660 #define  FSMC_PMEM3_MEMHOLD3_0               ((u32)0x00010000)        /* Bit 0 */
04661 #define  FSMC_PMEM3_MEMHOLD3_1               ((u32)0x00020000)        /* Bit 1 */
04662 #define  FSMC_PMEM3_MEMHOLD3_2               ((u32)0x00040000)        /* Bit 2 */
04663 #define  FSMC_PMEM3_MEMHOLD3_3               ((u32)0x00080000)        /* Bit 3 */
04664 #define  FSMC_PMEM3_MEMHOLD3_4               ((u32)0x00100000)        /* Bit 4 */
04665 #define  FSMC_PMEM3_MEMHOLD3_5               ((u32)0x00200000)        /* Bit 5 */
04666 #define  FSMC_PMEM3_MEMHOLD3_6               ((u32)0x00400000)        /* Bit 6 */
04667 #define  FSMC_PMEM3_MEMHOLD3_7               ((u32)0x00800000)        /* Bit 7 */
04668
04669 #define  FSMC_PMEM3_MEMHIZ3                  ((u32)0xFF000000)        /* MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
04670 #define  FSMC_PMEM3_MEMHIZ3_0                ((u32)0x01000000)        /* Bit 0 */
04671 #define  FSMC_PMEM3_MEMHIZ3_1                ((u32)0x02000000)        /* Bit 1 */
04672 #define  FSMC_PMEM3_MEMHIZ3_2                ((u32)0x04000000)        /* Bit 2 */
04673 #define  FSMC_PMEM3_MEMHIZ3_3                ((u32)0x08000000)        /* Bit 3 */
04674 #define  FSMC_PMEM3_MEMHIZ3_4                ((u32)0x10000000)        /* Bit 4 */
04675 #define  FSMC_PMEM3_MEMHIZ3_5                ((u32)0x20000000)        /* Bit 5 */
04676 #define  FSMC_PMEM3_MEMHIZ3_6                ((u32)0x40000000)        /* Bit 6 */
04677 #define  FSMC_PMEM3_MEMHIZ3_7                ((u32)0x80000000)        /* Bit 7 */
04678
04679
04680 /******************  Bit definition for FSMC_PMEM4 register  ******************/
04681 #define  FSMC_PMEM4_MEMSET4                  ((u32)0x000000FF)        /* MEMSET4[7:0] bits (Common memory 4 setup time) */
04682 #define  FSMC_PMEM4_MEMSET4_0                ((u32)0x00000001)        /* Bit 0 */
04683 #define  FSMC_PMEM4_MEMSET4_1                ((u32)0x00000002)        /* Bit 1 */
04684 #define  FSMC_PMEM4_MEMSET4_2                ((u32)0x00000004)        /* Bit 2 */
04685 #define  FSMC_PMEM4_MEMSET4_3                ((u32)0x00000008)        /* Bit 3 */
04686 #define  FSMC_PMEM4_MEMSET4_4                ((u32)0x00000010)        /* Bit 4 */
04687 #define  FSMC_PMEM4_MEMSET4_5                ((u32)0x00000020)        /* Bit 5 */
04688 #define  FSMC_PMEM4_MEMSET4_6                ((u32)0x00000040)        /* Bit 6 */
04689 #define  FSMC_PMEM4_MEMSET4_7                ((u32)0x00000080)        /* Bit 7 */
04690
04691 #define  FSMC_PMEM4_MEMWAIT4                 ((u32)0x0000FF00)        /* MEMWAIT4[7:0] bits (Common memory 4 wait time) */
04692 #define  FSMC_PMEM4_MEMWAIT4_0               ((u32)0x00000100)        /* Bit 0 */
04693 #define  FSMC_PMEM4_MEMWAIT4_1               ((u32)0x00000200)        /* Bit 1 */
04694 #define  FSMC_PMEM4_MEMWAIT4_2               ((u32)0x00000400)        /* Bit 2 */
04695 #define  FSMC_PMEM4_MEMWAIT4_3               ((u32)0x00000800)        /* Bit 3 */
04696 #define  FSMC_PMEM4_MEMWAIT4_4               ((u32)0x00001000)        /* Bit 4 */
04697 #define  FSMC_PMEM4_MEMWAIT4_5               ((u32)0x00002000)        /* Bit 5 */
04698 #define  FSMC_PMEM4_MEMWAIT4_6               ((u32)0x00004000)        /* Bit 6 */
04699 #define  FSMC_PMEM4_MEMWAIT4_7               ((u32)0x00008000)        /* Bit 7 */
04700
04701 #define  FSMC_PMEM4_MEMHOLD4                 ((u32)0x00FF0000)        /* MEMHOLD4[7:0] bits (Common memory 4 hold time) */
04702 #define  FSMC_PMEM4_MEMHOLD4_0               ((u32)0x00010000)        /* Bit 0 */
04703 #define  FSMC_PMEM4_MEMHOLD4_1               ((u32)0x00020000)        /* Bit 1 */
04704 #define  FSMC_PMEM4_MEMHOLD4_2               ((u32)0x00040000)        /* Bit 2 */
04705 #define  FSMC_PMEM4_MEMHOLD4_3               ((u32)0x00080000)        /* Bit 3 */
04706 #define  FSMC_PMEM4_MEMHOLD4_4               ((u32)0x00100000)        /* Bit 4 */
04707 #define  FSMC_PMEM4_MEMHOLD4_5               ((u32)0x00200000)        /* Bit 5 */
04708 #define  FSMC_PMEM4_MEMHOLD4_6               ((u32)0x00400000)        /* Bit 6 */
04709 #define  FSMC_PMEM4_MEMHOLD4_7               ((u32)0x00800000)        /* Bit 7 */
04710
04711 #define  FSMC_PMEM4_MEMHIZ4                  ((u32)0xFF000000)        /* MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
04712 #define  FSMC_PMEM4_MEMHIZ4_0                ((u32)0x01000000)        /* Bit 0 */
04713 #define  FSMC_PMEM4_MEMHIZ4_1                ((u32)0x02000000)        /* Bit 1 */
04714 #define  FSMC_PMEM4_MEMHIZ4_2                ((u32)0x04000000)        /* Bit 2 */
04715 #define  FSMC_PMEM4_MEMHIZ4_3                ((u32)0x08000000)        /* Bit 3 */
04716 #define  FSMC_PMEM4_MEMHIZ4_4                ((u32)0x10000000)        /* Bit 4 */
04717 #define  FSMC_PMEM4_MEMHIZ4_5                ((u32)0x20000000)        /* Bit 5 */
04718 #define  FSMC_PMEM4_MEMHIZ4_6                ((u32)0x40000000)        /* Bit 6 */
04719 #define  FSMC_PMEM4_MEMHIZ4_7                ((u32)0x80000000)        /* Bit 7 */
04720
04721
04722 /******************  Bit definition for FSMC_PATT2 register  ******************/
04723 #define  FSMC_PATT2_ATTSET2                  ((u32)0x000000FF)        /* ATTSET2[7:0] bits (Attribute memory 2 setup time) */
04724 #define  FSMC_PATT2_ATTSET2_0                ((u32)0x00000001)        /* Bit 0 */
04725 #define  FSMC_PATT2_ATTSET2_1                ((u32)0x00000002)        /* Bit 1 */
04726 #define  FSMC_PATT2_ATTSET2_2                ((u32)0x00000004)        /* Bit 2 */
04727 #define  FSMC_PATT2_ATTSET2_3                ((u32)0x00000008)        /* Bit 3 */
04728 #define  FSMC_PATT2_ATTSET2_4                ((u32)0x00000010)        /* Bit 4 */
04729 #define  FSMC_PATT2_ATTSET2_5                ((u32)0x00000020)        /* Bit 5 */
04730 #define  FSMC_PATT2_ATTSET2_6                ((u32)0x00000040)        /* Bit 6 */
04731 #define  FSMC_PATT2_ATTSET2_7                ((u32)0x00000080)        /* Bit 7 */
04732
04733 #define  FSMC_PATT2_ATTWAIT2                 ((u32)0x0000FF00)        /* ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
04734 #define  FSMC_PATT2_ATTWAIT2_0               ((u32)0x00000100)        /* Bit 0 */
04735 #define  FSMC_PATT2_ATTWAIT2_1               ((u32)0x00000200)        /* Bit 1 */
04736 #define  FSMC_PATT2_ATTWAIT2_2               ((u32)0x00000400)        /* Bit 2 */
04737 #define  FSMC_PATT2_ATTWAIT2_3               ((u32)0x00000800)        /* Bit 3 */
04738 #define  FSMC_PATT2_ATTWAIT2_4               ((u32)0x00001000)        /* Bit 4 */
04739 #define  FSMC_PATT2_ATTWAIT2_5               ((u32)0x00002000)        /* Bit 5 */
04740 #define  FSMC_PATT2_ATTWAIT2_6               ((u32)0x00004000)        /* Bit 6 */
04741 #define  FSMC_PATT2_ATTWAIT2_7               ((u32)0x00008000)        /* Bit 7 */
04742
04743 #define  FSMC_PATT2_ATTHOLD2                 ((u32)0x00FF0000)        /* ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
04744 #define  FSMC_PATT2_ATTHOLD2_0               ((u32)0x00010000)        /* Bit 0 */
04745 #define  FSMC_PATT2_ATTHOLD2_1               ((u32)0x00020000)        /* Bit 1 */
04746 #define  FSMC_PATT2_ATTHOLD2_2               ((u32)0x00040000)        /* Bit 2 */
04747 #define  FSMC_PATT2_ATTHOLD2_3               ((u32)0x00080000)        /* Bit 3 */
04748 #define  FSMC_PATT2_ATTHOLD2_4               ((u32)0x00100000)        /* Bit 4 */
04749 #define  FSMC_PATT2_ATTHOLD2_5               ((u32)0x00200000)        /* Bit 5 */
04750 #define  FSMC_PATT2_ATTHOLD2_6               ((u32)0x00400000)        /* Bit 6 */
04751 #define  FSMC_PATT2_ATTHOLD2_7               ((u32)0x00800000)        /* Bit 7 */
04752
04753 #define  FSMC_PATT2_ATTHIZ2                  ((u32)0xFF000000)        /* ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
04754 #define  FSMC_PATT2_ATTHIZ2_0                ((u32)0x01000000)        /* Bit 0 */
04755 #define  FSMC_PATT2_ATTHIZ2_1                ((u32)0x02000000)        /* Bit 1 */
04756 #define  FSMC_PATT2_ATTHIZ2_2                ((u32)0x04000000)        /* Bit 2 */
04757 #define  FSMC_PATT2_ATTHIZ2_3                ((u32)0x08000000)        /* Bit 3 */
04758 #define  FSMC_PATT2_ATTHIZ2_4                ((u32)0x10000000)        /* Bit 4 */
04759 #define  FSMC_PATT2_ATTHIZ2_5                ((u32)0x20000000)        /* Bit 5 */
04760 #define  FSMC_PATT2_ATTHIZ2_6                ((u32)0x40000000)        /* Bit 6 */
04761 #define  FSMC_PATT2_ATTHIZ2_7                ((u32)0x80000000)        /* Bit 7 */
04762
04763
04764 /******************  Bit definition for FSMC_PATT3 register  ******************/
04765 #define  FSMC_PATT3_ATTSET3                  ((u32)0x000000FF)        /* ATTSET3[7:0] bits (Attribute memory 3 setup time) */
04766 #define  FSMC_PATT3_ATTSET3_0                ((u32)0x00000001)        /* Bit 0 */
04767 #define  FSMC_PATT3_ATTSET3_1                ((u32)0x00000002)        /* Bit 1 */
04768 #define  FSMC_PATT3_ATTSET3_2                ((u32)0x00000004)        /* Bit 2 */
04769 #define  FSMC_PATT3_ATTSET3_3                ((u32)0x00000008)        /* Bit 3 */
04770 #define  FSMC_PATT3_ATTSET3_4                ((u32)0x00000010)        /* Bit 4 */
04771 #define  FSMC_PATT3_ATTSET3_5                ((u32)0x00000020)        /* Bit 5 */
04772 #define  FSMC_PATT3_ATTSET3_6                ((u32)0x00000040)        /* Bit 6 */
04773 #define  FSMC_PATT3_ATTSET3_7                ((u32)0x00000080)        /* Bit 7 */
04774
04775 #define  FSMC_PATT3_ATTWAIT3                 ((u32)0x0000FF00)        /* ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
04776 #define  FSMC_PATT3_ATTWAIT3_0               ((u32)0x00000100)        /* Bit 0 */
04777 #define  FSMC_PATT3_ATTWAIT3_1               ((u32)0x00000200)        /* Bit 1 */
04778 #define  FSMC_PATT3_ATTWAIT3_2               ((u32)0x00000400)        /* Bit 2 */
04779 #define  FSMC_PATT3_ATTWAIT3_3               ((u32)0x00000800)        /* Bit 3 */
04780 #define  FSMC_PATT3_ATTWAIT3_4               ((u32)0x00001000)        /* Bit 4 */
04781 #define  FSMC_PATT3_ATTWAIT3_5               ((u32)0x00002000)        /* Bit 5 */
04782 #define  FSMC_PATT3_ATTWAIT3_6               ((u32)0x00004000)        /* Bit 6 */
04783 #define  FSMC_PATT3_ATTWAIT3_7               ((u32)0x00008000)        /* Bit 7 */
04784
04785 #define  FSMC_PATT3_ATTHOLD3                 ((u32)0x00FF0000)        /* ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
04786 #define  FSMC_PATT3_ATTHOLD3_0               ((u32)0x00010000)        /* Bit 0 */
04787 #define  FSMC_PATT3_ATTHOLD3_1               ((u32)0x00020000)        /* Bit 1 */
04788 #define  FSMC_PATT3_ATTHOLD3_2               ((u32)0x00040000)        /* Bit 2 */
04789 #define  FSMC_PATT3_ATTHOLD3_3               ((u32)0x00080000)        /* Bit 3 */
04790 #define  FSMC_PATT3_ATTHOLD3_4               ((u32)0x00100000)        /* Bit 4 */
04791 #define  FSMC_PATT3_ATTHOLD3_5               ((u32)0x00200000)        /* Bit 5 */
04792 #define  FSMC_PATT3_ATTHOLD3_6               ((u32)0x00400000)        /* Bit 6 */
04793 #define  FSMC_PATT3_ATTHOLD3_7               ((u32)0x00800000)        /* Bit 7 */
04794
04795 #define  FSMC_PATT3_ATTHIZ3                  ((u32)0xFF000000)        /* ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
04796 #define  FSMC_PATT3_ATTHIZ3_0                ((u32)0x01000000)        /* Bit 0 */
04797 #define  FSMC_PATT3_ATTHIZ3_1                ((u32)0x02000000)        /* Bit 1 */
04798 #define  FSMC_PATT3_ATTHIZ3_2                ((u32)0x04000000)        /* Bit 2 */
04799 #define  FSMC_PATT3_ATTHIZ3_3                ((u32)0x08000000)        /* Bit 3 */
04800 #define  FSMC_PATT3_ATTHIZ3_4                ((u32)0x10000000)        /* Bit 4 */
04801 #define  FSMC_PATT3_ATTHIZ3_5                ((u32)0x20000000)        /* Bit 5 */
04802 #define  FSMC_PATT3_ATTHIZ3_6                ((u32)0x40000000)        /* Bit 6 */
04803 #define  FSMC_PATT3_ATTHIZ3_7                ((u32)0x80000000)        /* Bit 7 */
04804
04805
04806 /******************  Bit definition for FSMC_PATT4 register  ******************/
04807 #define  FSMC_PATT4_ATTSET4                  ((u32)0x000000FF)        /* ATTSET4[7:0] bits (Attribute memory 4 setup time) */
04808 #define  FSMC_PATT4_ATTSET4_0                ((u32)0x00000001)        /* Bit 0 */
04809 #define  FSMC_PATT4_ATTSET4_1                ((u32)0x00000002)        /* Bit 1 */
04810 #define  FSMC_PATT4_ATTSET4_2                ((u32)0x00000004)        /* Bit 2 */
04811 #define  FSMC_PATT4_ATTSET4_3                ((u32)0x00000008)        /* Bit 3 */
04812 #define  FSMC_PATT4_ATTSET4_4                ((u32)0x00000010)        /* Bit 4 */
04813 #define  FSMC_PATT4_ATTSET4_5                ((u32)0x00000020)        /* Bit 5 */
04814 #define  FSMC_PATT4_ATTSET4_6                ((u32)0x00000040)        /* Bit 6 */
04815 #define  FSMC_PATT4_ATTSET4_7                ((u32)0x00000080)        /* Bit 7 */
04816
04817 #define  FSMC_PATT4_ATTWAIT4                 ((u32)0x0000FF00)        /* ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
04818 #define  FSMC_PATT4_ATTWAIT4_0               ((u32)0x00000100)        /* Bit 0 */
04819 #define  FSMC_PATT4_ATTWAIT4_1               ((u32)0x00000200)        /* Bit 1 */
04820 #define  FSMC_PATT4_ATTWAIT4_2               ((u32)0x00000400)        /* Bit 2 */
04821 #define  FSMC_PATT4_ATTWAIT4_3               ((u32)0x00000800)        /* Bit 3 */
04822 #define  FSMC_PATT4_ATTWAIT4_4               ((u32)0x00001000)        /* Bit 4 */
04823 #define  FSMC_PATT4_ATTWAIT4_5               ((u32)0x00002000)        /* Bit 5 */
04824 #define  FSMC_PATT4_ATTWAIT4_6               ((u32)0x00004000)        /* Bit 6 */
04825 #define  FSMC_PATT4_ATTWAIT4_7               ((u32)0x00008000)        /* Bit 7 */
04826
04827 #define  FSMC_PATT4_ATTHOLD4                 ((u32)0x00FF0000)        /* ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
04828 #define  FSMC_PATT4_ATTHOLD4_0               ((u32)0x00010000)        /* Bit 0 */
04829 #define  FSMC_PATT4_ATTHOLD4_1               ((u32)0x00020000)        /* Bit 1 */
04830 #define  FSMC_PATT4_ATTHOLD4_2               ((u32)0x00040000)        /* Bit 2 */
04831 #define  FSMC_PATT4_ATTHOLD4_3               ((u32)0x00080000)        /* Bit 3 */
04832 #define  FSMC_PATT4_ATTHOLD4_4               ((u32)0x00100000)        /* Bit 4 */
04833 #define  FSMC_PATT4_ATTHOLD4_5               ((u32)0x00200000)        /* Bit 5 */
04834 #define  FSMC_PATT4_ATTHOLD4_6               ((u32)0x00400000)        /* Bit 6 */
04835 #define  FSMC_PATT4_ATTHOLD4_7               ((u32)0x00800000)        /* Bit 7 */
04836
04837 #define  FSMC_PATT4_ATTHIZ4                  ((u32)0xFF000000)        /* ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
04838 #define  FSMC_PATT4_ATTHIZ4_0                ((u32)0x01000000)        /* Bit 0 */
04839 #define  FSMC_PATT4_ATTHIZ4_1                ((u32)0x02000000)        /* Bit 1 */
04840 #define  FSMC_PATT4_ATTHIZ4_2                ((u32)0x04000000)        /* Bit 2 */
04841 #define  FSMC_PATT4_ATTHIZ4_3                ((u32)0x08000000)        /* Bit 3 */
04842 #define  FSMC_PATT4_ATTHIZ4_4                ((u32)0x10000000)        /* Bit 4 */
04843 #define  FSMC_PATT4_ATTHIZ4_5                ((u32)0x20000000)        /* Bit 5 */
04844 #define  FSMC_PATT4_ATTHIZ4_6                ((u32)0x40000000)        /* Bit 6 */
04845 #define  FSMC_PATT4_ATTHIZ4_7                ((u32)0x80000000)        /* Bit 7 */
04846
04847
04848 /******************  Bit definition for FSMC_PIO4 register  *******************/
04849 #define  FSMC_PIO4_IOSET4                    ((u32)0x000000FF)        /* IOSET4[7:0] bits (I/O 4 setup time) */
04850 #define  FSMC_PIO4_IOSET4_0                  ((u32)0x00000001)        /* Bit 0 */
04851 #define  FSMC_PIO4_IOSET4_1                  ((u32)0x00000002)        /* Bit 1 */
04852 #define  FSMC_PIO4_IOSET4_2                  ((u32)0x00000004)        /* Bit 2 */
04853 #define  FSMC_PIO4_IOSET4_3                  ((u32)0x00000008)        /* Bit 3 */
04854 #define  FSMC_PIO4_IOSET4_4                  ((u32)0x00000010)        /* Bit 4 */
04855 #define  FSMC_PIO4_IOSET4_5                  ((u32)0x00000020)        /* Bit 5 */
04856 #define  FSMC_PIO4_IOSET4_6                  ((u32)0x00000040)        /* Bit 6 */
04857 #define  FSMC_PIO4_IOSET4_7                  ((u32)0x00000080)        /* Bit 7 */
04858
04859 #define  FSMC_PIO4_IOWAIT4                   ((u32)0x0000FF00)        /* IOWAIT4[7:0] bits (I/O 4 wait time) */
04860 #define  FSMC_PIO4_IOWAIT4_0                 ((u32)0x00000100)        /* Bit 0 */
04861 #define  FSMC_PIO4_IOWAIT4_1                 ((u32)0x00000200)        /* Bit 1 */
04862 #define  FSMC_PIO4_IOWAIT4_2                 ((u32)0x00000400)        /* Bit 2 */
04863 #define  FSMC_PIO4_IOWAIT4_3                 ((u32)0x00000800)        /* Bit 3 */
04864 #define  FSMC_PIO4_IOWAIT4_4                 ((u32)0x00001000)        /* Bit 4 */
04865 #define  FSMC_PIO4_IOWAIT4_5                 ((u32)0x00002000)        /* Bit 5 */
04866 #define  FSMC_PIO4_IOWAIT4_6                 ((u32)0x00004000)        /* Bit 6 */
04867 #define  FSMC_PIO4_IOWAIT4_7                 ((u32)0x00008000)        /* Bit 7 */
04868
04869 #define  FSMC_PIO4_IOHOLD4                   ((u32)0x00FF0000)        /* IOHOLD4[7:0] bits (I/O 4 hold time) */
04870 #define  FSMC_PIO4_IOHOLD4_0                 ((u32)0x00010000)        /* Bit 0 */
04871 #define  FSMC_PIO4_IOHOLD4_1                 ((u32)0x00020000)        /* Bit 1 */
04872 #define  FSMC_PIO4_IOHOLD4_2                 ((u32)0x00040000)        /* Bit 2 */
04873 #define  FSMC_PIO4_IOHOLD4_3                 ((u32)0x00080000)        /* Bit 3 */
04874 #define  FSMC_PIO4_IOHOLD4_4                 ((u32)0x00100000)        /* Bit 4 */
04875 #define  FSMC_PIO4_IOHOLD4_5                 ((u32)0x00200000)        /* Bit 5 */
04876 #define  FSMC_PIO4_IOHOLD4_6                 ((u32)0x00400000)        /* Bit 6 */
04877 #define  FSMC_PIO4_IOHOLD4_7                 ((u32)0x00800000)        /* Bit 7 */
04878
04879 #define  FSMC_PIO4_IOHIZ4                    ((u32)0xFF000000)        /* IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
04880 #define  FSMC_PIO4_IOHIZ4_0                  ((u32)0x01000000)        /* Bit 0 */
04881 #define  FSMC_PIO4_IOHIZ4_1                  ((u32)0x02000000)        /* Bit 1 */
04882 #define  FSMC_PIO4_IOHIZ4_2                  ((u32)0x04000000)        /* Bit 2 */
04883 #define  FSMC_PIO4_IOHIZ4_3                  ((u32)0x08000000)        /* Bit 3 */
04884 #define  FSMC_PIO4_IOHIZ4_4                  ((u32)0x10000000)        /* Bit 4 */
04885 #define  FSMC_PIO4_IOHIZ4_5                  ((u32)0x20000000)        /* Bit 5 */
04886 #define  FSMC_PIO4_IOHIZ4_6                  ((u32)0x40000000)        /* Bit 6 */
04887 #define  FSMC_PIO4_IOHIZ4_7                  ((u32)0x80000000)        /* Bit 7 */
04888
04889
04890 /******************  Bit definition for FSMC_ECCR2 register  ******************/
04891 #define  FSMC_ECCR2_ECC2                     ((u32)0xFFFFFFFF)        /* ECC result */
04892
04893 /******************  Bit definition for FSMC_ECCR3 register  ******************/
04894 #define  FSMC_ECCR3_ECC3                     ((u32)0xFFFFFFFF)        /* ECC result */
04895
04896
04897
04898 /******************************************************************************/
04899 /*                                                                            */
04900 /*                           SD host Interface                                */
04901 /*                                                                            */
04902 /******************************************************************************/
04903
04904 /******************  Bit definition for SDIO_POWER register  ******************/
04905 #define  SDIO_POWER_PWRCTRL                  ((u8)0x03)               /* PWRCTRL[1:0] bits (Power supply control bits) */
04906 #define  SDIO_POWER_PWRCTRL_0                ((u8)0x01)               /* Bit 0 */
04907 #define  SDIO_POWER_PWRCTRL_1                ((u8)0x02)               /* Bit 1 */
04908
04909
04910 /******************  Bit definition for SDIO_CLKCR register  ******************/
04911 #define  SDIO_CLKCR_CLKDIV                   ((u16)0x00FF)            /* Clock divide factor */
04912 #define  SDIO_CLKCR_CLKEN                    ((u16)0x0100)            /* Clock enable bit */
04913 #define  SDIO_CLKCR_PWRSAV                   ((u16)0x0200)            /* Power saving configuration bit */
04914 #define  SDIO_CLKCR_BYPASS                   ((u16)0x0400)            /* Clock divider bypass enable bit */
04915
04916 #define  SDIO_CLKCR_WIDBUS                   ((u16)0x1800)            /* WIDBUS[1:0] bits (Wide bus mode enable bit) */
04917 #define  SDIO_CLKCR_WIDBUS_0                 ((u16)0x0800)            /* Bit 0 */
04918 #define  SDIO_CLKCR_WIDBUS_1                 ((u16)0x1000)            /* Bit 1 */
04919
04920 #define  SDIO_CLKCR_NEGEDGE                  ((u16)0x2000)            /* SDIO_CK dephasing selection bit */
04921 #define  SDIO_CLKCR_HWFC_EN                  ((u16)0x4000)            /* HW Flow Control enable */
04922
04923
04924 /*******************  Bit definition for SDIO_ARG register  *******************/
04925 #define  SDIO_ARG_CMDARG                     ((u32)0xFFFFFFFF)            /* Command argument */
04926
04927
04928 /*******************  Bit definition for SDIO_CMD register  *******************/
04929 #define  SDIO_CMD_CMDINDEX                   ((u16)0x003F)            /* Command Index */
04930
04931 #define  SDIO_CMD_WAITRESP                   ((u16)0x00C0)            /* WAITRESP[1:0] bits (Wait for response bits) */
04932 #define  SDIO_CMD_WAITRESP_0                 ((u16)0x0040)            /*  Bit 0 */
04933 #define  SDIO_CMD_WAITRESP_1                 ((u16)0x0080)            /*  Bit 1 */
04934
04935 #define  SDIO_CMD_WAITINT                    ((u16)0x0100)            /* CPSM Waits for Interrupt Request */
04936 #define  SDIO_CMD_WAITPEND                   ((u16)0x0200)            /* CPSM Waits for ends of data transfer (CmdPend internal signal) */
04937 #define  SDIO_CMD_CPSMEN                     ((u16)0x0400)            /* Command path state machine (CPSM) Enable bit */
04938 #define  SDIO_CMD_SDIOSUSPEND                ((u16)0x0800)            /* SD I/O suspend command */
04939 #define  SDIO_CMD_ENCMDCOMPL                 ((u16)0x1000)            /* Enable CMD completion */
04940 #define  SDIO_CMD_NIEN                       ((u16)0x2000)            /* Not Interrupt Enable */
04941 #define  SDIO_CMD_CEATACMD                   ((u16)0x4000)            /* CE-ATA command */
04942
04943
04944 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
04945 #define  SDIO_RESPCMD_RESPCMD                ((u8)0x3F)               /* Response command index */
04946
04947
04948 /******************  Bit definition for SDIO_RESP0 register  ******************/
04949 #define  SDIO_RESP0_CARDSTATUS0              ((u32)0xFFFFFFFF)        /* Card Status */
04950
04951
04952 /******************  Bit definition for SDIO_RESP1 register  ******************/
04953 #define  SDIO_RESP1_CARDSTATUS1              ((u32)0xFFFFFFFF)        /* Card Status */
04954
04955
04956 /******************  Bit definition for SDIO_RESP2 register  ******************/
04957 #define  SDIO_RESP2_CARDSTATUS2              ((u32)0xFFFFFFFF)        /* Card Status */
04958
04959
04960 /******************  Bit definition for SDIO_RESP3 register  ******************/
04961 #define  SDIO_RESP3_CARDSTATUS3              ((u32)0xFFFFFFFF)        /* Card Status */
04962
04963
04964 /******************  Bit definition for SDIO_RESP4 register  ******************/
04965 #define  SDIO_RESP4_CARDSTATUS4              ((u32)0xFFFFFFFF)        /* Card Status */
04966
04967
04968 /******************  Bit definition for SDIO_DTIMER register  *****************/
04969 #define  SDIO_DTIMER_DATATIME                ((u32)0xFFFFFFFF)        /* Data timeout period. */
04970
04971
04972 /******************  Bit definition for SDIO_DLEN register  *******************/
04973 #define  SDIO_DLEN_DATALENGTH                ((u32)0x01FFFFFF)        /* Data length value */
04974
04975
04976 /******************  Bit definition for SDIO_DCTRL register  ******************/
04977 #define  SDIO_DCTRL_DTEN                     ((u16)0x0001)            /* Data transfer enabled bit */
04978 #define  SDIO_DCTRL_DTDIR                    ((u16)0x0002)            /* Data transfer direction selection */
04979 #define  SDIO_DCTRL_DTMODE                   ((u16)0x0004)            /* Data transfer mode selection */
04980 #define  SDIO_DCTRL_DMAEN                    ((u16)0x0008)            /* DMA enabled bit */
04981
04982 #define  SDIO_DCTRL_DBLOCKSIZE               ((u16)0x00F0)            /* DBLOCKSIZE[3:0] bits (Data block size) */
04983 #define  SDIO_DCTRL_DBLOCKSIZE_0             ((u16)0x0010)            /* Bit 0 */
04984 #define  SDIO_DCTRL_DBLOCKSIZE_1             ((u16)0x0020)            /* Bit 1 */
04985 #define  SDIO_DCTRL_DBLOCKSIZE_2             ((u16)0x0040)            /* Bit 2 */
04986 #define  SDIO_DCTRL_DBLOCKSIZE_3             ((u16)0x0080)            /* Bit 3 */
04987
04988 #define  SDIO_DCTRL_RWSTART                  ((u16)0x0100)            /* Read wait start */
04989 #define  SDIO_DCTRL_RWSTOP                   ((u16)0x0200)            /* Read wait stop */
04990 #define  SDIO_DCTRL_RWMOD                    ((u16)0x0400)            /* Read wait mode */
04991 #define  SDIO_DCTRL_SDIOEN                   ((u16)0x0800)            /* SD I/O enable functions */
04992
04993
04994 /******************  Bit definition for SDIO_DCOUNT register  *****************/
04995 #define  SDIO_DCOUNT_DATACOUNT               ((u32)0x01FFFFFF)        /* Data count value */
04996
04997
04998 /******************  Bit definition for SDIO_STA register  ********************/
04999 #define  SDIO_STA_CCRCFAIL                   ((u32)0x00000001)        /* Command response received (CRC check failed) */
05000 #define  SDIO_STA_DCRCFAIL                   ((u32)0x00000002)        /* Data block sent/received (CRC check failed) */
05001 #define  SDIO_STA_CTIMEOUT                   ((u32)0x00000004)        /* Command response timeout */
05002 #define  SDIO_STA_DTIMEOUT                   ((u32)0x00000008)        /* Data timeout */
05003 #define  SDIO_STA_TXUNDERR                   ((u32)0x00000010)        /* Transmit FIFO underrun error */
05004 #define  SDIO_STA_RXOVERR                    ((u32)0x00000020)        /* Received FIFO overrun error */
05005 #define  SDIO_STA_CMDREND                    ((u32)0x00000040)        /* Command response received (CRC check passed) */
05006 #define  SDIO_STA_CMDSENT                    ((u32)0x00000080)        /* Command sent (no response required) */
05007 #define  SDIO_STA_DATAEND                    ((u32)0x00000100)        /* Data end (data counter, SDIDCOUNT, is zero) */
05008 #define  SDIO_STA_STBITERR                   ((u32)0x00000200)        /* Start bit not detected on all data signals in wide bus mode */
05009 #define  SDIO_STA_DBCKEND                    ((u32)0x00000400)        /* Data block sent/received (CRC check passed) */
05010 #define  SDIO_STA_CMDACT                     ((u32)0x00000800)        /* Command transfer in progress */
05011 #define  SDIO_STA_TXACT                      ((u32)0x00001000)        /* Data transmit in progress */
05012 #define  SDIO_STA_RXACT                      ((u32)0x00002000)        /* Data receive in progress */
05013 #define  SDIO_STA_TXFIFOHE                   ((u32)0x00004000)        /* Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
05014 #define  SDIO_STA_RXFIFOHF                   ((u32)0x00008000)        /* Receive FIFO Half Full: there are at least 8 words in the FIFO */
05015 #define  SDIO_STA_TXFIFOF                    ((u32)0x00010000)        /* Transmit FIFO full */
05016 #define  SDIO_STA_RXFIFOF                    ((u32)0x00020000)        /* Receive FIFO full */
05017 #define  SDIO_STA_TXFIFOE                    ((u32)0x00040000)        /* Transmit FIFO empty */
05018 #define  SDIO_STA_RXFIFOE                    ((u32)0x00080000)        /* Receive FIFO empty */
05019 #define  SDIO_STA_TXDAVL                     ((u32)0x00100000)        /* Data available in transmit FIFO */
05020 #define  SDIO_STA_RXDAVL                     ((u32)0x00200000)        /* Data available in receive FIFO */
05021 #define  SDIO_STA_SDIOIT                     ((u32)0x00400000)        /* SDIO interrupt received */
05022 #define  SDIO_STA_CEATAEND                   ((u32)0x00800000)        /* CE-ATA command completion signal received for CMD61 */
05023
05024
05025 /*******************  Bit definition for SDIO_ICR register  *******************/
05026 #define  SDIO_ICR_CCRCFAILC                  ((u32)0x00000001)        /* CCRCFAIL flag clear bit */
05027 #define  SDIO_ICR_DCRCFAILC                  ((u32)0x00000002)        /* DCRCFAIL flag clear bit */
05028 #define  SDIO_ICR_CTIMEOUTC                  ((u32)0x00000004)        /* CTIMEOUT flag clear bit */
05029 #define  SDIO_ICR_DTIMEOUTC                  ((u32)0x00000008)        /* DTIMEOUT flag clear bit */
05030 #define  SDIO_ICR_TXUNDERRC                  ((u32)0x00000010)        /* TXUNDERR flag clear bit */
05031 #define  SDIO_ICR_RXOVERRC                   ((u32)0x00000020)        /* RXOVERR flag clear bit */
05032 #define  SDIO_ICR_CMDRENDC                   ((u32)0x00000040)        /* CMDREND flag clear bit */
05033 #define  SDIO_ICR_CMDSENTC                   ((u32)0x00000080)        /* CMDSENT flag clear bit */
05034 #define  SDIO_ICR_DATAENDC                   ((u32)0x00000100)        /* DATAEND flag clear bit */
05035 #define  SDIO_ICR_STBITERRC                  ((u32)0x00000200)        /* STBITERR flag clear bit */
05036 #define  SDIO_ICR_DBCKENDC                   ((u32)0x00000400)        /* DBCKEND flag clear bit */
05037 #define  SDIO_ICR_SDIOITC                    ((u32)0x00400000)        /* SDIOIT flag clear bit */
05038 #define  SDIO_ICR_CEATAENDC                  ((u32)0x00800000)        /* CEATAEND flag clear bit */
05039
05040
05041 /******************  Bit definition for SDIO_MASK register  *******************/
05042 #define  SDIO_MASK_CCRCFAILIE                ((u32)0x00000001)        /* Command CRC Fail Interrupt Enable */
05043 #define  SDIO_MASK_DCRCFAILIE                ((u32)0x00000002)        /* Data CRC Fail Interrupt Enable */
05044 #define  SDIO_MASK_CTIMEOUTIE                ((u32)0x00000004)        /* Command TimeOut Interrupt Enable */
05045 #define  SDIO_MASK_DTIMEOUTIE                ((u32)0x00000008)        /* Data TimeOut Interrupt Enable */
05046 #define  SDIO_MASK_TXUNDERRIE                ((u32)0x00000010)        /* Tx FIFO UnderRun Error Interrupt Enable */
05047 #define  SDIO_MASK_RXOVERRIE                 ((u32)0x00000020)        /* Rx FIFO OverRun Error Interrupt Enable */
05048 #define  SDIO_MASK_CMDRENDIE                 ((u32)0x00000040)        /* Command Response Received Interrupt Enable */
05049 #define  SDIO_MASK_CMDSENTIE                 ((u32)0x00000080)        /* Command Sent Interrupt Enable */
05050 #define  SDIO_MASK_DATAENDIE                 ((u32)0x00000100)        /* Data End Interrupt Enable */
05051 #define  SDIO_MASK_STBITERRIE                ((u32)0x00000200)        /* Start Bit Error Interrupt Enable */
05052 #define  SDIO_MASK_DBCKENDIE                 ((u32)0x00000400)        /* Data Block End Interrupt Enable */
05053 #define  SDIO_MASK_CMDACTIE                  ((u32)0x00000800)        /* CCommand Acting Interrupt Enable */
05054 #define  SDIO_MASK_TXACTIE                   ((u32)0x00001000)        /* Data Transmit Acting Interrupt Enable */
05055 #define  SDIO_MASK_RXACTIE                   ((u32)0x00002000)        /* Data receive acting interrupt enabled */
05056 #define  SDIO_MASK_TXFIFOHEIE                ((u32)0x00004000)        /* Tx FIFO Half Empty interrupt Enable */
05057 #define  SDIO_MASK_RXFIFOHFIE                ((u32)0x00008000)        /* Rx FIFO Half Full interrupt Enable */
05058 #define  SDIO_MASK_TXFIFOFIE                 ((u32)0x00010000)        /* Tx FIFO Full interrupt Enable */
05059 #define  SDIO_MASK_RXFIFOFIE                 ((u32)0x00020000)        /* Rx FIFO Full interrupt Enable */
05060 #define  SDIO_MASK_TXFIFOEIE                 ((u32)0x00040000)        /* Tx FIFO Empty interrupt Enable */
05061 #define  SDIO_MASK_RXFIFOEIE                 ((u32)0x00080000)        /* Rx FIFO Empty interrupt Enable */
05062 #define  SDIO_MASK_TXDAVLIE                  ((u32)0x00100000)        /* Data available in Tx FIFO interrupt Enable */
05063 #define  SDIO_MASK_RXDAVLIE                  ((u32)0x00200000)        /* Data available in Rx FIFO interrupt Enable */
05064 #define  SDIO_MASK_SDIOITIE                  ((u32)0x00400000)        /* SDIO Mode Interrupt Received interrupt Enable */
05065 #define  SDIO_MASK_CEATAENDIE                ((u32)0x00800000)        /* CE-ATA command completion signal received Interrupt Enable */
05066
05067
05068 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
05069 #define  SDIO_FIFOCNT_FIFOCOUNT              ((u32)0x00FFFFFF)        /* Remaining number of words to be written to or read from the FIFO */
05070
05071
05072 /******************  Bit definition for SDIO_FIFO register  *******************/
05073 #define  SDIO_FIFO_FIFODATA                  ((u32)0xFFFFFFFF)        /* Receive and transmit FIFO data */
05074
05075
05076
05077 /******************************************************************************/
05078 /*                                                                            */
05079 /*                                   USB                                      */
05080 /*                                                                            */
05081 /******************************************************************************/
05082
05083 /* Endpoint-specific registers */
05084 /*******************  Bit definition for USB_EP0R register  *******************/
05085 #define  USB_EP0R_EA                         ((u16)0x000F)            /* Endpoint Address */
05086
05087 #define  USB_EP0R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05088 #define  USB_EP0R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05089 #define  USB_EP0R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05090
05091 #define  USB_EP0R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05092 #define  USB_EP0R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05093 #define  USB_EP0R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05094
05095 #define  USB_EP0R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05096 #define  USB_EP0R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05097 #define  USB_EP0R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05098
05099 #define  USB_EP0R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05100
05101 #define  USB_EP0R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05102 #define  USB_EP0R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05103 #define  USB_EP0R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05104
05105 #define  USB_EP0R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05106 #define  USB_EP0R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05107
05108
05109 /*******************  Bit definition for USB_EP1R register  *******************/
05110 #define  USB_EP1R_EA                         ((u16)0x000F)            /* Endpoint Address */
05111
05112 #define  USB_EP1R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05113 #define  USB_EP1R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05114 #define  USB_EP1R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05115
05116 #define  USB_EP1R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05117 #define  USB_EP1R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05118 #define  USB_EP1R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05119
05120 #define  USB_EP1R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05121 #define  USB_EP1R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05122 #define  USB_EP1R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05123
05124 #define  USB_EP1R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05125
05126 #define  USB_EP1R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05127 #define  USB_EP1R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05128 #define  USB_EP1R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05129
05130 #define  USB_EP1R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05131 #define  USB_EP1R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05132
05133
05134 /*******************  Bit definition for USB_EP2R register  *******************/
05135 #define  USB_EP2R_EA                         ((u16)0x000F)            /* Endpoint Address */
05136
05137 #define  USB_EP2R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05138 #define  USB_EP2R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05139 #define  USB_EP2R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05140
05141 #define  USB_EP2R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05142 #define  USB_EP2R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05143 #define  USB_EP2R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05144
05145 #define  USB_EP2R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05146 #define  USB_EP2R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05147 #define  USB_EP2R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05148
05149 #define  USB_EP2R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05150
05151 #define  USB_EP2R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05152 #define  USB_EP2R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05153 #define  USB_EP2R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05154
05155 #define  USB_EP2R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05156 #define  USB_EP2R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05157
05158
05159 /*******************  Bit definition for USB_EP3R register  *******************/
05160 #define  USB_EP3R_EA                         ((u16)0x000F)            /* Endpoint Address */
05161
05162 #define  USB_EP3R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05163 #define  USB_EP3R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05164 #define  USB_EP3R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05165
05166 #define  USB_EP3R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05167 #define  USB_EP3R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05168 #define  USB_EP3R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05169
05170 #define  USB_EP3R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05171 #define  USB_EP3R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05172 #define  USB_EP3R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05173
05174 #define  USB_EP3R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05175
05176 #define  USB_EP3R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05177 #define  USB_EP3R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05178 #define  USB_EP3R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05179
05180 #define  USB_EP3R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05181 #define  USB_EP3R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05182
05183
05184 /*******************  Bit definition for USB_EP4R register  *******************/
05185 #define  USB_EP4R_EA                         ((u16)0x000F)            /* Endpoint Address */
05186
05187 #define  USB_EP4R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05188 #define  USB_EP4R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05189 #define  USB_EP4R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05190
05191 #define  USB_EP4R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05192 #define  USB_EP4R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05193 #define  USB_EP4R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05194
05195 #define  USB_EP4R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05196 #define  USB_EP4R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05197 #define  USB_EP4R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05198
05199 #define  USB_EP4R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05200
05201 #define  USB_EP4R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05202 #define  USB_EP4R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05203 #define  USB_EP4R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05204
05205 #define  USB_EP4R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05206 #define  USB_EP4R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05207
05208
05209 /*******************  Bit definition for USB_EP5R register  *******************/
05210 #define  USB_EP5R_EA                         ((u16)0x000F)            /* Endpoint Address */
05211
05212 #define  USB_EP5R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05213 #define  USB_EP5R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05214 #define  USB_EP5R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05215
05216 #define  USB_EP5R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05217 #define  USB_EP5R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05218 #define  USB_EP5R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05219
05220 #define  USB_EP5R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05221 #define  USB_EP5R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05222 #define  USB_EP5R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05223
05224 #define  USB_EP5R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05225
05226 #define  USB_EP5R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05227 #define  USB_EP5R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05228 #define  USB_EP5R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05229
05230 #define  USB_EP5R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05231 #define  USB_EP5R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05232
05233
05234 /*******************  Bit definition for USB_EP6R register  *******************/
05235 #define  USB_EP6R_EA                         ((u16)0x000F)            /* Endpoint Address */
05236
05237 #define  USB_EP6R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05238 #define  USB_EP6R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05239 #define  USB_EP6R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05240
05241 #define  USB_EP6R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05242 #define  USB_EP6R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05243 #define  USB_EP6R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05244
05245 #define  USB_EP6R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05246 #define  USB_EP6R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05247 #define  USB_EP6R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05248
05249 #define  USB_EP6R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05250
05251 #define  USB_EP6R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05252 #define  USB_EP6R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05253 #define  USB_EP6R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05254
05255 #define  USB_EP6R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05256 #define  USB_EP6R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05257
05258
05259 /*******************  Bit definition for USB_EP7R register  *******************/
05260 #define  USB_EP7R_EA                         ((u16)0x000F)            /* Endpoint Address */
05261
05262 #define  USB_EP7R_STAT_TX                    ((u16)0x0030)            /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
05263 #define  USB_EP7R_STAT_TX_0                  ((u16)0x0010)            /* Bit 0 */
05264 #define  USB_EP7R_STAT_TX_1                  ((u16)0x0020)            /* Bit 1 */
05265
05266 #define  USB_EP7R_DTOG_TX                    ((u16)0x0040)            /* Data Toggle, for transmission transfers */
05267 #define  USB_EP7R_CTR_TX                     ((u16)0x0080)            /* Correct Transfer for transmission */
05268 #define  USB_EP7R_EP_KIND                    ((u16)0x0100)            /* Endpoint Kind */
05269
05270 #define  USB_EP7R_EP_TYPE                    ((u16)0x0600)            /* EP_TYPE[1:0] bits (Endpoint type) */
05271 #define  USB_EP7R_EP_TYPE_0                  ((u16)0x0200)            /* Bit 0 */
05272 #define  USB_EP7R_EP_TYPE_1                  ((u16)0x0400)            /* Bit 1 */
05273
05274 #define  USB_EP7R_SETUP                      ((u16)0x0800)            /* Setup transaction completed */
05275
05276 #define  USB_EP7R_STAT_RX                    ((u16)0x3000)            /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
05277 #define  USB_EP7R_STAT_RX_0                  ((u16)0x1000)            /* Bit 0 */
05278 #define  USB_EP7R_STAT_RX_1                  ((u16)0x2000)            /* Bit 1 */
05279
05280 #define  USB_EP7R_DTOG_RX                    ((u16)0x4000)            /* Data Toggle, for reception transfers */
05281 #define  USB_EP7R_CTR_RX                     ((u16)0x8000)            /* Correct Transfer for reception */
05282
05283
05284 /* Common registers */
05285 /*******************  Bit definition for USB_CNTR register  *******************/
05286 #define  USB_CNTR_FRES                       ((u16)0x0001)            /* Force USB Reset */
05287 #define  USB_CNTR_PDWN                       ((u16)0x0002)            /* Power down */
05288 #define  USB_CNTR_LP_MODE                    ((u16)0x0004)            /* Low-power mode */
05289 #define  USB_CNTR_FSUSP                      ((u16)0x0008)            /* Force suspend */
05290 #define  USB_CNTR_RESUME                     ((u16)0x0010)            /* Resume request */
05291 #define  USB_CNTR_ESOFM                      ((u16)0x0100)            /* Expected Start Of Frame Interrupt Mask */
05292 #define  USB_CNTR_SOFM                       ((u16)0x0200)            /* Start Of Frame Interrupt Mask */
05293 #define  USB_CNTR_RESETM                     ((u16)0x0400)            /* RESET Interrupt Mask */
05294 #define  USB_CNTR_SUSPM                      ((u16)0x0800)            /* Suspend mode Interrupt Mask */
05295 #define  USB_CNTR_WKUPM                      ((u16)0x1000)            /* Wakeup Interrupt Mask */
05296 #define  USB_CNTR_ERRM                       ((u16)0x2000)            /* Error Interrupt Mask */
05297 #define  USB_CNTR_PMAOVRM                    ((u16)0x4000)            /* Packet Memory Area Over / Underrun Interrupt Mask */
05298 #define  USB_CNTR_CTRM                       ((u16)0x8000)            /* Correct Transfer Interrupt Mask */
05299
05300
05301 /*******************  Bit definition for USB_ISTR register  *******************/
05302 #define  USB_ISTR_EP_ID                      ((u16)0x000F)            /* Endpoint Identifier */
05303 #define  USB_ISTR_DIR                        ((u16)0x0010)            /* Direction of transaction */
05304 #define  USB_ISTR_ESOF                       ((u16)0x0100)            /* Expected Start Of Frame */
05305 #define  USB_ISTR_SOF                        ((u16)0x0200)            /* Start Of Frame */
05306 #define  USB_ISTR_RESET                      ((u16)0x0400)            /* USB RESET request */
05307 #define  USB_ISTR_SUSP                       ((u16)0x0800)            /* Suspend mode request */
05308 #define  USB_ISTR_WKUP                       ((u16)0x1000)            /* Wake up */
05309 #define  USB_ISTR_ERR                        ((u16)0x2000)            /* Error */
05310 #define  USB_ISTR_PMAOVR                     ((u16)0x4000)            /* Packet Memory Area Over / Underrun */
05311 #define  USB_ISTR_CTR                        ((u16)0x8000)            /* Correct Transfer */
05312
05313
05314 /*******************  Bit definition for USB_FNR register  ********************/
05315 #define  USB_FNR_FN                          ((u16)0x07FF)            /* Frame Number */
05316 #define  USB_FNR_LSOF                        ((u16)0x1800)            /* Lost SOF */
05317 #define  USB_FNR_LCK                         ((u16)0x2000)            /* Locked */
05318 #define  USB_FNR_RXDM                        ((u16)0x4000)            /* Receive Data - Line Status */
05319 #define  USB_FNR_RXDP                        ((u16)0x8000)            /* Receive Data + Line Status */
05320
05321
05322 /******************  Bit definition for USB_DADDR register  *******************/
05323 #define  USB_DADDR_ADD                       ((u8)0x7F)               /* ADD[6:0] bits (Device Address) */
05324 #define  USB_DADDR_ADD0                      ((u8)0x01)               /* Bit 0 */
05325 #define  USB_DADDR_ADD1                      ((u8)0x02)               /* Bit 1 */
05326 #define  USB_DADDR_ADD2                      ((u8)0x04)               /* Bit 2 */
05327 #define  USB_DADDR_ADD3                      ((u8)0x08)               /* Bit 3 */
05328 #define  USB_DADDR_ADD4                      ((u8)0x10)               /* Bit 4 */
05329 #define  USB_DADDR_ADD5                      ((u8)0x20)               /* Bit 5 */
05330 #define  USB_DADDR_ADD6                      ((u8)0x40)               /* Bit 6 */
05331
05332 #define  USB_DADDR_EF                        ((u8)0x80)               /* Enable Function */
05333
05334
05335 /******************  Bit definition for USB_BTABLE register  ******************/
05336 #define  USB_BTABLE_BTABLE                   ((u16)0xFFF8)            /* Buffer Table */
05337
05338
05339 /* Buffer descriptor table */
05340 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
05341 #define  USB_ADDR0_TX_ADDR0_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 0 */
05342
05343
05344 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
05345 #define  USB_ADDR1_TX_ADDR1_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 1 */
05346
05347
05348 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
05349 #define  USB_ADDR2_TX_ADDR2_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 2 */
05350
05351
05352 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
05353 #define  USB_ADDR3_TX_ADDR3_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 3 */
05354
05355
05356 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
05357 #define  USB_ADDR4_TX_ADDR4_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 4 */
05358
05359
05360 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
05361 #define  USB_ADDR5_TX_ADDR5_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 5 */
05362
05363
05364 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
05365 #define  USB_ADDR6_TX_ADDR6_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 6 */
05366
05367
05368 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
05369 #define  USB_ADDR7_TX_ADDR7_TX               ((u16)0xFFFE)            /* Transmission Buffer Address 7 */
05370
05371
05372 /*----------------------------------------------------------------------------*/
05373
05374
05375 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
05376 #define  USB_COUNT0_TX_COUNT0_TX             ((u16)0x03FF)            /* Transmission Byte Count 0 */
05377
05378
05379 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
05380 #define  USB_COUNT1_TX_COUNT1_TX             ((u16)0x03FF)            /* Transmission Byte Count 1 */
05381
05382
05383 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
05384 #define  USB_COUNT2_TX_COUNT2_TX             ((u16)0x03FF)            /* Transmission Byte Count 2 */
05385
05386
05387 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
05388 #define  USB_COUNT3_TX_COUNT3_TX             ((u16)0x03FF)            /* Transmission Byte Count 3 */
05389
05390
05391 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
05392 #define  USB_COUNT4_TX_COUNT4_TX             ((u16)0x03FF)            /* Transmission Byte Count 4 */
05393
05394 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
05395 #define  USB_COUNT5_TX_COUNT5_TX             ((u16)0x03FF)            /* Transmission Byte Count 5 */
05396
05397
05398 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
05399 #define  USB_COUNT6_TX_COUNT6_TX             ((u16)0x03FF)            /* Transmission Byte Count 6 */
05400
05401
05402 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
05403 #define  USB_COUNT7_TX_COUNT7_TX             ((u16)0x03FF)            /* Transmission Byte Count 7 */
05404
05405
05406 /*----------------------------------------------------------------------------*/
05407
05408
05409 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
05410 #define  USB_COUNT0_TX_0_COUNT0_TX_0         ((u32)0x000003FF)        /* Transmission Byte Count 0 (low) */
05411
05412 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
05413 #define  USB_COUNT0_TX_1_COUNT0_TX_1         ((u32)0x03FF0000)        /* Transmission Byte Count 0 (high) */
05414
05415
05416
05417 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
05418 #define  USB_COUNT1_TX_0_COUNT1_TX_0          ((u32)0x000003FF)        /* Transmission Byte Count 1 (low) */
05419
05420 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
05421 #define  USB_COUNT1_TX_1_COUNT1_TX_1          ((u32)0x03FF0000)        /* Transmission Byte Count 1 (high) */
05422
05423
05424
05425 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
05426 #define  USB_COUNT2_TX_0_COUNT2_TX_0         ((u32)0x000003FF)        /* Transmission Byte Count 2 (low) */
05427
05428 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
05429 #define  USB_COUNT2_TX_1_COUNT2_TX_1         ((u32)0x03FF0000)        /* Transmission Byte Count 2 (high) */
05430
05431
05432
05433 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
05434 #define  USB_COUNT3_TX_0_COUNT3_TX_0         ((u16)0x000003FF)        /* Transmission Byte Count 3 (low) */
05435
05436 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
05437 #define  USB_COUNT3_TX_1_COUNT3_TX_1         ((u16)0x03FF0000)        /* Transmission Byte Count 3 (high) */
05438
05439
05440
05441 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
05442 #define  USB_COUNT4_TX_0_COUNT4_TX_0         ((u32)0x000003FF)        /* Transmission Byte Count 4 (low) */
05443
05444 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
05445 #define  USB_COUNT4_TX_1_COUNT4_TX_1         ((u32)0x03FF0000)        /* Transmission Byte Count 4 (high) */
05446
05447
05448
05449 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
05450 #define  USB_COUNT5_TX_0_COUNT5_TX_0         ((u32)0x000003FF)        /* Transmission Byte Count 5 (low) */
05451
05452 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
05453 #define  USB_COUNT5_TX_1_COUNT5_TX_1         ((u32)0x03FF0000)        /* Transmission Byte Count 5 (high) */
05454
05455
05456
05457 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
05458 #define  USB_COUNT6_TX_0_COUNT6_TX_0         ((u32)0x000003FF)        /* Transmission Byte Count 6 (low) */
05459
05460 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
05461 #define  USB_COUNT6_TX_1_COUNT6_TX_1         ((u32)0x03FF0000)        /* Transmission Byte Count 6 (high) */
05462
05463
05464
05465 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
05466 #define  USB_COUNT7_TX_0_COUNT7_TX_0         ((u32)0x000003FF)        /* Transmission Byte Count 7 (low) */
05467
05468 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
05469 #define  USB_COUNT7_TX_1_COUNT7_TX_1         ((u32)0x03FF0000)        /* Transmission Byte Count 7 (high) */
05470
05471
05472 /*----------------------------------------------------------------------------*/
05473
05474
05475 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
05476 #define  USB_ADDR0_RX_ADDR0_RX               ((u16)0xFFFE)            /* Reception Buffer Address 0 */
05477
05478
05479 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
05480 #define  USB_ADDR1_RX_ADDR1_RX               ((u16)0xFFFE)            /* Reception Buffer Address 1 */
05481
05482
05483 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
05484 #define  USB_ADDR2_RX_ADDR2_RX               ((u16)0xFFFE)            /* Reception Buffer Address 2 */
05485
05486
05487 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
05488 #define  USB_ADDR3_RX_ADDR3_RX               ((u16)0xFFFE)            /* Reception Buffer Address 3 */
05489
05490
05491 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
05492 #define  USB_ADDR4_RX_ADDR4_RX               ((u16)0xFFFE)            /* Reception Buffer Address 4 */
05493
05494
05495 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
05496 #define  USB_ADDR5_RX_ADDR5_RX               ((u16)0xFFFE)            /* Reception Buffer Address 5 */
05497
05498
05499 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
05500 #define  USB_ADDR6_RX_ADDR6_RX               ((u16)0xFFFE)            /* Reception Buffer Address 6 */
05501
05502
05503 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
05504 #define  USB_ADDR7_RX_ADDR7_RX               ((u16)0xFFFE)            /* Reception Buffer Address 7 */
05505
05506
05507 /*----------------------------------------------------------------------------*/
05508
05509
05510 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
05511 #define  USB_COUNT0_RX_COUNT0_RX             ((u16)0x03FF)            /* Reception Byte Count */
05512
05513 #define  USB_COUNT0_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05514 #define  USB_COUNT0_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05515 #define  USB_COUNT0_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05516 #define  USB_COUNT0_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05517 #define  USB_COUNT0_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05518 #define  USB_COUNT0_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05519
05520 #define  USB_COUNT0_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05521
05522
05523 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
05524 #define  USB_COUNT1_RX_COUNT1_RX             ((u16)0x03FF)            /* Reception Byte Count */
05525
05526 #define  USB_COUNT1_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05527 #define  USB_COUNT1_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05528 #define  USB_COUNT1_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05529 #define  USB_COUNT1_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05530 #define  USB_COUNT1_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05531 #define  USB_COUNT1_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05532
05533 #define  USB_COUNT1_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05534
05535
05536 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
05537 #define  USB_COUNT2_RX_COUNT2_RX             ((u16)0x03FF)            /* Reception Byte Count */
05538
05539 #define  USB_COUNT2_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05540 #define  USB_COUNT2_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05541 #define  USB_COUNT2_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05542 #define  USB_COUNT2_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05543 #define  USB_COUNT2_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05544 #define  USB_COUNT2_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05545
05546 #define  USB_COUNT2_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05547
05548
05549 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
05550 #define  USB_COUNT3_RX_COUNT3_RX             ((u16)0x03FF)            /* Reception Byte Count */
05551
05552 #define  USB_COUNT3_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05553 #define  USB_COUNT3_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05554 #define  USB_COUNT3_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05555 #define  USB_COUNT3_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05556 #define  USB_COUNT3_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05557 #define  USB_COUNT3_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05558
05559 #define  USB_COUNT3_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05560
05561
05562 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
05563 #define  USB_COUNT4_RX_COUNT4_RX             ((u16)0x03FF)            /* Reception Byte Count */
05564
05565 #define  USB_COUNT4_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05566 #define  USB_COUNT4_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05567 #define  USB_COUNT4_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05568 #define  USB_COUNT4_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05569 #define  USB_COUNT4_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05570 #define  USB_COUNT4_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05571
05572 #define  USB_COUNT4_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05573
05574
05575 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
05576 #define  USB_COUNT5_RX_COUNT5_RX             ((u16)0x03FF)            /* Reception Byte Count */
05577
05578 #define  USB_COUNT5_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05579 #define  USB_COUNT5_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05580 #define  USB_COUNT5_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05581 #define  USB_COUNT5_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05582 #define  USB_COUNT5_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05583 #define  USB_COUNT5_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05584
05585 #define  USB_COUNT5_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05586
05587 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
05588 #define  USB_COUNT6_RX_COUNT6_RX             ((u16)0x03FF)            /* Reception Byte Count */
05589
05590 #define  USB_COUNT6_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05591 #define  USB_COUNT6_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05592 #define  USB_COUNT6_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05593 #define  USB_COUNT6_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05594 #define  USB_COUNT6_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05595 #define  USB_COUNT6_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05596
05597 #define  USB_COUNT6_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05598
05599
05600 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
05601 #define  USB_COUNT7_RX_COUNT7_RX             ((u16)0x03FF)            /* Reception Byte Count */
05602
05603 #define  USB_COUNT7_RX_NUM_BLOCK             ((u16)0x7C00)            /* NUM_BLOCK[4:0] bits (Number of blocks) */
05604 #define  USB_COUNT7_RX_NUM_BLOCK_0           ((u16)0x0400)            /* Bit 0 */
05605 #define  USB_COUNT7_RX_NUM_BLOCK_1           ((u16)0x0800)            /* Bit 1 */
05606 #define  USB_COUNT7_RX_NUM_BLOCK_2           ((u16)0x1000)            /* Bit 2 */
05607 #define  USB_COUNT7_RX_NUM_BLOCK_3           ((u16)0x2000)            /* Bit 3 */
05608 #define  USB_COUNT7_RX_NUM_BLOCK_4           ((u16)0x4000)            /* Bit 4 */
05609
05610 #define  USB_COUNT7_RX_BLSIZE                ((u16)0x8000)            /* BLock SIZE */
05611
05612
05613 /*----------------------------------------------------------------------------*/
05614
05615
05616 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
05617 #define  USB_COUNT0_RX_0_COUNT0_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05618
05619 #define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05620 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((u32)0x00000400)        /* Bit 0 */
05621 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((u32)0x00000800)        /* Bit 1 */
05622 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((u32)0x00001000)        /* Bit 2 */
05623 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((u32)0x00002000)        /* Bit 3 */
05624 #define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((u32)0x00004000)        /* Bit 4 */
05625
05626 #define  USB_COUNT0_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05627
05628 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
05629 #define  USB_COUNT0_RX_1_COUNT0_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05630
05631 #define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05632 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 1 */
05633 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05634 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05635 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05636 #define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05637
05638 #define  USB_COUNT0_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05639
05640
05641
05642 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
05643 #define  USB_COUNT1_RX_0_COUNT1_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05644
05645 #define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05646 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((u32)0x00000400)        /* Bit 0 */
05647 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((u32)0x00000800)        /* Bit 1 */
05648 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((u32)0x00001000)        /* Bit 2 */
05649 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((u32)0x00002000)        /* Bit 3 */
05650 #define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((u32)0x00004000)        /* Bit 4 */
05651
05652 #define  USB_COUNT1_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05653
05654 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
05655 #define  USB_COUNT1_RX_1_COUNT1_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05656
05657 #define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05658 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 0 */
05659 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05660 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05661 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05662 #define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05663
05664 #define  USB_COUNT1_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05665
05666
05667
05668 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
05669 #define  USB_COUNT2_RX_0_COUNT2_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05670
05671 #define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05672 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((u32)0x00000400)        /* Bit 0 */
05673 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((u32)0x00000800)        /* Bit 1 */
05674 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((u32)0x00001000)        /* Bit 2 */
05675 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((u32)0x00002000)        /* Bit 3 */
05676 #define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((u32)0x00004000)        /* Bit 4 */
05677
05678 #define  USB_COUNT2_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05679
05680 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
05681 #define  USB_COUNT2_RX_1_COUNT2_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05682
05683 #define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05684 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 0 */
05685 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05686 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05687 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05688 #define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05689
05690 #define  USB_COUNT2_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05691
05692
05693
05694 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
05695 #define  USB_COUNT3_RX_0_COUNT3_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05696
05697 #define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05698 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((u32)0x00000400)        /* Bit 0 */
05699 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((u32)0x00000800)        /* Bit 1 */
05700 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((u32)0x00001000)        /* Bit 2 */
05701 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((u32)0x00002000)        /* Bit 3 */
05702 #define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((u32)0x00004000)        /* Bit 4 */
05703
05704 #define  USB_COUNT3_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05705
05706 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
05707 #define  USB_COUNT3_RX_1_COUNT3_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05708
05709 #define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05710 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 0 */
05711 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05712 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05713 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05714 #define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05715
05716 #define  USB_COUNT3_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05717
05718
05719
05720 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
05721 #define  USB_COUNT4_RX_0_COUNT4_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05722
05723 #define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05724 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((u32)0x00000400)        /* Bit 0 */
05725 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((u32)0x00000800)        /* Bit 1 */
05726 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((u32)0x00001000)        /* Bit 2 */
05727 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((u32)0x00002000)        /* Bit 3 */
05728 #define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((u32)0x00004000)        /* Bit 4 */
05729
05730 #define  USB_COUNT4_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05731
05732 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
05733 #define  USB_COUNT4_RX_1_COUNT4_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05734
05735 #define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05736 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 0 */
05737 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05738 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05739 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05740 #define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05741
05742 #define  USB_COUNT4_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05743
05744
05745
05746 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
05747 #define  USB_COUNT5_RX_0_COUNT5_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05748
05749 #define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05750 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((u32)0x00000400)        /* Bit 0 */
05751 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((u32)0x00000800)        /* Bit 1 */
05752 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((u32)0x00001000)        /* Bit 2 */
05753 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((u32)0x00002000)        /* Bit 3 */
05754 #define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((u32)0x00004000)        /* Bit 4 */
05755
05756 #define  USB_COUNT5_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05757
05758 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
05759 #define  USB_COUNT5_RX_1_COUNT5_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05760
05761 #define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05762 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 0 */
05763 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05764 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05765 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05766 #define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05767
05768 #define  USB_COUNT5_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05769
05770
05771
05772 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
05773 #define  USB_COUNT6_RX_0_COUNT6_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05774
05775 #define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05776 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((u32)0x00000400)        /* Bit 0 */
05777 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((u32)0x00000800)        /* Bit 1 */
05778 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((u32)0x00001000)        /* Bit 2 */
05779 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((u32)0x00002000)        /* Bit 3 */
05780 #define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((u32)0x00004000)        /* Bit 4 */
05781
05782 #define  USB_COUNT6_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05783
05784 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
05785 #define  USB_COUNT6_RX_1_COUNT6_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05786
05787 #define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05788 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 0 */
05789 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05790 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05791 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05792 #define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05793
05794 #define  USB_COUNT6_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05795
05796
05797
05798 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
05799 #define  USB_COUNT7_RX_0_COUNT7_RX_0         ((u32)0x000003FF)        /* Reception Byte Count (low) */
05800
05801 #define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((u32)0x00007C00)        /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
05802 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((u32)0x00000400)        /* Bit 0 */
05803 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((u32)0x00000800)        /* Bit 1 */
05804 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((u32)0x00001000)        /* Bit 2 */
05805 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((u32)0x00002000)        /* Bit 3 */
05806 #define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((u32)0x00004000)        /* Bit 4 */
05807
05808 #define  USB_COUNT7_RX_0_BLSIZE_0            ((u32)0x00008000)        /* BLock SIZE (low) */
05809
05810 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
05811 #define  USB_COUNT7_RX_1_COUNT7_RX_1         ((u32)0x03FF0000)        /* Reception Byte Count (high) */
05812
05813 #define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((u32)0x7C000000)        /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
05814 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((u32)0x04000000)        /* Bit 0 */
05815 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((u32)0x08000000)        /* Bit 1 */
05816 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((u32)0x10000000)        /* Bit 2 */
05817 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((u32)0x20000000)        /* Bit 3 */
05818 #define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((u32)0x40000000)        /* Bit 4 */
05819
05820 #define  USB_COUNT7_RX_1_BLSIZE_1            ((u32)0x80000000)        /* BLock SIZE (high) */
05821
05822
05823
05824 /******************************************************************************/
05825 /*                                                                            */
05826 /*                          Controller Area Network                           */
05827 /*                                                                            */
05828 /******************************************************************************/
05829
05830 /* CAN control and status registers */
05831 /*******************  Bit definition for CAN_MCR register  ********************/
05832 #define  CAN_MCR_INRQ                        ((u16)0x0001)            /* Initialization Request */
05833 #define  CAN_MCR_SLEEP                       ((u16)0x0002)            /* Sleep Mode Request */
05834 #define  CAN_MCR_TXFP                        ((u16)0x0004)            /* Transmit FIFO Priority */
05835 #define  CAN_MCR_RFLM                        ((u16)0x0008)            /* Receive FIFO Locked Mode */
05836 #define  CAN_MCR_NART                        ((u16)0x0010)            /* No Automatic Retransmission */
05837 #define  CAN_MCR_AWUM                        ((u16)0x0020)            /* Automatic Wakeup Mode */
05838 #define  CAN_MCR_ABOM                        ((u16)0x0040)            /* Automatic Bus-Off Management */
05839 #define  CAN_MCR_TTCM                        ((u16)0x0080)            /* Time Triggered Communication Mode */
05840 #define  CAN_MCR_RESET                       ((u16)0x8000)            /* bxCAN software master reset */
05841
05842
05843 /*******************  Bit definition for CAN_MSR register  ********************/
05844 #define  CAN_MSR_INAK                        ((u16)0x0001)            /* Initialization Acknowledge */
05845 #define  CAN_MSR_SLAK                        ((u16)0x0002)            /* Sleep Acknowledge */
05846 #define  CAN_MSR_ERRI                        ((u16)0x0004)            /* Error Interrupt */
05847 #define  CAN_MSR_WKUI                        ((u16)0x0008)            /* Wakeup Interrupt */
05848 #define  CAN_MSR_SLAKI                       ((u16)0x0010)            /* Sleep Acknowledge Interrupt */
05849 #define  CAN_MSR_TXM                         ((u16)0x0100)            /* Transmit Mode */
05850 #define  CAN_MSR_RXM                         ((u16)0x0200)            /* Receive Mode */
05851 #define  CAN_MSR_SAMP                        ((u16)0x0400)            /* Last Sample Point */
05852 #define  CAN_MSR_RX                          ((u16)0x0800)            /* CAN Rx Signal */
05853
05854
05855 /*******************  Bit definition for CAN_TSR register  ********************/
05856 #define  CAN_TSR_RQCP0                       ((u32)0x00000001)        /* Request Completed Mailbox0 */
05857 #define  CAN_TSR_TXOK0                       ((u32)0x00000002)        /* Transmission OK of Mailbox0 */
05858 #define  CAN_TSR_ALST0                       ((u32)0x00000004)        /* Arbitration Lost for Mailbox0 */
05859 #define  CAN_TSR_TERR0                       ((u32)0x00000008)        /* Transmission Error of Mailbox0 */
05860 #define  CAN_TSR_ABRQ0                       ((u32)0x00000080)        /* Abort Request for Mailbox0 */
05861 #define  CAN_TSR_RQCP1                       ((u32)0x00000100)        /* Request Completed Mailbox1 */
05862 #define  CAN_TSR_TXOK1                       ((u32)0x00000200)        /* Transmission OK of Mailbox1 */
05863 #define  CAN_TSR_ALST1                       ((u32)0x00000400)        /* Arbitration Lost for Mailbox1 */
05864 #define  CAN_TSR_TERR1                       ((u32)0x00000800)        /* Transmission Error of Mailbox1 */
05865 #define  CAN_TSR_ABRQ1                       ((u32)0x00008000)        /* Abort Request for Mailbox 1 */
05866 #define  CAN_TSR_RQCP2                       ((u32)0x00010000)        /* Request Completed Mailbox2 */
05867 #define  CAN_TSR_TXOK2                       ((u32)0x00020000)        /* Transmission OK of Mailbox 2 */
05868 #define  CAN_TSR_ALST2                       ((u32)0x00040000)        /* Arbitration Lost for mailbox 2 */
05869 #define  CAN_TSR_TERR2                       ((u32)0x00080000)        /* Transmission Error of Mailbox 2 */
05870 #define  CAN_TSR_ABRQ2                       ((u32)0x00800000)        /* Abort Request for Mailbox 2 */
05871 #define  CAN_TSR_CODE                        ((u32)0x03000000)        /* Mailbox Code */
05872
05873 #define  CAN_TSR_TME                         ((u32)0x1C000000)        /* TME[2:0] bits */
05874 #define  CAN_TSR_TME0                        ((u32)0x04000000)        /* Transmit Mailbox 0 Empty */
05875 #define  CAN_TSR_TME1                        ((u32)0x08000000)        /* Transmit Mailbox 1 Empty */
05876 #define  CAN_TSR_TME2                        ((u32)0x10000000)        /* Transmit Mailbox 2 Empty */
05877
05878 #define  CAN_TSR_LOW                         ((u32)0xE0000000)        /* LOW[2:0] bits */
05879 #define  CAN_TSR_LOW0                        ((u32)0x20000000)        /* Lowest Priority Flag for Mailbox 0 */
05880 #define  CAN_TSR_LOW1                        ((u32)0x40000000)        /* Lowest Priority Flag for Mailbox 1 */
05881 #define  CAN_TSR_LOW2                        ((u32)0x80000000)        /* Lowest Priority Flag for Mailbox 2 */
05882
05883
05884 /*******************  Bit definition for CAN_RF0R register  *******************/
05885 #define  CAN_RF0R_FMP0                       ((u8)0x03)               /* FIFO 0 Message Pending */
05886 #define  CAN_RF0R_FULL0                      ((u8)0x08)               /* FIFO 0 Full */
05887 #define  CAN_RF0R_FOVR0                      ((u8)0x10)               /* FIFO 0 Overrun */
05888 #define  CAN_RF0R_RFOM0                      ((u8)0x20)               /* Release FIFO 0 Output Mailbox */
05889
05890
05891 /*******************  Bit definition for CAN_RF1R register  *******************/
05892 #define  CAN_RF1R_FMP1                       ((u8)0x03)               /* FIFO 1 Message Pending */
05893 #define  CAN_RF1R_FULL1                      ((u8)0x08)               /* FIFO 1 Full */
05894 #define  CAN_RF1R_FOVR1                      ((u8)0x10)               /* FIFO 1 Overrun */
05895 #define  CAN_RF1R_RFOM1                      ((u8)0x20)               /* Release FIFO 1 Output Mailbox */
05896
05897
05898 /********************  Bit definition for CAN_IER register  *******************/
05899 #define  CAN_IER_TMEIE                       ((u32)0x00000001)        /* Transmit Mailbox Empty Interrupt Enable */
05900 #define  CAN_IER_FMPIE0                      ((u32)0x00000002)        /* FIFO Message Pending Interrupt Enable */
05901 #define  CAN_IER_FFIE0                       ((u32)0x00000004)        /* FIFO Full Interrupt Enable */
05902 #define  CAN_IER_FOVIE0                      ((u32)0x00000008)        /* FIFO Overrun Interrupt Enable */
05903 #define  CAN_IER_FMPIE1                      ((u32)0x00000010)        /* FIFO Message Pending Interrupt Enable */
05904 #define  CAN_IER_FFIE1                       ((u32)0x00000020)        /* FIFO Full Interrupt Enable */
05905 #define  CAN_IER_FOVIE1                      ((u32)0x00000040)        /* FIFO Overrun Interrupt Enable */
05906 #define  CAN_IER_EWGIE                       ((u32)0x00000100)        /* Error Warning Interrupt Enable */
05907 #define  CAN_IER_EPVIE                       ((u32)0x00000200)        /* Error Passive Interrupt Enable */
05908 #define  CAN_IER_BOFIE                       ((u32)0x00000400)        /* Bus-Off Interrupt Enable */
05909 #define  CAN_IER_LECIE                       ((u32)0x00000800)        /* Last Error Code Interrupt Enable */
05910 #define  CAN_IER_ERRIE                       ((u32)0x00008000)        /* Error Interrupt Enable */
05911 #define  CAN_IER_WKUIE                       ((u32)0x00010000)        /* Wakeup Interrupt Enable */
05912 #define  CAN_IER_SLKIE                       ((u32)0x00020000)        /* Sleep Interrupt Enable */
05913
05914
05915 /********************  Bit definition for CAN_ESR register  *******************/
05916 #define  CAN_ESR_EWGF                        ((u32)0x00000001)        /* Error Warning Flag */
05917 #define  CAN_ESR_EPVF                        ((u32)0x00000002)        /* Error Passive Flag */
05918 #define  CAN_ESR_BOFF                        ((u32)0x00000004)        /* Bus-Off Flag */
05919
05920 #define  CAN_ESR_LEC                         ((u32)0x00000070)        /* LEC[2:0] bits (Last Error Code) */
05921 #define  CAN_ESR_LEC_0                       ((u32)0x00000010)        /* Bit 0 */
05922 #define  CAN_ESR_LEC_1                       ((u32)0x00000020)        /* Bit 1 */
05923 #define  CAN_ESR_LEC_2                       ((u32)0x00000040)        /* Bit 2 */
05924
05925 #define  CAN_ESR_TEC                         ((u32)0x00FF0000)        /* Least significant byte of the 9-bit Transmit Error Counter */
05926 #define  CAN_ESR_REC                         ((u32)0xFF000000)        /* Receive Error Counter */
05927
05928
05929 /*******************  Bit definition for CAN_BTR register  ********************/
05930 #define  CAN_BTR_BRP                         ((u32)0x000003FF)        /* Baud Rate Prescaler */
05931 #define  CAN_BTR_TS1                         ((u32)0x000F0000)        /* Time Segment 1 */
05932 #define  CAN_BTR_TS2                         ((u32)0x00700000)        /* Time Segment 2 */
05933 #define  CAN_BTR_SJW                         ((u32)0x03000000)        /* Resynchronization Jump Width */
05934 #define  CAN_BTR_LBKM                        ((u32)0x40000000)        /* Loop Back Mode (Debug) */
05935 #define  CAN_BTR_SILM                        ((u32)0x80000000)        /* Silent Mode */
05936
05937
05938 /* Mailbox registers */
05939 /******************  Bit definition for CAN_TI0R register  ********************/
05940 #define  CAN_TI0R_TXRQ                       ((u32)0x00000001)        /* Transmit Mailbox Request */
05941 #define  CAN_TI0R_RTR                        ((u32)0x00000002)        /* Remote Transmission Request */
05942 #define  CAN_TI0R_IDE                        ((u32)0x00000004)        /* Identifier Extension */
05943 #define  CAN_TI0R_EXID                       ((u32)0x001FFFF8)        /* Extended Identifier */
05944 #define  CAN_TI0R_STID                       ((u32)0xFFE00000)        /* Standard Identifier or Extended Identifier */
05945
05946
05947 /******************  Bit definition for CAN_TDT0R register  *******************/
05948 #define  CAN_TDT0R_DLC                       ((u32)0x0000000F)        /* Data Length Code */
05949 #define  CAN_TDT0R_TGT                       ((u32)0x00000100)        /* Transmit Global Time */
05950 #define  CAN_TDT0R_TIME                      ((u32)0xFFFF0000)        /* Message Time Stamp */
05951
05952
05953 /******************  Bit definition for CAN_TDL0R register  *******************/
05954 #define  CAN_TDL0R_DATA0                     ((u32)0x000000FF)        /* Data byte 0 */
05955 #define  CAN_TDL0R_DATA1                     ((u32)0x0000FF00)        /* Data byte 1 */
05956 #define  CAN_TDL0R_DATA2                     ((u32)0x00FF0000)        /* Data byte 2 */
05957 #define  CAN_TDL0R_DATA3                     ((u32)0xFF000000)        /* Data byte 3 */
05958
05959
05960 /******************  Bit definition for CAN_TDH0R register  *******************/
05961 #define  CAN_TDH0R_DATA4                     ((u32)0x000000FF)        /* Data byte 4 */
05962 #define  CAN_TDH0R_DATA5                     ((u32)0x0000FF00)        /* Data byte 5 */
05963 #define  CAN_TDH0R_DATA6                     ((u32)0x00FF0000)        /* Data byte 6 */
05964 #define  CAN_TDH0R_DATA7                     ((u32)0xFF000000)        /* Data byte 7 */
05965
05966
05967 /*******************  Bit definition for CAN_TI1R register  *******************/
05968 #define  CAN_TI1R_TXRQ                       ((u32)0x00000001)        /* Transmit Mailbox Request */
05969 #define  CAN_TI1R_RTR                        ((u32)0x00000002)        /* Remote Transmission Request */
05970 #define  CAN_TI1R_IDE                        ((u32)0x00000004)        /* Identifier Extension */
05971 #define  CAN_TI1R_EXID                       ((u32)0x001FFFF8)        /* Extended Identifier */
05972 #define  CAN_TI1R_STID                       ((u32)0xFFE00000)        /* Standard Identifier or Extended Identifier */
05973
05974
05975 /*******************  Bit definition for CAN_TDT1R register  ******************/
05976 #define  CAN_TDT1R_DLC                       ((u32)0x0000000F)        /* Data Length Code */
05977 #define  CAN_TDT1R_TGT                       ((u32)0x00000100)        /* Transmit Global Time */
05978 #define  CAN_TDT1R_TIME                      ((u32)0xFFFF0000)        /* Message Time Stamp */
05979
05980
05981 /*******************  Bit definition for CAN_TDL1R register  ******************/
05982 #define  CAN_TDL1R_DATA0                     ((u32)0x000000FF)        /* Data byte 0 */
05983 #define  CAN_TDL1R_DATA1                     ((u32)0x0000FF00)        /* Data byte 1 */
05984 #define  CAN_TDL1R_DATA2                     ((u32)0x00FF0000)        /* Data byte 2 */
05985 #define  CAN_TDL1R_DATA3                     ((u32)0xFF000000)        /* Data byte 3 */
05986
05987
05988 /*******************  Bit definition for CAN_TDH1R register  ******************/
05989 #define  CAN_TDH1R_DATA4                     ((u32)0x000000FF)        /* Data byte 4 */
05990 #define  CAN_TDH1R_DATA5                     ((u32)0x0000FF00)        /* Data byte 5 */
05991 #define  CAN_TDH1R_DATA6                     ((u32)0x00FF0000)        /* Data byte 6 */
05992 #define  CAN_TDH1R_DATA7                     ((u32)0xFF000000)        /* Data byte 7 */
05993
05994
05995 /*******************  Bit definition for CAN_TI2R register  *******************/
05996 #define  CAN_TI2R_TXRQ                       ((u32)0x00000001)        /* Transmit Mailbox Request */
05997 #define  CAN_TI2R_RTR                        ((u32)0x00000002)        /* Remote Transmission Request */
05998 #define  CAN_TI2R_IDE                        ((u32)0x00000004)        /* Identifier Extension */
05999 #define  CAN_TI2R_EXID                       ((u32)0x001FFFF8)        /* Extended identifier */
06000 #define  CAN_TI2R_STID                       ((u32)0xFFE00000)        /* Standard Identifier or Extended Identifier */
06001
06002
06003 /*******************  Bit definition for CAN_TDT2R register  ******************/
06004 #define  CAN_TDT2R_DLC                       ((u32)0x0000000F)        /* Data Length Code */
06005 #define  CAN_TDT2R_TGT                       ((u32)0x00000100)        /* Transmit Global Time */
06006 #define  CAN_TDT2R_TIME                      ((u32)0xFFFF0000)        /* Message Time Stamp */
06007
06008
06009 /*******************  Bit definition for CAN_TDL2R register  ******************/
06010 #define  CAN_TDL2R_DATA0                     ((u32)0x000000FF)        /* Data byte 0 */
06011 #define  CAN_TDL2R_DATA1                     ((u32)0x0000FF00)        /* Data byte 1 */
06012 #define  CAN_TDL2R_DATA2                     ((u32)0x00FF0000)        /* Data byte 2 */
06013 #define  CAN_TDL2R_DATA3                     ((u32)0xFF000000)        /* Data byte 3 */
06014
06015
06016 /*******************  Bit definition for CAN_TDH2R register  ******************/
06017 #define  CAN_TDH2R_DATA4                     ((u32)0x000000FF)        /* Data byte 4 */
06018 #define  CAN_TDH2R_DATA5                     ((u32)0x0000FF00)        /* Data byte 5 */
06019 #define  CAN_TDH2R_DATA6                     ((u32)0x00FF0000)        /* Data byte 6 */
06020 #define  CAN_TDH2R_DATA7                     ((u32)0xFF000000)        /* Data byte 7 */
06021
06022
06023 /*******************  Bit definition for CAN_RI0R register  *******************/
06024 #define  CAN_RI0R_RTR                        ((u32)0x00000002)        /* Remote Transmission Request */
06025 #define  CAN_RI0R_IDE                        ((u32)0x00000004)        /* Identifier Extension */
06026 #define  CAN_RI0R_EXID                       ((u32)0x001FFFF8)        /* Extended Identifier */
06027 #define  CAN_RI0R_STID                       ((u32)0xFFE00000)        /* Standard Identifier or Extended Identifier */
06028
06029
06030 /*******************  Bit definition for CAN_RDT0R register  ******************/
06031 #define  CAN_RDT0R_DLC                       ((u32)0x0000000F)        /* Data Length Code */
06032 #define  CAN_RDT0R_FMI                       ((u32)0x0000FF00)        /* Filter Match Index */
06033 #define  CAN_RDT0R_TIME                      ((u32)0xFFFF0000)        /* Message Time Stamp */
06034
06035
06036 /*******************  Bit definition for CAN_RDL0R register  ******************/
06037 #define  CAN_RDL0R_DATA0                     ((u32)0x000000FF)        /* Data byte 0 */
06038 #define  CAN_RDL0R_DATA1                     ((u32)0x0000FF00)        /* Data byte 1 */
06039 #define  CAN_RDL0R_DATA2                     ((u32)0x00FF0000)        /* Data byte 2 */
06040 #define  CAN_RDL0R_DATA3                     ((u32)0xFF000000)        /* Data byte 3 */
06041
06042
06043 /*******************  Bit definition for CAN_RDH0R register  ******************/
06044 #define  CAN_RDH0R_DATA4                     ((u32)0x000000FF)        /* Data byte 4 */
06045 #define  CAN_RDH0R_DATA5                     ((u32)0x0000FF00)        /* Data byte 5 */
06046 #define  CAN_RDH0R_DATA6                     ((u32)0x00FF0000)        /* Data byte 6 */
06047 #define  CAN_RDH0R_DATA7                     ((u32)0xFF000000)        /* Data byte 7 */
06048
06049
06050 /*******************  Bit definition for CAN_RI1R register  *******************/
06051 #define  CAN_RI1R_RTR                        ((u32)0x00000002)        /* Remote Transmission Request */
06052 #define  CAN_RI1R_IDE                        ((u32)0x00000004)        /* Identifier Extension */
06053 #define  CAN_RI1R_EXID                       ((u32)0x001FFFF8)        /* Extended identifier */
06054 #define  CAN_RI1R_STID                       ((u32)0xFFE00000)        /* Standard Identifier or Extended Identifier */
06055
06056
06057 /*******************  Bit definition for CAN_RDT1R register  ******************/
06058 #define  CAN_RDT1R_DLC                       ((u32)0x0000000F)        /* Data Length Code */
06059 #define  CAN_RDT1R_FMI                       ((u32)0x0000FF00)        /* Filter Match Index */
06060 #define  CAN_RDT1R_TIME                      ((u32)0xFFFF0000)        /* Message Time Stamp */
06061
06062
06063 /*******************  Bit definition for CAN_RDL1R register  ******************/
06064 #define  CAN_RDL1R_DATA0                     ((u32)0x000000FF)        /* Data byte 0 */
06065 #define  CAN_RDL1R_DATA1                     ((u32)0x0000FF00)        /* Data byte 1 */
06066 #define  CAN_RDL1R_DATA2                     ((u32)0x00FF0000)        /* Data byte 2 */
06067 #define  CAN_RDL1R_DATA3                     ((u32)0xFF000000)        /* Data byte 3 */
06068
06069
06070 /*******************  Bit definition for CAN_RDH1R register  ******************/
06071 #define  CAN_RDH1R_DATA4                     ((u32)0x000000FF)        /* Data byte 4 */
06072 #define  CAN_RDH1R_DATA5                     ((u32)0x0000FF00)        /* Data byte 5 */
06073 #define  CAN_RDH1R_DATA6                     ((u32)0x00FF0000)        /* Data byte 6 */
06074 #define  CAN_RDH1R_DATA7                     ((u32)0xFF000000)        /* Data byte 7 */
06075
06076 /* CAN filter registers */
06077 /*******************  Bit definition for CAN_FMR register  ********************/
06078 #define  CAN_FMR_FINIT                       ((u8)0x01)               /* Filter Init Mode */
06079
06080
06081 /*******************  Bit definition for CAN_FM1R register  *******************/
06082 #define  CAN_FM1R_FBM                        ((u16)0x3FFF)            /* Filter Mode */
06083 #define  CAN_FM1R_FBM0                       ((u16)0x0001)            /* Filter Init Mode bit 0 */
06084 #define  CAN_FM1R_FBM1                       ((u16)0x0002)            /* Filter Init Mode bit 1 */
06085 #define  CAN_FM1R_FBM2                       ((u16)0x0004)            /* Filter Init Mode bit 2 */
06086 #define  CAN_FM1R_FBM3                       ((u16)0x0008)            /* Filter Init Mode bit 3 */
06087 #define  CAN_FM1R_FBM4                       ((u16)0x0010)            /* Filter Init Mode bit 4 */
06088 #define  CAN_FM1R_FBM5                       ((u16)0x0020)            /* Filter Init Mode bit 5 */
06089 #define  CAN_FM1R_FBM6                       ((u16)0x0040)            /* Filter Init Mode bit 6 */
06090 #define  CAN_FM1R_FBM7                       ((u16)0x0080)            /* Filter Init Mode bit 7 */
06091 #define  CAN_FM1R_FBM8                       ((u16)0x0100)            /* Filter Init Mode bit 8 */
06092 #define  CAN_FM1R_FBM9                       ((u16)0x0200)            /* Filter Init Mode bit 9 */
06093 #define  CAN_FM1R_FBM10                      ((u16)0x0400)            /* Filter Init Mode bit 10 */
06094 #define  CAN_FM1R_FBM11                      ((u16)0x0800)            /* Filter Init Mode bit 11 */
06095 #define  CAN_FM1R_FBM12                      ((u16)0x1000)            /* Filter Init Mode bit 12 */
06096 #define  CAN_FM1R_FBM13                      ((u16)0x2000)            /* Filter Init Mode bit 13 */
06097
06098
06099 /*******************  Bit definition for CAN_FS1R register  *******************/
06100 #define  CAN_FS1R_FSC                        ((u16)0x3FFF)            /* Filter Scale Configuration */
06101 #define  CAN_FS1R_FSC0                       ((u16)0x0001)            /* Filter Scale Configuration bit 0 */
06102 #define  CAN_FS1R_FSC1                       ((u16)0x0002)            /* Filter Scale Configuration bit 1 */
06103 #define  CAN_FS1R_FSC2                       ((u16)0x0004)            /* Filter Scale Configuration bit 2 */
06104 #define  CAN_FS1R_FSC3                       ((u16)0x0008)            /* Filter Scale Configuration bit 3 */
06105 #define  CAN_FS1R_FSC4                       ((u16)0x0010)            /* Filter Scale Configuration bit 4 */
06106 #define  CAN_FS1R_FSC5                       ((u16)0x0020)            /* Filter Scale Configuration bit 5 */
06107 #define  CAN_FS1R_FSC6                       ((u16)0x0040)            /* Filter Scale Configuration bit 6 */
06108 #define  CAN_FS1R_FSC7                       ((u16)0x0080)            /* Filter Scale Configuration bit 7 */
06109 #define  CAN_FS1R_FSC8                       ((u16)0x0100)            /* Filter Scale Configuration bit 8 */
06110 #define  CAN_FS1R_FSC9                       ((u16)0x0200)            /* Filter Scale Configuration bit 9 */
06111 #define  CAN_FS1R_FSC10                      ((u16)0x0400)            /* Filter Scale Configuration bit 10 */
06112 #define  CAN_FS1R_FSC11                      ((u16)0x0800)            /* Filter Scale Configuration bit 11 */
06113 #define  CAN_FS1R_FSC12                      ((u16)0x1000)            /* Filter Scale Configuration bit 12 */
06114 #define  CAN_FS1R_FSC13                      ((u16)0x2000)            /* Filter Scale Configuration bit 13 */
06115
06116
06117 /******************  Bit definition for CAN_FFA1R register  *******************/
06118 #define  CAN_FFA1R_FFA                       ((u16)0x3FFF)            /* Filter FIFO Assignment */
06119 #define  CAN_FFA1R_FFA0                      ((u16)0x0001)            /* Filter FIFO Assignment for Filter 0 */
06120 #define  CAN_FFA1R_FFA1                      ((u16)0x0002)            /* Filter FIFO Assignment for Filter 1 */
06121 #define  CAN_FFA1R_FFA2                      ((u16)0x0004)            /* Filter FIFO Assignment for Filter 2 */
06122 #define  CAN_FFA1R_FFA3                      ((u16)0x0008)            /* Filter FIFO Assignment for Filter 3 */
06123 #define  CAN_FFA1R_FFA4                      ((u16)0x0010)            /* Filter FIFO Assignment for Filter 4 */
06124 #define  CAN_FFA1R_FFA5                      ((u16)0x0020)            /* Filter FIFO Assignment for Filter 5 */
06125 #define  CAN_FFA1R_FFA6                      ((u16)0x0040)            /* Filter FIFO Assignment for Filter 6 */
06126 #define  CAN_FFA1R_FFA7                      ((u16)0x0080)            /* Filter FIFO Assignment for Filter 7 */
06127 #define  CAN_FFA1R_FFA8                      ((u16)0x0100)            /* Filter FIFO Assignment for Filter 8 */
06128 #define  CAN_FFA1R_FFA9                      ((u16)0x0200)            /* Filter FIFO Assignment for Filter 9 */
06129 #define  CAN_FFA1R_FFA10                     ((u16)0x0400)            /* Filter FIFO Assignment for Filter 10 */
06130 #define  CAN_FFA1R_FFA11                     ((u16)0x0800)            /* Filter FIFO Assignment for Filter 11 */
06131 #define  CAN_FFA1R_FFA12                     ((u16)0x1000)            /* Filter FIFO Assignment for Filter 12 */
06132 #define  CAN_FFA1R_FFA13                     ((u16)0x2000)            /* Filter FIFO Assignment for Filter 13 */
06133
06134
06135 /*******************  Bit definition for CAN_FA1R register  *******************/
06136 #define  CAN_FA1R_FACT                       ((u16)0x3FFF)            /* Filter Active */
06137 #define  CAN_FA1R_FACT0                      ((u16)0x0001)            /* Filter 0 Active */
06138 #define  CAN_FA1R_FACT1                      ((u16)0x0002)            /* Filter 1 Active */
06139 #define  CAN_FA1R_FACT2                      ((u16)0x0004)            /* Filter 2 Active */
06140 #define  CAN_FA1R_FACT3                      ((u16)0x0008)            /* Filter 3 Active */
06141 #define  CAN_FA1R_FACT4                      ((u16)0x0010)            /* Filter 4 Active */
06142 #define  CAN_FA1R_FACT5                      ((u16)0x0020)            /* Filter 5 Active */
06143 #define  CAN_FA1R_FACT6                      ((u16)0x0040)            /* Filter 6 Active */
06144 #define  CAN_FA1R_FACT7                      ((u16)0x0080)            /* Filter 7 Active */
06145 #define  CAN_FA1R_FACT8                      ((u16)0x0100)            /* Filter 8 Active */
06146 #define  CAN_FA1R_FACT9                      ((u16)0x0200)            /* Filter 9 Active */
06147 #define  CAN_FA1R_FACT10                     ((u16)0x0400)            /* Filter 10 Active */
06148 #define  CAN_FA1R_FACT11                     ((u16)0x0800)            /* Filter 11 Active */
06149 #define  CAN_FA1R_FACT12                     ((u16)0x1000)            /* Filter 12 Active */
06150 #define  CAN_FA1R_FACT13                     ((u16)0x2000)            /* Filter 13 Active */
06151
06152
06153 /*******************  Bit definition for CAN_F0R1 register  *******************/
06154 #define  CAN_F0R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06155 #define  CAN_F0R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06156 #define  CAN_F0R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06157 #define  CAN_F0R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06158 #define  CAN_F0R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06159 #define  CAN_F0R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06160 #define  CAN_F0R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06161 #define  CAN_F0R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06162 #define  CAN_F0R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06163 #define  CAN_F0R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06164 #define  CAN_F0R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06165 #define  CAN_F0R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06166 #define  CAN_F0R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06167 #define  CAN_F0R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06168 #define  CAN_F0R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06169 #define  CAN_F0R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06170 #define  CAN_F0R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06171 #define  CAN_F0R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06172 #define  CAN_F0R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06173 #define  CAN_F0R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06174 #define  CAN_F0R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06175 #define  CAN_F0R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06176 #define  CAN_F0R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06177 #define  CAN_F0R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06178 #define  CAN_F0R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06179 #define  CAN_F0R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06180 #define  CAN_F0R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06181 #define  CAN_F0R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06182 #define  CAN_F0R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06183 #define  CAN_F0R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06184 #define  CAN_F0R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06185 #define  CAN_F0R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06186
06187
06188 /*******************  Bit definition for CAN_F1R1 register  *******************/
06189 #define  CAN_F1R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06190 #define  CAN_F1R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06191 #define  CAN_F1R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06192 #define  CAN_F1R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06193 #define  CAN_F1R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06194 #define  CAN_F1R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06195 #define  CAN_F1R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06196 #define  CAN_F1R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06197 #define  CAN_F1R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06198 #define  CAN_F1R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06199 #define  CAN_F1R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06200 #define  CAN_F1R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06201 #define  CAN_F1R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06202 #define  CAN_F1R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06203 #define  CAN_F1R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06204 #define  CAN_F1R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06205 #define  CAN_F1R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06206 #define  CAN_F1R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06207 #define  CAN_F1R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06208 #define  CAN_F1R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06209 #define  CAN_F1R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06210 #define  CAN_F1R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06211 #define  CAN_F1R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06212 #define  CAN_F1R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06213 #define  CAN_F1R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06214 #define  CAN_F1R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06215 #define  CAN_F1R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06216 #define  CAN_F1R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06217 #define  CAN_F1R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06218 #define  CAN_F1R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06219 #define  CAN_F1R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06220 #define  CAN_F1R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06221
06222
06223 /*******************  Bit definition for CAN_F2R1 register  *******************/
06224 #define  CAN_F2R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06225 #define  CAN_F2R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06226 #define  CAN_F2R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06227 #define  CAN_F2R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06228 #define  CAN_F2R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06229 #define  CAN_F2R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06230 #define  CAN_F2R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06231 #define  CAN_F2R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06232 #define  CAN_F2R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06233 #define  CAN_F2R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06234 #define  CAN_F2R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06235 #define  CAN_F2R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06236 #define  CAN_F2R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06237 #define  CAN_F2R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06238 #define  CAN_F2R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06239 #define  CAN_F2R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06240 #define  CAN_F2R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06241 #define  CAN_F2R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06242 #define  CAN_F2R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06243 #define  CAN_F2R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06244 #define  CAN_F2R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06245 #define  CAN_F2R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06246 #define  CAN_F2R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06247 #define  CAN_F2R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06248 #define  CAN_F2R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06249 #define  CAN_F2R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06250 #define  CAN_F2R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06251 #define  CAN_F2R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06252 #define  CAN_F2R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06253 #define  CAN_F2R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06254 #define  CAN_F2R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06255 #define  CAN_F2R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06256
06257
06258 /*******************  Bit definition for CAN_F3R1 register  *******************/
06259 #define  CAN_F3R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06260 #define  CAN_F3R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06261 #define  CAN_F3R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06262 #define  CAN_F3R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06263 #define  CAN_F3R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06264 #define  CAN_F3R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06265 #define  CAN_F3R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06266 #define  CAN_F3R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06267 #define  CAN_F3R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06268 #define  CAN_F3R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06269 #define  CAN_F3R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06270 #define  CAN_F3R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06271 #define  CAN_F3R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06272 #define  CAN_F3R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06273 #define  CAN_F3R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06274 #define  CAN_F3R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06275 #define  CAN_F3R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06276 #define  CAN_F3R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06277 #define  CAN_F3R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06278 #define  CAN_F3R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06279 #define  CAN_F3R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06280 #define  CAN_F3R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06281 #define  CAN_F3R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06282 #define  CAN_F3R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06283 #define  CAN_F3R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06284 #define  CAN_F3R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06285 #define  CAN_F3R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06286 #define  CAN_F3R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06287 #define  CAN_F3R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06288 #define  CAN_F3R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06289 #define  CAN_F3R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06290 #define  CAN_F3R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06291
06292
06293 /*******************  Bit definition for CAN_F4R1 register  *******************/
06294 #define  CAN_F4R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06295 #define  CAN_F4R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06296 #define  CAN_F4R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06297 #define  CAN_F4R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06298 #define  CAN_F4R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06299 #define  CAN_F4R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06300 #define  CAN_F4R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06301 #define  CAN_F4R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06302 #define  CAN_F4R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06303 #define  CAN_F4R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06304 #define  CAN_F4R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06305 #define  CAN_F4R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06306 #define  CAN_F4R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06307 #define  CAN_F4R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06308 #define  CAN_F4R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06309 #define  CAN_F4R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06310 #define  CAN_F4R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06311 #define  CAN_F4R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06312 #define  CAN_F4R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06313 #define  CAN_F4R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06314 #define  CAN_F4R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06315 #define  CAN_F4R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06316 #define  CAN_F4R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06317 #define  CAN_F4R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06318 #define  CAN_F4R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06319 #define  CAN_F4R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06320 #define  CAN_F4R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06321 #define  CAN_F4R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06322 #define  CAN_F4R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06323 #define  CAN_F4R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06324 #define  CAN_F4R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06325 #define  CAN_F4R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06326
06327
06328 /*******************  Bit definition for CAN_F5R1 register  *******************/
06329 #define  CAN_F5R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06330 #define  CAN_F5R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06331 #define  CAN_F5R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06332 #define  CAN_F5R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06333 #define  CAN_F5R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06334 #define  CAN_F5R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06335 #define  CAN_F5R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06336 #define  CAN_F5R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06337 #define  CAN_F5R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06338 #define  CAN_F5R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06339 #define  CAN_F5R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06340 #define  CAN_F5R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06341 #define  CAN_F5R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06342 #define  CAN_F5R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06343 #define  CAN_F5R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06344 #define  CAN_F5R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06345 #define  CAN_F5R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06346 #define  CAN_F5R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06347 #define  CAN_F5R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06348 #define  CAN_F5R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06349 #define  CAN_F5R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06350 #define  CAN_F5R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06351 #define  CAN_F5R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06352 #define  CAN_F5R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06353 #define  CAN_F5R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06354 #define  CAN_F5R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06355 #define  CAN_F5R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06356 #define  CAN_F5R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06357 #define  CAN_F5R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06358 #define  CAN_F5R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06359 #define  CAN_F5R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06360 #define  CAN_F5R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06361
06362
06363 /*******************  Bit definition for CAN_F6R1 register  *******************/
06364 #define  CAN_F6R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06365 #define  CAN_F6R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06366 #define  CAN_F6R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06367 #define  CAN_F6R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06368 #define  CAN_F6R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06369 #define  CAN_F6R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06370 #define  CAN_F6R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06371 #define  CAN_F6R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06372 #define  CAN_F6R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06373 #define  CAN_F6R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06374 #define  CAN_F6R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06375 #define  CAN_F6R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06376 #define  CAN_F6R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06377 #define  CAN_F6R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06378 #define  CAN_F6R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06379 #define  CAN_F6R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06380 #define  CAN_F6R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06381 #define  CAN_F6R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06382 #define  CAN_F6R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06383 #define  CAN_F6R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06384 #define  CAN_F6R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06385 #define  CAN_F6R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06386 #define  CAN_F6R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06387 #define  CAN_F6R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06388 #define  CAN_F6R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06389 #define  CAN_F6R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06390 #define  CAN_F6R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06391 #define  CAN_F6R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06392 #define  CAN_F6R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06393 #define  CAN_F6R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06394 #define  CAN_F6R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06395 #define  CAN_F6R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06396
06397
06398 /*******************  Bit definition for CAN_F7R1 register  *******************/
06399 #define  CAN_F7R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06400 #define  CAN_F7R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06401 #define  CAN_F7R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06402 #define  CAN_F7R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06403 #define  CAN_F7R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06404 #define  CAN_F7R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06405 #define  CAN_F7R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06406 #define  CAN_F7R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06407 #define  CAN_F7R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06408 #define  CAN_F7R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06409 #define  CAN_F7R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06410 #define  CAN_F7R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06411 #define  CAN_F7R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06412 #define  CAN_F7R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06413 #define  CAN_F7R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06414 #define  CAN_F7R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06415 #define  CAN_F7R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06416 #define  CAN_F7R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06417 #define  CAN_F7R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06418 #define  CAN_F7R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06419 #define  CAN_F7R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06420 #define  CAN_F7R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06421 #define  CAN_F7R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06422 #define  CAN_F7R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06423 #define  CAN_F7R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06424 #define  CAN_F7R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06425 #define  CAN_F7R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06426 #define  CAN_F7R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06427 #define  CAN_F7R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06428 #define  CAN_F7R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06429 #define  CAN_F7R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06430 #define  CAN_F7R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06431
06432
06433 /*******************  Bit definition for CAN_F8R1 register  *******************/
06434 #define  CAN_F8R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06435 #define  CAN_F8R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06436 #define  CAN_F8R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06437 #define  CAN_F8R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06438 #define  CAN_F8R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06439 #define  CAN_F8R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06440 #define  CAN_F8R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06441 #define  CAN_F8R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06442 #define  CAN_F8R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06443 #define  CAN_F8R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06444 #define  CAN_F8R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06445 #define  CAN_F8R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06446 #define  CAN_F8R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06447 #define  CAN_F8R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06448 #define  CAN_F8R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06449 #define  CAN_F8R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06450 #define  CAN_F8R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06451 #define  CAN_F8R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06452 #define  CAN_F8R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06453 #define  CAN_F8R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06454 #define  CAN_F8R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06455 #define  CAN_F8R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06456 #define  CAN_F8R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06457 #define  CAN_F8R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06458 #define  CAN_F8R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06459 #define  CAN_F8R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06460 #define  CAN_F8R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06461 #define  CAN_F8R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06462 #define  CAN_F8R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06463 #define  CAN_F8R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06464 #define  CAN_F8R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06465 #define  CAN_F8R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06466
06467
06468 /*******************  Bit definition for CAN_F9R1 register  *******************/
06469 #define  CAN_F9R1_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06470 #define  CAN_F9R1_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06471 #define  CAN_F9R1_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06472 #define  CAN_F9R1_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06473 #define  CAN_F9R1_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06474 #define  CAN_F9R1_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06475 #define  CAN_F9R1_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06476 #define  CAN_F9R1_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06477 #define  CAN_F9R1_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06478 #define  CAN_F9R1_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06479 #define  CAN_F9R1_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06480 #define  CAN_F9R1_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06481 #define  CAN_F9R1_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06482 #define  CAN_F9R1_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06483 #define  CAN_F9R1_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06484 #define  CAN_F9R1_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06485 #define  CAN_F9R1_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06486 #define  CAN_F9R1_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06487 #define  CAN_F9R1_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06488 #define  CAN_F9R1_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06489 #define  CAN_F9R1_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06490 #define  CAN_F9R1_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06491 #define  CAN_F9R1_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06492 #define  CAN_F9R1_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06493 #define  CAN_F9R1_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06494 #define  CAN_F9R1_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06495 #define  CAN_F9R1_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06496 #define  CAN_F9R1_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06497 #define  CAN_F9R1_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06498 #define  CAN_F9R1_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06499 #define  CAN_F9R1_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06500 #define  CAN_F9R1_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06501
06502
06503 /*******************  Bit definition for CAN_F10R1 register  ******************/
06504 #define  CAN_F10R1_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
06505 #define  CAN_F10R1_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
06506 #define  CAN_F10R1_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
06507 #define  CAN_F10R1_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
06508 #define  CAN_F10R1_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
06509 #define  CAN_F10R1_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
06510 #define  CAN_F10R1_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
06511 #define  CAN_F10R1_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
06512 #define  CAN_F10R1_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
06513 #define  CAN_F10R1_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
06514 #define  CAN_F10R1_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
06515 #define  CAN_F10R1_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
06516 #define  CAN_F10R1_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
06517 #define  CAN_F10R1_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
06518 #define  CAN_F10R1_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
06519 #define  CAN_F10R1_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
06520 #define  CAN_F10R1_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
06521 #define  CAN_F10R1_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
06522 #define  CAN_F10R1_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
06523 #define  CAN_F10R1_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
06524 #define  CAN_F10R1_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
06525 #define  CAN_F10R1_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
06526 #define  CAN_F10R1_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
06527 #define  CAN_F10R1_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
06528 #define  CAN_F10R1_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
06529 #define  CAN_F10R1_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
06530 #define  CAN_F10R1_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
06531 #define  CAN_F10R1_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
06532 #define  CAN_F10R1_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
06533 #define  CAN_F10R1_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
06534 #define  CAN_F10R1_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
06535 #define  CAN_F10R1_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
06536
06537
06538 /*******************  Bit definition for CAN_F11R1 register  ******************/
06539 #define  CAN_F11R1_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
06540 #define  CAN_F11R1_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
06541 #define  CAN_F11R1_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
06542 #define  CAN_F11R1_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
06543 #define  CAN_F11R1_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
06544 #define  CAN_F11R1_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
06545 #define  CAN_F11R1_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
06546 #define  CAN_F11R1_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
06547 #define  CAN_F11R1_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
06548 #define  CAN_F11R1_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
06549 #define  CAN_F11R1_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
06550 #define  CAN_F11R1_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
06551 #define  CAN_F11R1_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
06552 #define  CAN_F11R1_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
06553 #define  CAN_F11R1_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
06554 #define  CAN_F11R1_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
06555 #define  CAN_F11R1_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
06556 #define  CAN_F11R1_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
06557 #define  CAN_F11R1_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
06558 #define  CAN_F11R1_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
06559 #define  CAN_F11R1_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
06560 #define  CAN_F11R1_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
06561 #define  CAN_F11R1_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
06562 #define  CAN_F11R1_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
06563 #define  CAN_F11R1_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
06564 #define  CAN_F11R1_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
06565 #define  CAN_F11R1_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
06566 #define  CAN_F11R1_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
06567 #define  CAN_F11R1_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
06568 #define  CAN_F11R1_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
06569 #define  CAN_F11R1_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
06570 #define  CAN_F11R1_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
06571
06572
06573 /*******************  Bit definition for CAN_F12R1 register  ******************/
06574 #define  CAN_F12R1_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
06575 #define  CAN_F12R1_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
06576 #define  CAN_F12R1_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
06577 #define  CAN_F12R1_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
06578 #define  CAN_F12R1_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
06579 #define  CAN_F12R1_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
06580 #define  CAN_F12R1_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
06581 #define  CAN_F12R1_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
06582 #define  CAN_F12R1_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
06583 #define  CAN_F12R1_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
06584 #define  CAN_F12R1_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
06585 #define  CAN_F12R1_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
06586 #define  CAN_F12R1_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
06587 #define  CAN_F12R1_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
06588 #define  CAN_F12R1_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
06589 #define  CAN_F12R1_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
06590 #define  CAN_F12R1_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
06591 #define  CAN_F12R1_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
06592 #define  CAN_F12R1_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
06593 #define  CAN_F12R1_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
06594 #define  CAN_F12R1_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
06595 #define  CAN_F12R1_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
06596 #define  CAN_F12R1_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
06597 #define  CAN_F12R1_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
06598 #define  CAN_F12R1_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
06599 #define  CAN_F12R1_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
06600 #define  CAN_F12R1_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
06601 #define  CAN_F12R1_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
06602 #define  CAN_F12R1_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
06603 #define  CAN_F12R1_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
06604 #define  CAN_F12R1_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
06605 #define  CAN_F12R1_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
06606
06607
06608 /*******************  Bit definition for CAN_F13R1 register  ******************/
06609 #define  CAN_F13R1_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
06610 #define  CAN_F13R1_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
06611 #define  CAN_F13R1_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
06612 #define  CAN_F13R1_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
06613 #define  CAN_F13R1_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
06614 #define  CAN_F13R1_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
06615 #define  CAN_F13R1_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
06616 #define  CAN_F13R1_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
06617 #define  CAN_F13R1_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
06618 #define  CAN_F13R1_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
06619 #define  CAN_F13R1_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
06620 #define  CAN_F13R1_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
06621 #define  CAN_F13R1_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
06622 #define  CAN_F13R1_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
06623 #define  CAN_F13R1_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
06624 #define  CAN_F13R1_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
06625 #define  CAN_F13R1_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
06626 #define  CAN_F13R1_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
06627 #define  CAN_F13R1_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
06628 #define  CAN_F13R1_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
06629 #define  CAN_F13R1_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
06630 #define  CAN_F13R1_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
06631 #define  CAN_F13R1_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
06632 #define  CAN_F13R1_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
06633 #define  CAN_F13R1_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
06634 #define  CAN_F13R1_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
06635 #define  CAN_F13R1_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
06636 #define  CAN_F13R1_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
06637 #define  CAN_F13R1_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
06638 #define  CAN_F13R1_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
06639 #define  CAN_F13R1_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
06640 #define  CAN_F13R1_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
06641
06642
06643 /*******************  Bit definition for CAN_F0R2 register  *******************/
06644 #define  CAN_F0R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06645 #define  CAN_F0R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06646 #define  CAN_F0R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06647 #define  CAN_F0R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06648 #define  CAN_F0R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06649 #define  CAN_F0R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06650 #define  CAN_F0R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06651 #define  CAN_F0R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06652 #define  CAN_F0R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06653 #define  CAN_F0R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06654 #define  CAN_F0R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06655 #define  CAN_F0R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06656 #define  CAN_F0R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06657 #define  CAN_F0R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06658 #define  CAN_F0R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06659 #define  CAN_F0R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06660 #define  CAN_F0R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06661 #define  CAN_F0R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06662 #define  CAN_F0R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06663 #define  CAN_F0R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06664 #define  CAN_F0R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06665 #define  CAN_F0R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06666 #define  CAN_F0R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06667 #define  CAN_F0R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06668 #define  CAN_F0R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06669 #define  CAN_F0R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06670 #define  CAN_F0R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06671 #define  CAN_F0R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06672 #define  CAN_F0R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06673 #define  CAN_F0R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06674 #define  CAN_F0R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06675 #define  CAN_F0R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06676
06677
06678 /*******************  Bit definition for CAN_F1R2 register  *******************/
06679 #define  CAN_F1R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06680 #define  CAN_F1R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06681 #define  CAN_F1R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06682 #define  CAN_F1R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06683 #define  CAN_F1R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06684 #define  CAN_F1R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06685 #define  CAN_F1R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06686 #define  CAN_F1R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06687 #define  CAN_F1R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06688 #define  CAN_F1R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06689 #define  CAN_F1R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06690 #define  CAN_F1R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06691 #define  CAN_F1R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06692 #define  CAN_F1R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06693 #define  CAN_F1R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06694 #define  CAN_F1R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06695 #define  CAN_F1R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06696 #define  CAN_F1R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06697 #define  CAN_F1R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06698 #define  CAN_F1R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06699 #define  CAN_F1R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06700 #define  CAN_F1R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06701 #define  CAN_F1R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06702 #define  CAN_F1R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06703 #define  CAN_F1R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06704 #define  CAN_F1R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06705 #define  CAN_F1R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06706 #define  CAN_F1R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06707 #define  CAN_F1R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06708 #define  CAN_F1R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06709 #define  CAN_F1R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06710 #define  CAN_F1R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06711
06712
06713 /*******************  Bit definition for CAN_F2R2 register  *******************/
06714 #define  CAN_F2R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06715 #define  CAN_F2R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06716 #define  CAN_F2R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06717 #define  CAN_F2R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06718 #define  CAN_F2R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06719 #define  CAN_F2R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06720 #define  CAN_F2R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06721 #define  CAN_F2R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06722 #define  CAN_F2R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06723 #define  CAN_F2R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06724 #define  CAN_F2R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06725 #define  CAN_F2R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06726 #define  CAN_F2R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06727 #define  CAN_F2R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06728 #define  CAN_F2R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06729 #define  CAN_F2R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06730 #define  CAN_F2R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06731 #define  CAN_F2R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06732 #define  CAN_F2R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06733 #define  CAN_F2R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06734 #define  CAN_F2R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06735 #define  CAN_F2R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06736 #define  CAN_F2R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06737 #define  CAN_F2R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06738 #define  CAN_F2R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06739 #define  CAN_F2R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06740 #define  CAN_F2R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06741 #define  CAN_F2R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06742 #define  CAN_F2R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06743 #define  CAN_F2R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06744 #define  CAN_F2R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06745 #define  CAN_F2R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06746
06747
06748 /*******************  Bit definition for CAN_F3R2 register  *******************/
06749 #define  CAN_F3R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06750 #define  CAN_F3R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06751 #define  CAN_F3R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06752 #define  CAN_F3R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06753 #define  CAN_F3R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06754 #define  CAN_F3R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06755 #define  CAN_F3R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06756 #define  CAN_F3R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06757 #define  CAN_F3R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06758 #define  CAN_F3R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06759 #define  CAN_F3R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06760 #define  CAN_F3R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06761 #define  CAN_F3R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06762 #define  CAN_F3R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06763 #define  CAN_F3R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06764 #define  CAN_F3R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06765 #define  CAN_F3R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06766 #define  CAN_F3R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06767 #define  CAN_F3R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06768 #define  CAN_F3R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06769 #define  CAN_F3R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06770 #define  CAN_F3R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06771 #define  CAN_F3R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06772 #define  CAN_F3R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06773 #define  CAN_F3R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06774 #define  CAN_F3R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06775 #define  CAN_F3R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06776 #define  CAN_F3R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06777 #define  CAN_F3R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06778 #define  CAN_F3R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06779 #define  CAN_F3R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06780 #define  CAN_F3R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06781
06782
06783 /*******************  Bit definition for CAN_F4R2 register  *******************/
06784 #define  CAN_F4R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06785 #define  CAN_F4R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06786 #define  CAN_F4R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06787 #define  CAN_F4R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06788 #define  CAN_F4R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06789 #define  CAN_F4R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06790 #define  CAN_F4R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06791 #define  CAN_F4R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06792 #define  CAN_F4R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06793 #define  CAN_F4R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06794 #define  CAN_F4R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06795 #define  CAN_F4R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06796 #define  CAN_F4R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06797 #define  CAN_F4R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06798 #define  CAN_F4R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06799 #define  CAN_F4R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06800 #define  CAN_F4R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06801 #define  CAN_F4R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06802 #define  CAN_F4R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06803 #define  CAN_F4R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06804 #define  CAN_F4R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06805 #define  CAN_F4R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06806 #define  CAN_F4R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06807 #define  CAN_F4R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06808 #define  CAN_F4R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06809 #define  CAN_F4R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06810 #define  CAN_F4R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06811 #define  CAN_F4R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06812 #define  CAN_F4R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06813 #define  CAN_F4R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06814 #define  CAN_F4R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06815 #define  CAN_F4R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06816
06817
06818 /*******************  Bit definition for CAN_F5R2 register  *******************/
06819 #define  CAN_F5R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06820 #define  CAN_F5R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06821 #define  CAN_F5R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06822 #define  CAN_F5R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06823 #define  CAN_F5R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06824 #define  CAN_F5R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06825 #define  CAN_F5R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06826 #define  CAN_F5R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06827 #define  CAN_F5R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06828 #define  CAN_F5R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06829 #define  CAN_F5R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06830 #define  CAN_F5R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06831 #define  CAN_F5R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06832 #define  CAN_F5R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06833 #define  CAN_F5R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06834 #define  CAN_F5R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06835 #define  CAN_F5R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06836 #define  CAN_F5R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06837 #define  CAN_F5R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06838 #define  CAN_F5R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06839 #define  CAN_F5R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06840 #define  CAN_F5R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06841 #define  CAN_F5R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06842 #define  CAN_F5R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06843 #define  CAN_F5R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06844 #define  CAN_F5R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06845 #define  CAN_F5R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06846 #define  CAN_F5R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06847 #define  CAN_F5R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06848 #define  CAN_F5R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06849 #define  CAN_F5R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06850 #define  CAN_F5R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06851
06852
06853 /*******************  Bit definition for CAN_F6R2 register  *******************/
06854 #define  CAN_F6R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06855 #define  CAN_F6R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06856 #define  CAN_F6R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06857 #define  CAN_F6R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06858 #define  CAN_F6R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06859 #define  CAN_F6R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06860 #define  CAN_F6R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06861 #define  CAN_F6R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06862 #define  CAN_F6R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06863 #define  CAN_F6R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06864 #define  CAN_F6R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06865 #define  CAN_F6R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06866 #define  CAN_F6R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06867 #define  CAN_F6R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06868 #define  CAN_F6R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06869 #define  CAN_F6R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06870 #define  CAN_F6R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06871 #define  CAN_F6R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06872 #define  CAN_F6R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06873 #define  CAN_F6R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06874 #define  CAN_F6R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06875 #define  CAN_F6R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06876 #define  CAN_F6R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06877 #define  CAN_F6R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06878 #define  CAN_F6R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06879 #define  CAN_F6R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06880 #define  CAN_F6R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06881 #define  CAN_F6R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06882 #define  CAN_F6R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06883 #define  CAN_F6R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06884 #define  CAN_F6R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06885 #define  CAN_F6R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06886
06887
06888 /*******************  Bit definition for CAN_F7R2 register  *******************/
06889 #define  CAN_F7R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06890 #define  CAN_F7R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06891 #define  CAN_F7R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06892 #define  CAN_F7R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06893 #define  CAN_F7R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06894 #define  CAN_F7R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06895 #define  CAN_F7R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06896 #define  CAN_F7R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06897 #define  CAN_F7R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06898 #define  CAN_F7R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06899 #define  CAN_F7R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06900 #define  CAN_F7R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06901 #define  CAN_F7R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06902 #define  CAN_F7R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06903 #define  CAN_F7R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06904 #define  CAN_F7R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06905 #define  CAN_F7R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06906 #define  CAN_F7R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06907 #define  CAN_F7R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06908 #define  CAN_F7R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06909 #define  CAN_F7R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06910 #define  CAN_F7R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06911 #define  CAN_F7R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06912 #define  CAN_F7R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06913 #define  CAN_F7R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06914 #define  CAN_F7R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06915 #define  CAN_F7R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06916 #define  CAN_F7R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06917 #define  CAN_F7R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06918 #define  CAN_F7R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06919 #define  CAN_F7R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06920 #define  CAN_F7R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06921
06922
06923 /*******************  Bit definition for CAN_F8R2 register  *******************/
06924 #define  CAN_F8R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06925 #define  CAN_F8R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06926 #define  CAN_F8R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06927 #define  CAN_F8R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06928 #define  CAN_F8R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06929 #define  CAN_F8R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06930 #define  CAN_F8R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06931 #define  CAN_F8R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06932 #define  CAN_F8R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06933 #define  CAN_F8R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06934 #define  CAN_F8R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06935 #define  CAN_F8R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06936 #define  CAN_F8R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06937 #define  CAN_F8R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06938 #define  CAN_F8R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06939 #define  CAN_F8R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06940 #define  CAN_F8R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06941 #define  CAN_F8R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06942 #define  CAN_F8R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06943 #define  CAN_F8R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06944 #define  CAN_F8R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06945 #define  CAN_F8R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06946 #define  CAN_F8R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06947 #define  CAN_F8R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06948 #define  CAN_F8R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06949 #define  CAN_F8R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06950 #define  CAN_F8R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06951 #define  CAN_F8R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06952 #define  CAN_F8R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06953 #define  CAN_F8R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06954 #define  CAN_F8R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06955 #define  CAN_F8R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06956
06957
06958 /*******************  Bit definition for CAN_F9R2 register  *******************/
06959 #define  CAN_F9R2_FB0                        ((u32)0x00000001)        /* Filter bit 0 */
06960 #define  CAN_F9R2_FB1                        ((u32)0x00000002)        /* Filter bit 1 */
06961 #define  CAN_F9R2_FB2                        ((u32)0x00000004)        /* Filter bit 2 */
06962 #define  CAN_F9R2_FB3                        ((u32)0x00000008)        /* Filter bit 3 */
06963 #define  CAN_F9R2_FB4                        ((u32)0x00000010)        /* Filter bit 4 */
06964 #define  CAN_F9R2_FB5                        ((u32)0x00000020)        /* Filter bit 5 */
06965 #define  CAN_F9R2_FB6                        ((u32)0x00000040)        /* Filter bit 6 */
06966 #define  CAN_F9R2_FB7                        ((u32)0x00000080)        /* Filter bit 7 */
06967 #define  CAN_F9R2_FB8                        ((u32)0x00000100)        /* Filter bit 8 */
06968 #define  CAN_F9R2_FB9                        ((u32)0x00000200)        /* Filter bit 9 */
06969 #define  CAN_F9R2_FB10                       ((u32)0x00000400)        /* Filter bit 10 */
06970 #define  CAN_F9R2_FB11                       ((u32)0x00000800)        /* Filter bit 11 */
06971 #define  CAN_F9R2_FB12                       ((u32)0x00001000)        /* Filter bit 12 */
06972 #define  CAN_F9R2_FB13                       ((u32)0x00002000)        /* Filter bit 13 */
06973 #define  CAN_F9R2_FB14                       ((u32)0x00004000)        /* Filter bit 14 */
06974 #define  CAN_F9R2_FB15                       ((u32)0x00008000)        /* Filter bit 15 */
06975 #define  CAN_F9R2_FB16                       ((u32)0x00010000)        /* Filter bit 16 */
06976 #define  CAN_F9R2_FB17                       ((u32)0x00020000)        /* Filter bit 17 */
06977 #define  CAN_F9R2_FB18                       ((u32)0x00040000)        /* Filter bit 18 */
06978 #define  CAN_F9R2_FB19                       ((u32)0x00080000)        /* Filter bit 19 */
06979 #define  CAN_F9R2_FB20                       ((u32)0x00100000)        /* Filter bit 20 */
06980 #define  CAN_F9R2_FB21                       ((u32)0x00200000)        /* Filter bit 21 */
06981 #define  CAN_F9R2_FB22                       ((u32)0x00400000)        /* Filter bit 22 */
06982 #define  CAN_F9R2_FB23                       ((u32)0x00800000)        /* Filter bit 23 */
06983 #define  CAN_F9R2_FB24                       ((u32)0x01000000)        /* Filter bit 24 */
06984 #define  CAN_F9R2_FB25                       ((u32)0x02000000)        /* Filter bit 25 */
06985 #define  CAN_F9R2_FB26                       ((u32)0x04000000)        /* Filter bit 26 */
06986 #define  CAN_F9R2_FB27                       ((u32)0x08000000)        /* Filter bit 27 */
06987 #define  CAN_F9R2_FB28                       ((u32)0x10000000)        /* Filter bit 28 */
06988 #define  CAN_F9R2_FB29                       ((u32)0x20000000)        /* Filter bit 29 */
06989 #define  CAN_F9R2_FB30                       ((u32)0x40000000)        /* Filter bit 30 */
06990 #define  CAN_F9R2_FB31                       ((u32)0x80000000)        /* Filter bit 31 */
06991
06992
06993 /*******************  Bit definition for CAN_F10R2 register  ******************/
06994 #define  CAN_F10R2_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
06995 #define  CAN_F10R2_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
06996 #define  CAN_F10R2_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
06997 #define  CAN_F10R2_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
06998 #define  CAN_F10R2_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
06999 #define  CAN_F10R2_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
07000 #define  CAN_F10R2_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
07001 #define  CAN_F10R2_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
07002 #define  CAN_F10R2_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
07003 #define  CAN_F10R2_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
07004 #define  CAN_F10R2_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
07005 #define  CAN_F10R2_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
07006 #define  CAN_F10R2_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
07007 #define  CAN_F10R2_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
07008 #define  CAN_F10R2_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
07009 #define  CAN_F10R2_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
07010 #define  CAN_F10R2_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
07011 #define  CAN_F10R2_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
07012 #define  CAN_F10R2_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
07013 #define  CAN_F10R2_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
07014 #define  CAN_F10R2_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
07015 #define  CAN_F10R2_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
07016 #define  CAN_F10R2_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
07017 #define  CAN_F10R2_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
07018 #define  CAN_F10R2_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
07019 #define  CAN_F10R2_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
07020 #define  CAN_F10R2_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
07021 #define  CAN_F10R2_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
07022 #define  CAN_F10R2_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
07023 #define  CAN_F10R2_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
07024 #define  CAN_F10R2_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
07025 #define  CAN_F10R2_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
07026
07027
07028 /*******************  Bit definition for CAN_F11R2 register  ******************/
07029 #define  CAN_F11R2_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
07030 #define  CAN_F11R2_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
07031 #define  CAN_F11R2_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
07032 #define  CAN_F11R2_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
07033 #define  CAN_F11R2_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
07034 #define  CAN_F11R2_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
07035 #define  CAN_F11R2_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
07036 #define  CAN_F11R2_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
07037 #define  CAN_F11R2_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
07038 #define  CAN_F11R2_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
07039 #define  CAN_F11R2_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
07040 #define  CAN_F11R2_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
07041 #define  CAN_F11R2_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
07042 #define  CAN_F11R2_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
07043 #define  CAN_F11R2_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
07044 #define  CAN_F11R2_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
07045 #define  CAN_F11R2_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
07046 #define  CAN_F11R2_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
07047 #define  CAN_F11R2_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
07048 #define  CAN_F11R2_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
07049 #define  CAN_F11R2_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
07050 #define  CAN_F11R2_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
07051 #define  CAN_F11R2_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
07052 #define  CAN_F11R2_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
07053 #define  CAN_F11R2_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
07054 #define  CAN_F11R2_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
07055 #define  CAN_F11R2_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
07056 #define  CAN_F11R2_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
07057 #define  CAN_F11R2_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
07058 #define  CAN_F11R2_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
07059 #define  CAN_F11R2_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
07060 #define  CAN_F11R2_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
07061
07062
07063 /*******************  Bit definition for CAN_F12R2 register  ******************/
07064 #define  CAN_F12R2_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
07065 #define  CAN_F12R2_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
07066 #define  CAN_F12R2_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
07067 #define  CAN_F12R2_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
07068 #define  CAN_F12R2_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
07069 #define  CAN_F12R2_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
07070 #define  CAN_F12R2_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
07071 #define  CAN_F12R2_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
07072 #define  CAN_F12R2_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
07073 #define  CAN_F12R2_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
07074 #define  CAN_F12R2_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
07075 #define  CAN_F12R2_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
07076 #define  CAN_F12R2_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
07077 #define  CAN_F12R2_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
07078 #define  CAN_F12R2_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
07079 #define  CAN_F12R2_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
07080 #define  CAN_F12R2_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
07081 #define  CAN_F12R2_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
07082 #define  CAN_F12R2_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
07083 #define  CAN_F12R2_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
07084 #define  CAN_F12R2_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
07085 #define  CAN_F12R2_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
07086 #define  CAN_F12R2_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
07087 #define  CAN_F12R2_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
07088 #define  CAN_F12R2_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
07089 #define  CAN_F12R2_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
07090 #define  CAN_F12R2_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
07091 #define  CAN_F12R2_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
07092 #define  CAN_F12R2_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
07093 #define  CAN_F12R2_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
07094 #define  CAN_F12R2_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
07095 #define  CAN_F12R2_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
07096
07097
07098 /*******************  Bit definition for CAN_F13R2 register  ******************/
07099 #define  CAN_F13R2_FB0                       ((u32)0x00000001)        /* Filter bit 0 */
07100 #define  CAN_F13R2_FB1                       ((u32)0x00000002)        /* Filter bit 1 */
07101 #define  CAN_F13R2_FB2                       ((u32)0x00000004)        /* Filter bit 2 */
07102 #define  CAN_F13R2_FB3                       ((u32)0x00000008)        /* Filter bit 3 */
07103 #define  CAN_F13R2_FB4                       ((u32)0x00000010)        /* Filter bit 4 */
07104 #define  CAN_F13R2_FB5                       ((u32)0x00000020)        /* Filter bit 5 */
07105 #define  CAN_F13R2_FB6                       ((u32)0x00000040)        /* Filter bit 6 */
07106 #define  CAN_F13R2_FB7                       ((u32)0x00000080)        /* Filter bit 7 */
07107 #define  CAN_F13R2_FB8                       ((u32)0x00000100)        /* Filter bit 8 */
07108 #define  CAN_F13R2_FB9                       ((u32)0x00000200)        /* Filter bit 9 */
07109 #define  CAN_F13R2_FB10                      ((u32)0x00000400)        /* Filter bit 10 */
07110 #define  CAN_F13R2_FB11                      ((u32)0x00000800)        /* Filter bit 11 */
07111 #define  CAN_F13R2_FB12                      ((u32)0x00001000)        /* Filter bit 12 */
07112 #define  CAN_F13R2_FB13                      ((u32)0x00002000)        /* Filter bit 13 */
07113 #define  CAN_F13R2_FB14                      ((u32)0x00004000)        /* Filter bit 14 */
07114 #define  CAN_F13R2_FB15                      ((u32)0x00008000)        /* Filter bit 15 */
07115 #define  CAN_F13R2_FB16                      ((u32)0x00010000)        /* Filter bit 16 */
07116 #define  CAN_F13R2_FB17                      ((u32)0x00020000)        /* Filter bit 17 */
07117 #define  CAN_F13R2_FB18                      ((u32)0x00040000)        /* Filter bit 18 */
07118 #define  CAN_F13R2_FB19                      ((u32)0x00080000)        /* Filter bit 19 */
07119 #define  CAN_F13R2_FB20                      ((u32)0x00100000)        /* Filter bit 20 */
07120 #define  CAN_F13R2_FB21                      ((u32)0x00200000)        /* Filter bit 21 */
07121 #define  CAN_F13R2_FB22                      ((u32)0x00400000)        /* Filter bit 22 */
07122 #define  CAN_F13R2_FB23                      ((u32)0x00800000)        /* Filter bit 23 */
07123 #define  CAN_F13R2_FB24                      ((u32)0x01000000)        /* Filter bit 24 */
07124 #define  CAN_F13R2_FB25                      ((u32)0x02000000)        /* Filter bit 25 */
07125 #define  CAN_F13R2_FB26                      ((u32)0x04000000)        /* Filter bit 26 */
07126 #define  CAN_F13R2_FB27                      ((u32)0x08000000)        /* Filter bit 27 */
07127 #define  CAN_F13R2_FB28                      ((u32)0x10000000)        /* Filter bit 28 */
07128 #define  CAN_F13R2_FB29                      ((u32)0x20000000)        /* Filter bit 29 */
07129 #define  CAN_F13R2_FB30                      ((u32)0x40000000)        /* Filter bit 30 */
07130 #define  CAN_F13R2_FB31                      ((u32)0x80000000)        /* Filter bit 31 */
07131
07132
07133
07134 /******************************************************************************/
07135 /*                                                                            */
07136 /*                        Serial Peripheral Interface                         */
07137 /*                                                                            */
07138 /******************************************************************************/
07139
07140 /*******************  Bit definition for SPI_CR1 register  ********************/
07141 #define  SPI_CR1_CPHA                        ((u16)0x0001)            /* Clock Phase */
07142 #define  SPI_CR1_CPOL                        ((u16)0x0002)            /* Clock Polarity */
07143 #define  SPI_CR1_MSTR                        ((u16)0x0004)            /* Master Selection */
07144
07145 #define  SPI_CR1_BR                          ((u16)0x0038)            /* BR[2:0] bits (Baud Rate Control) */
07146 #define  SPI_CR1_BR_0                        ((u16)0x0008)            /* Bit 0 */
07147 #define  SPI_CR1_BR_1                        ((u16)0x0010)            /* Bit 1 */
07148 #define  SPI_CR1_BR_2                        ((u16)0x0020)            /* Bit 2 */
07149
07150 #define  SPI_CR1_SPE                         ((u16)0x0040)            /* SPI Enable */
07151 #define  SPI_CR1_LSBFIRST                    ((u16)0x0080)            /* Frame Format */
07152 #define  SPI_CR1_SSI                         ((u16)0x0100)            /* Internal slave select */
07153 #define  SPI_CR1_SSM                         ((u16)0x0200)            /* Software slave management */
07154 #define  SPI_CR1_RXONLY                      ((u16)0x0400)            /* Receive only */
07155 #define  SPI_CR1_DFF                         ((u16)0x0800)            /* Data Frame Format */
07156 #define  SPI_CR1_CRCNEXT                     ((u16)0x1000)            /* Transmit CRC next */
07157 #define  SPI_CR1_CRCEN                       ((u16)0x2000)            /* Hardware CRC calculation enable */
07158 #define  SPI_CR1_BIDIOE                      ((u16)0x4000)            /* Output enable in bidirectional mode */
07159 #define  SPI_CR1_BIDIMODE                    ((u16)0x8000)            /* Bidirectional data mode enable */
07160
07161
07162 /*******************  Bit definition for SPI_CR2 register  ********************/
07163 #define  SPI_CR2_RXDMAEN                     ((u8)0x01)               /* Rx Buffer DMA Enable */
07164 #define  SPI_CR2_TXDMAEN                     ((u8)0x02)               /* Tx Buffer DMA Enable */
07165 #define  SPI_CR2_SSOE                        ((u8)0x04)               /* SS Output Enable */
07166 #define  SPI_CR2_ERRIE                       ((u8)0x20)               /* Error Interrupt Enable */
07167 #define  SPI_CR2_RXNEIE                      ((u8)0x40)               /* RX buffer Not Empty Interrupt Enable */
07168 #define  SPI_CR2_TXEIE                       ((u8)0x80)               /* Tx buffer Empty Interrupt Enable */
07169
07170
07171 /********************  Bit definition for SPI_SR register  ********************/
07172 #define  SPI_SR_RXNE                         ((u8)0x01)               /* Receive buffer Not Empty */
07173 #define  SPI_SR_TXE                          ((u8)0x02)               /* Transmit buffer Empty */
07174 #define  SPI_SR_CHSIDE                       ((u8)0x04)               /* Channel side */
07175 #define  SPI_SR_UDR                          ((u8)0x08)               /* Underrun flag */
07176 #define  SPI_SR_CRCERR                       ((u8)0x10)               /* CRC Error flag */
07177 #define  SPI_SR_MODF                         ((u8)0x20)               /* Mode fault */
07178 #define  SPI_SR_OVR                          ((u8)0x40)               /* Overrun flag */
07179 #define  SPI_SR_BSY                          ((u8)0x80)               /* Busy flag */
07180
07181
07182 /********************  Bit definition for SPI_DR register  ********************/
07183 #define  SPI_DR_DR                           ((u16)0xFFFF)            /* Data Register */
07184
07185
07186 /*******************  Bit definition for SPI_CRCPR register  ******************/
07187 #define  SPI_CRCPR_CRCPOLY                   ((u16)0xFFFF)            /* CRC polynomial register */
07188
07189
07190 /******************  Bit definition for SPI_RXCRCR register  ******************/
07191 #define  SPI_RXCRCR_RXCRC                    ((u16)0xFFFF)            /* Rx CRC Register */
07192
07193
07194 /******************  Bit definition for SPI_TXCRCR register  ******************/
07195 #define  SPI_TXCRCR_TXCRC                    ((u16)0xFFFF)            /* Tx CRC Register */
07196
07197
07198 /******************  Bit definition for SPI_I2SCFGR register  *****************/
07199 #define  SPI_I2SCFGR_CHLEN                   ((u16)0x0001)            /* Channel length (number of bits per audio channel) */
07200
07201 #define  SPI_I2SCFGR_DATLEN                  ((u16)0x0006)            /* DATLEN[1:0] bits (Data length to be transferred) */
07202 #define  SPI_I2SCFGR_DATLEN_0                ((u16)0x0002)            /* Bit 0 */
07203 #define  SPI_I2SCFGR_DATLEN_1                ((u16)0x0004)            /* Bit 1 */
07204
07205 #define  SPI_I2SCFGR_CKPOL                   ((u16)0x0008)            /* steady state clock polarity */
07206
07207 #define  SPI_I2SCFGR_I2SSTD                  ((u16)0x0030)            /* I2SSTD[1:0] bits (I2S standard selection) */
07208 #define  SPI_I2SCFGR_I2SSTD_0                ((u16)0x0010)            /* Bit 0 */
07209 #define  SPI_I2SCFGR_I2SSTD_1                ((u16)0x0020)            /* Bit 1 */
07210
07211 #define  SPI_I2SCFGR_PCMSYNC                 ((u16)0x0080)            /* PCM frame synchronization */
07212
07213 #define  SPI_I2SCFGR_I2SCFG                  ((u16)0x0300)            /* I2SCFG[1:0] bits (I2S configuration mode) */
07214 #define  SPI_I2SCFGR_I2SCFG_0                ((u16)0x0100)            /* Bit 0 */
07215 #define  SPI_I2SCFGR_I2SCFG_1                ((u16)0x0200)            /* Bit 1 */
07216
07217 #define  SPI_I2SCFGR_I2SE                    ((u16)0x0400)            /* I2S Enable */
07218 #define  SPI_I2SCFGR_I2SMOD                  ((u16)0x0800)            /* I2S mode selection */
07219
07220
07221 /******************  Bit definition for SPI_I2SPR register  *******************/
07222 #define  SPI_I2SPR_I2SDIV                    ((u16)0x00FF)            /* I2S Linear prescaler */
07223 #define  SPI_I2SPR_ODD                       ((u16)0x0100)            /* Odd factor for the prescaler */
07224 #define  SPI_I2SPR_MCKOE                     ((u16)0x0200)            /* Master Clock Output Enable */
07225
07226
07227
07228 /******************************************************************************/
07229 /*                                                                            */
07230 /*                      Inter-integrated Circuit Interface                    */
07231 /*                                                                            */
07232 /******************************************************************************/
07233
07234 /*******************  Bit definition for I2C_CR1 register  ********************/
07235 #define  I2C_CR1_PE                          ((u16)0x0001)            /* Peripheral Enable */
07236 #define  I2C_CR1_SMBUS                       ((u16)0x0002)            /* SMBus Mode */
07237 #define  I2C_CR1_SMBTYPE                     ((u16)0x0008)            /* SMBus Type */
07238 #define  I2C_CR1_ENARP                       ((u16)0x0010)            /* ARP Enable */
07239 #define  I2C_CR1_ENPEC                       ((u16)0x0020)            /* PEC Enable */
07240 #define  I2C_CR1_ENGC                        ((u16)0x0040)            /* General Call Enable */
07241 #define  I2C_CR1_NOSTRETCH                   ((u16)0x0080)            /* Clock Stretching Disable (Slave mode) */
07242 #define  I2C_CR1_START                       ((u16)0x0100)            /* Start Generation */
07243 #define  I2C_CR1_STOP                        ((u16)0x0200)            /* Stop Generation */
07244 #define  I2C_CR1_ACK                         ((u16)0x0400)            /* Acknowledge Enable */
07245 #define  I2C_CR1_POS                         ((u16)0x0800)            /* Acknowledge/PEC Position (for data reception) */
07246 #define  I2C_CR1_PEC                         ((u16)0x1000)            /* Packet Error Checking */
07247 #define  I2C_CR1_ALERT                       ((u16)0x2000)            /* SMBus Alert */
07248 #define  I2C_CR1_SWRST                       ((u16)0x8000)            /* Software Reset */
07249
07250
07251 /*******************  Bit definition for I2C_CR2 register  ********************/
07252 #define  I2C_CR2_FREQ                        ((u16)0x003F)            /* FREQ[5:0] bits (Peripheral Clock Frequency) */
07253 #define  I2C_CR2_FREQ_0                      ((u16)0x0001)            /* Bit 0 */
07254 #define  I2C_CR2_FREQ_1                      ((u16)0x0002)            /* Bit 1 */
07255 #define  I2C_CR2_FREQ_2                      ((u16)0x0004)            /* Bit 2 */
07256 #define  I2C_CR2_FREQ_3                      ((u16)0x0008)            /* Bit 3 */
07257 #define  I2C_CR2_FREQ_4                      ((u16)0x0010)            /* Bit 4 */
07258 #define  I2C_CR2_FREQ_5                      ((u16)0x0020)            /* Bit 5 */
07259
07260 #define  I2C_CR2_ITERREN                     ((u16)0x0100)            /* Error Interrupt Enable */
07261 #define  I2C_CR2_ITEVTEN                     ((u16)0x0200)            /* Event Interrupt Enable */
07262 #define  I2C_CR2_ITBUFEN                     ((u16)0x0400)            /* Buffer Interrupt Enable */
07263 #define  I2C_CR2_DMAEN                       ((u16)0x0800)            /* DMA Requests Enable */
07264 #define  I2C_CR2_LAST                        ((u16)0x1000)            /* DMA Last Transfer */
07265
07266
07267 /*******************  Bit definition for I2C_OAR1 register  *******************/
07268 #define  I2C_OAR1_ADD1_7                     ((u16)0x00FE)            /* Interface Address */
07269 #define  I2C_OAR1_ADD8_9                     ((u16)0x0300)            /* Interface Address */
07270
07271 #define  I2C_OAR1_ADD0                       ((u16)0x0001)            /* Bit 0 */
07272 #define  I2C_OAR1_ADD1                       ((u16)0x0002)            /* Bit 1 */
07273 #define  I2C_OAR1_ADD2                       ((u16)0x0004)            /* Bit 2 */
07274 #define  I2C_OAR1_ADD3                       ((u16)0x0008)            /* Bit 3 */
07275 #define  I2C_OAR1_ADD4                       ((u16)0x0010)            /* Bit 4 */
07276 #define  I2C_OAR1_ADD5                       ((u16)0x0020)            /* Bit 5 */
07277 #define  I2C_OAR1_ADD6                       ((u16)0x0040)            /* Bit 6 */
07278 #define  I2C_OAR1_ADD7                       ((u16)0x0080)            /* Bit 7 */
07279 #define  I2C_OAR1_ADD8                       ((u16)0x0100)            /* Bit 8 */
07280 #define  I2C_OAR1_ADD9                       ((u16)0x0200)            /* Bit 9 */
07281
07282 #define  I2C_OAR1_ADDMODE                    ((u16)0x8000)            /* Addressing Mode (Slave mode) */
07283
07284
07285 /*******************  Bit definition for I2C_OAR2 register  *******************/
07286 #define  I2C_OAR2_ENDUAL                     ((u8)0x01)               /* Dual addressing mode enable */
07287 #define  I2C_OAR2_ADD2                       ((u8)0xFE)               /* Interface address */
07288
07289
07290 /********************  Bit definition for I2C_DR register  ********************/
07291 #define  I2C_DR_DR                           ((u8)0xFF)               /* 8-bit Data Register */
07292
07293
07294 /*******************  Bit definition for I2C_SR1 register  ********************/
07295 #define  I2C_SR1_SB                          ((u16)0x0001)            /* Start Bit (Master mode) */
07296 #define  I2C_SR1_ADDR                        ((u16)0x0002)            /* Address sent (master mode)/matched (slave mode) */
07297 #define  I2C_SR1_BTF                         ((u16)0x0004)            /* Byte Transfer Finished */
07298 #define  I2C_SR1_ADD10                       ((u16)0x0008)            /* 10-bit header sent (Master mode) */
07299 #define  I2C_SR1_STOPF                       ((u16)0x0010)            /* Stop detection (Slave mode) */
07300 #define  I2C_SR1_RXNE                        ((u16)0x0040)            /* Data Register not Empty (receivers) */
07301 #define  I2C_SR1_TXE                         ((u16)0x0080)            /* Data Register Empty (transmitters) */
07302 #define  I2C_SR1_BERR                        ((u16)0x0100)            /* Bus Error */
07303 #define  I2C_SR1_ARLO                        ((u16)0x0200)            /* Arbitration Lost (master mode) */
07304 #define  I2C_SR1_AF                          ((u16)0x0400)            /* Acknowledge Failure */
07305 #define  I2C_SR1_OVR                         ((u16)0x0800)            /* Overrun/Underrun */
07306 #define  I2C_SR1_PECERR                      ((u16)0x1000)            /* PEC Error in reception */
07307 #define  I2C_SR1_TIMEOUT                     ((u16)0x4000)            /* Timeout or Tlow Error */
07308 #define  I2C_SR1_SMBALERT                    ((u16)0x8000)            /* SMBus Alert */
07309
07310
07311 /*******************  Bit definition for I2C_SR2 register  ********************/
07312 #define  I2C_SR2_MSL                         ((u16)0x0001)            /* Master/Slave */
07313 #define  I2C_SR2_BUSY                        ((u16)0x0002)            /* Bus Busy */
07314 #define  I2C_SR2_TRA                         ((u16)0x0004)            /* Transmitter/Receiver */
07315 #define  I2C_SR2_GENCALL                     ((u16)0x0010)            /* General Call Address (Slave mode) */
07316 #define  I2C_SR2_SMBDEFAULT                  ((u16)0x0020)            /* SMBus Device Default Address (Slave mode) */
07317 #define  I2C_SR2_SMBHOST                     ((u16)0x0040)            /* SMBus Host Header (Slave mode) */
07318 #define  I2C_SR2_DUALF                       ((u16)0x0080)            /* Dual Flag (Slave mode) */
07319 #define  I2C_SR2_PEC                         ((u16)0xFF00)            /* Packet Error Checking Register */
07320
07321
07322 /*******************  Bit definition for I2C_CCR register  ********************/
07323 #define  I2C_CCR_CCR                         ((u16)0x0FFF)            /* Clock Control Register in Fast/Standard mode (Master mode) */
07324 #define  I2C_CCR_DUTY                        ((u16)0x4000)            /* Fast Mode Duty Cycle */
07325 #define  I2C_CCR_FS                          ((u16)0x8000)            /* I2C Master Mode Selection */
07326
07327
07328 /******************  Bit definition for I2C_TRISE register  *******************/
07329 #define  I2C_TRISE_TRISE                     ((u8)0x3F)               /* Maximum Rise Time in Fast/Standard mode (Master mode) */
07330
07331
07332
07333 /******************************************************************************/
07334 /*                                                                            */
07335 /*          Universal Synchronous Asynchronous Receiver Transmitter           */
07336 /*                                                                            */
07337 /******************************************************************************/
07338
07339 /*******************  Bit definition for USART_SR register  *******************/
07340 #define  USART_SR_PE                         ((u16)0x0001)            /* Parity Error */
07341 #define  USART_SR_FE                         ((u16)0x0002)            /* Framing Error */
07342 #define  USART_SR_NE                         ((u16)0x0004)            /* Noise Error Flag */
07343 #define  USART_SR_ORE                        ((u16)0x0008)            /* OverRun Error */
07344 #define  USART_SR_IDLE                       ((u16)0x0010)            /* IDLE line detected */
07345 #define  USART_SR_RXNE                       ((u16)0x0020)            /* Read Data Register Not Empty */
07346 #define  USART_SR_TC                         ((u16)0x0040)            /* Transmission Complete */
07347 #define  USART_SR_TXE                        ((u16)0x0080)            /* Transmit Data Register Empty */
07348 #define  USART_SR_LBD                        ((u16)0x0100)            /* LIN Break Detection Flag */
07349 #define  USART_SR_CTS                        ((u16)0x0200)            /* CTS Flag */
07350
07351
07352 /*******************  Bit definition for USART_DR register  *******************/
07353 #define  USART_DR_DR                         ((u16)0x01FF)            /* Data value */
07354
07355
07356 /******************  Bit definition for USART_BRR register  *******************/
07357 #define  USART_BRR_DIV_Fraction              ((u16)0x000F)            /* Fraction of USARTDIV */
07358 #define  USART_BRR_DIV_Mantissa              ((u16)0xFFF0)            /* Mantissa of USARTDIV */
07359
07360
07361 /******************  Bit definition for USART_CR1 register  *******************/
07362 #define  USART_CR1_SBK                       ((u16)0x0001)            /* Send Break */
07363 #define  USART_CR1_RWU                       ((u16)0x0002)            /* Receiver wakeup */
07364 #define  USART_CR1_RE                        ((u16)0x0004)            /* Receiver Enable */
07365 #define  USART_CR1_TE                        ((u16)0x0008)            /* Transmitter Enable */
07366 #define  USART_CR1_IDLEIE                    ((u16)0x0010)            /* IDLE Interrupt Enable */
07367 #define  USART_CR1_RXNEIE                    ((u16)0x0020)            /* RXNE Interrupt Enable */
07368 #define  USART_CR1_TCIE                      ((u16)0x0040)            /* Transmission Complete Interrupt Enable */
07369 #define  USART_CR1_TXEIE                     ((u16)0x0080)            /* PE Interrupt Enable */
07370 #define  USART_CR1_PEIE                      ((u16)0x0100)            /* PE Interrupt Enable */
07371 #define  USART_CR1_PS                        ((u16)0x0200)            /* Parity Selection */
07372 #define  USART_CR1_PCE                       ((u16)0x0400)            /* Parity Control Enable */
07373 #define  USART_CR1_WAKE                      ((u16)0x0800)            /* Wakeup method */
07374 #define  USART_CR1_M                         ((u16)0x1000)            /* Word length */
07375 #define  USART_CR1_UE                        ((u16)0x2000)            /* USART Enable */
07376
07377
07378 /******************  Bit definition for USART_CR2 register  *******************/
07379 #define  USART_CR2_ADD                       ((u16)0x000F)            /* Address of the USART node */
07380 #define  USART_CR2_LBDL                      ((u16)0x0020)            /* LIN Break Detection Length */
07381 #define  USART_CR2_LBDIE                     ((u16)0x0040)            /* LIN Break Detection Interrupt Enable */
07382 #define  USART_CR2_LBCL                      ((u16)0x0100)            /* Last Bit Clock pulse */
07383 #define  USART_CR2_CPHA                      ((u16)0x0200)            /* Clock Phase */
07384 #define  USART_CR2_CPOL                      ((u16)0x0400)            /* Clock Polarity */
07385 #define  USART_CR2_CLKEN                     ((u16)0x0800)            /* Clock Enable */
07386
07387 #define  USART_CR2_STOP                      ((u16)0x3000)            /* STOP[1:0] bits (STOP bits) */
07388 #define  USART_CR2_STOP_0                    ((u16)0x1000)            /* Bit 0 */
07389 #define  USART_CR2_STOP_1                    ((u16)0x2000)            /* Bit 1 */
07390
07391 #define  USART_CR2_LINEN                     ((u16)0x4000)            /* LIN mode enable */
07392
07393
07394 /******************  Bit definition for USART_CR3 register  *******************/
07395 #define  USART_CR3_EIE                       ((u16)0x0001)            /* Error Interrupt Enable */
07396 #define  USART_CR3_IREN                      ((u16)0x0002)            /* IrDA mode Enable */
07397 #define  USART_CR3_IRLP                      ((u16)0x0004)            /* IrDA Low-Power */
07398 #define  USART_CR3_HDSEL                     ((u16)0x0008)            /* Half-Duplex Selection */
07399 #define  USART_CR3_NACK                      ((u16)0x0010)            /* Smartcard NACK enable */
07400 #define  USART_CR3_SCEN                      ((u16)0x0020)            /* Smartcard mode enable */
07401 #define  USART_CR3_DMAR                      ((u16)0x0040)            /* DMA Enable Receiver */
07402 #define  USART_CR3_DMAT                      ((u16)0x0080)            /* DMA Enable Transmitter */
07403 #define  USART_CR3_RTSE                      ((u16)0x0100)            /* RTS Enable */
07404 #define  USART_CR3_CTSE                      ((u16)0x0200)            /* CTS Enable */
07405 #define  USART_CR3_CTSIE                     ((u16)0x0400)            /* CTS Interrupt Enable */
07406
07407
07408 /******************  Bit definition for USART_GTPR register  ******************/
07409 #define  USART_GTPR_PSC                      ((u16)0x00FF)            /* PSC[7:0] bits (Prescaler value) */
07410 #define  USART_GTPR_PSC_0                    ((u16)0x0001)            /* Bit 0 */
07411 #define  USART_GTPR_PSC_1                    ((u16)0x0002)            /* Bit 1 */
07412 #define  USART_GTPR_PSC_2                    ((u16)0x0004)            /* Bit 2 */
07413 #define  USART_GTPR_PSC_3                    ((u16)0x0008)            /* Bit 3 */
07414 #define  USART_GTPR_PSC_4                    ((u16)0x0010)            /* Bit 4 */
07415 #define  USART_GTPR_PSC_5                    ((u16)0x0020)            /* Bit 5 */
07416 #define  USART_GTPR_PSC_6                    ((u16)0x0040)            /* Bit 6 */
07417 #define  USART_GTPR_PSC_7                    ((u16)0x0080)            /* Bit 7 */
07418
07419 #define  USART_GTPR_GT                       ((u16)0xFF00)            /* Guard time value */
07420
07421
07422
07423 /******************************************************************************/
07424 /*                                                                            */
07425 /*                                 Debug MCU                                  */
07426 /*                                                                            */
07427 /******************************************************************************/
07428
07429 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
07430 #define  DBGMCU_IDCODE_DEV_ID                ((u32)0x00000FFF)        /* Device Identifier */
07431
07432 #define  DBGMCU_IDCODE_REV_ID                ((u32)0xFFFF0000)        /* REV_ID[15:0] bits (Revision Identifier) */
07433 #define  DBGMCU_IDCODE_REV_ID_0              ((u32)0x00010000)        /* Bit 0 */
07434 #define  DBGMCU_IDCODE_REV_ID_1              ((u32)0x00020000)        /* Bit 1 */
07435 #define  DBGMCU_IDCODE_REV_ID_2              ((u32)0x00040000)        /* Bit 2 */
07436 #define  DBGMCU_IDCODE_REV_ID_3              ((u32)0x00080000)        /* Bit 3 */
07437 #define  DBGMCU_IDCODE_REV_ID_4              ((u32)0x00100000)        /* Bit 4 */
07438 #define  DBGMCU_IDCODE_REV_ID_5              ((u32)0x00200000)        /* Bit 5 */
07439 #define  DBGMCU_IDCODE_REV_ID_6              ((u32)0x00400000)        /* Bit 6 */
07440 #define  DBGMCU_IDCODE_REV_ID_7              ((u32)0x00800000)        /* Bit 7 */
07441 #define  DBGMCU_IDCODE_REV_ID_8              ((u32)0x01000000)        /* Bit 8 */
07442 #define  DBGMCU_IDCODE_REV_ID_9              ((u32)0x02000000)        /* Bit 9 */
07443 #define  DBGMCU_IDCODE_REV_ID_10             ((u32)0x04000000)        /* Bit 10 */
07444 #define  DBGMCU_IDCODE_REV_ID_11             ((u32)0x08000000)        /* Bit 11 */
07445 #define  DBGMCU_IDCODE_REV_ID_12             ((u32)0x10000000)        /* Bit 12 */
07446 #define  DBGMCU_IDCODE_REV_ID_13             ((u32)0x20000000)        /* Bit 13 */
07447 #define  DBGMCU_IDCODE_REV_ID_14             ((u32)0x40000000)        /* Bit 14 */
07448 #define  DBGMCU_IDCODE_REV_ID_15             ((u32)0x80000000)        /* Bit 15 */
07449
07450
07451 /******************  Bit definition for DBGMCU_CR register  *******************/
07452 #define  DBGMCU_CR_DBG_SLEEP                 ((u32)0x00000001)        /* Debug Sleep Mode */
07453 #define  DBGMCU_CR_DBG_STOP                  ((u32)0x00000002)        /* Debug Stop Mode */
07454 #define  DBGMCU_CR_DBG_STANDBY               ((u32)0x00000004)        /* Debug Standby mode */
07455 #define  DBGMCU_CR_TRACE_IOEN                ((u32)0x00000020)        /* Trace Pin Assignment Control */
07456
07457 #define  DBGMCU_CR_TRACE_MODE                ((u32)0x000000C0)        /* TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
07458 #define  DBGMCU_CR_TRACE_MODE_0              ((u32)0x00000040)        /* Bit 0 */
07459 #define  DBGMCU_CR_TRACE_MODE_1              ((u32)0x00000080)        /* Bit 1 */
07460
07461 #define  DBGMCU_CR_DBG_IWDG_STOP             ((u32)0x00000100)        /* Debug Independent Watchdog stopped when Core is halted */
07462 #define  DBGMCU_CR_DBG_WWDG_STOP             ((u32)0x00000200)        /* Debug Window Watchdog stopped when Core is halted */
07463 #define  DBGMCU_CR_DBG_TIM1_STOP             ((u32)0x00000400)        /* TIM1 counter stopped when core is halted */
07464 #define  DBGMCU_CR_DBG_TIM2_STOP             ((u32)0x00000800)        /* TIM2 counter stopped when core is halted */
07465 #define  DBGMCU_CR_DBG_TIM3_STOP             ((u32)0x00001000)        /* TIM3 counter stopped when core is halted */
07466 #define  DBGMCU_CR_DBG_TIM4_STOP             ((u32)0x00002000)        /* TIM4 counter stopped when core is halted */
07467 #define  DBGMCU_CR_DBG_CAN_STOP              ((u32)0x00004000)        /* Debug CAN stopped when Core is halted */
07468 #define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((u32)0x00008000)        /* SMBUS timeout mode stopped when Core is halted */
07469 #define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((u32)0x00010000)        /* SMBUS timeout mode stopped when Core is halted */
07470 #define  DBGMCU_CR_DBG_TIM5_STOP             ((u32)0x00020000)        /* TIM5 counter stopped when core is halted */
07471 #define  DBGMCU_CR_DBG_TIM6_STOP             ((u32)0x00040000)        /* TIM6 counter stopped when core is halted */
07472 #define  DBGMCU_CR_DBG_TIM7_STOP             ((u32)0x00080000)        /* TIM7 counter stopped when core is halted */
07473 #define  DBGMCU_CR_DBG_TIM8_STOP             ((u32)0x00100000)        /* TIM8 counter stopped when core is halted */
07474
07475
07476
07477 /******************************************************************************/
07478 /*                                                                            */
07479 /*                      FLASH and Option Bytes Registers                      */
07480 /*                                                                            */
07481 /******************************************************************************/
07482
07483 /*******************  Bit definition for FLASH_ACR register  ******************/
07484 #define  FLASH_ACR_LATENCY                   ((u8)0x07)               /* LATENCY[2:0] bits (Latency) */
07485 #define  FLASH_ACR_LATENCY_0                 ((u8)0x01)               /* Bit 0 */
07486 #define  FLASH_ACR_LATENCY_1                 ((u8)0x02)               /* Bit 1 */
07487 #define  FLASH_ACR_LATENCY_2                 ((u8)0x04)               /* Bit 2 */
07488
07489 #define  FLASH_ACR_HLFCYA                    ((u8)0x08)               /* Flash Half Cycle Access Enable */
07490 #define  FLASH_ACR_PRFTBE                    ((u8)0x10)               /* Prefetch Buffer Enable */
07491 #define  FLASH_ACR_PRFTBS                    ((u8)0x20)               /* Prefetch Buffer Status */
07492
07493
07494 /******************  Bit definition for FLASH_KEYR register  ******************/
07495 #define  FLASH_KEYR_FKEYR                    ((u32)0xFFFFFFFF)        /* FPEC Key */
07496
07497
07498 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
07499 #define  FLASH_OPTKEYR_OPTKEYR               ((u32)0xFFFFFFFF)        /* Option Byte Key */
07500
07501
07502 /******************  Bit definition for FLASH_SR register  *******************/
07503 #define  FLASH_SR_BSY                        ((u8)0x01)               /* Busy */
07504 #define  FLASH_SR_PGERR                      ((u8)0x04)               /* Programming Error */
07505 #define  FLASH_SR_WRPRTERR                   ((u8)0x10)               /* Write Protection Error */
07506 #define  FLASH_SR_EOP                        ((u8)0x20)               /* End of operation */
07507
07508
07509 /*******************  Bit definition for FLASH_CR register  *******************/
07510 #define  FLASH_CR_PG                         ((u16)0x0001)            /* Programming */
07511 #define  FLASH_CR_PER                        ((u16)0x0002)            /* Page Erase */
07512 #define  FLASH_CR_MER                        ((u16)0x0004)            /* Mass Erase */
07513 #define  FLASH_CR_OPTPG                      ((u16)0x0010)            /* Option Byte Programming */
07514 #define  FLASH_CR_OPTER                      ((u16)0x0020)            /* Option Byte Erase */
07515 #define  FLASH_CR_STRT                       ((u16)0x0040)            /* Start */
07516 #define  FLASH_CR_LOCK                       ((u16)0x0080)            /* Lock */
07517 #define  FLASH_CR_OPTWRE                     ((u16)0x0200)            /* Option Bytes Write Enable */
07518 #define  FLASH_CR_ERRIE                      ((u16)0x0400)            /* Error Interrupt Enable */
07519 #define  FLASH_CR_EOPIE                      ((u16)0x1000)            /* End of operation interrupt enable */
07520
07521
07522 /*******************  Bit definition for FLASH_AR register  *******************/
07523 #define  FLASH_AR_FAR                        ((u32)0xFFFFFFFF)        /* Flash Address */
07524
07525
07526 /******************  Bit definition for FLASH_OBR register  *******************/
07527 #define  FLASH_OBR_OPTERR                    ((u16)0x0001)            /* Option Byte Error */
07528 #define  FLASH_OBR_RDPRT                     ((u16)0x0002)            /* Read protection */
07529
07530 #define  FLASH_OBR_USER                      ((u16)0x03FC)            /* User Option Bytes */
07531 #define  FLASH_OBR_WDG_SW                    ((u16)0x0004)            /* WDG_SW */
07532 #define  FLASH_OBR_nRST_STOP                 ((u16)0x0008)            /* nRST_STOP */
07533 #define  FLASH_OBR_nRST_STDBY                ((u16)0x0010)            /* nRST_STDBY */
07534 #define  FLASH_OBR_Notused                   ((u16)0x03E0)            /* Not used */
07535
07536
07537 /******************  Bit definition for FLASH_WRPR register  ******************/
07538 #define  FLASH_WRPR_WRP                        ((u32)0xFFFFFFFF)        /* Write Protect */
07539
07540
07541 /*----------------------------------------------------------------------------*/
07542
07543
07544 /******************  Bit definition for FLASH_RDP register  *******************/
07545 #define  FLASH_RDP_RDP                       ((u32)0x000000FF)        /* Read protection option byte */
07546 #define  FLASH_RDP_nRDP                      ((u32)0x0000FF00)        /* Read protection complemented option byte */
07547
07548
07549 /******************  Bit definition for FLASH_USER register  ******************/
07550 #define  FLASH_USER_USER                     ((u32)0x00FF0000)        /* User option byte */
07551 #define  FLASH_USER_nUSER                    ((u32)0xFF000000)        /* User complemented option byte */
07552
07553
07554 /******************  Bit definition for FLASH_Data0 register  *****************/
07555 #define  FLASH_Data0_Data0                   ((u32)0x000000FF)        /* User data storage option byte */
07556 #define  FLASH_Data0_nData0                  ((u32)0x0000FF00)        /* User data storage complemented option byte */
07557
07558
07559 /******************  Bit definition for FLASH_Data1 register  *****************/
07560 #define  FLASH_Data1_Data1                   ((u32)0x00FF0000)        /* User data storage option byte */
07561 #define  FLASH_Data1_nData1                  ((u32)0xFF000000)        /* User data storage complemented option byte */
07562
07563
07564 /******************  Bit definition for FLASH_WRP0 register  ******************/
07565 #define  FLASH_WRP0_WRP0                     ((u32)0x000000FF)        /* Flash memory write protection option bytes */
07566 #define  FLASH_WRP0_nWRP0                    ((u32)0x0000FF00)        /* Flash memory write protection complemented option bytes */
07567
07568
07569 /******************  Bit definition for FLASH_WRP1 register  ******************/
07570 #define  FLASH_WRP1_WRP1                     ((u32)0x00FF0000)        /* Flash memory write protection option bytes */
07571 #define  FLASH_WRP1_nWRP1                    ((u32)0xFF000000)        /* Flash memory write protection complemented option bytes */
07572
07573
07574 /******************  Bit definition for FLASH_WRP2 register  ******************/
07575 #define  FLASH_WRP2_WRP2                     ((u32)0x000000FF)        /* Flash memory write protection option bytes */
07576 #define  FLASH_WRP2_nWRP2                    ((u32)0x0000FF00)        /* Flash memory write protection complemented option bytes */
07577
07578
07579 /******************  Bit definition for FLASH_WRP3 register  ******************/
07580 #define  FLASH_WRP3_WRP3                     ((u32)0x00FF0000)        /* Flash memory write protection option bytes */
07581 #define  FLASH_WRP3_nWRP3                    ((u32)0xFF000000)        /* Flash memory write protection complemented option bytes */
07582
07583
07584 /* Exported macro ------------------------------------------------------------*/
07585 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
07586
07587 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
07588
07589 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
07590
07591 #define CLEAR_REG(REG)        ((REG) = 0x0)
07592
07593 #define WRITE_REG(REG, VAL)   ((REG) = VAL)
07594
07595 #define READ_REG(REG)         ((REG))
07596
07597 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK)))
07598
07599 /* Exported functions ------------------------------------------------------- */
07600
07601 #endif /* __STM32F10x_MAP_H */
07602
07603 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/