Contiki 2.6

clock.c

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00001 /*
00002  * Copyright (c) 2012, Swedish Institute of Computer Science.
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the Institute nor the names of its contributors
00014  *    may be used to endorse or promote products derived from this software
00015  *    without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
00018  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00020  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
00021  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00022  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00023  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00024  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00027  * SUCH DAMAGE.
00028  *
00029  * This file is part of the Contiki operating system.
00030  *
00031  */
00032  /**
00033  *  \brief This module contains AVR-specific code to implement
00034  *  the Contiki core clock functions.
00035  *  
00036  *  \author David Kopf <dak664@embarqmail.com> and others.
00037  *
00038 */
00039 /** \addtogroup avr
00040  * @{
00041  */
00042  /**
00043  *  \defgroup avrclock AVR clock implementation
00044  * @{
00045  */
00046 /**
00047  *  \file
00048  *  This file contains AVR-specific code to implement the Contiki core clock functions.
00049  *
00050  */
00051 /**
00052  * These routines define the AVR-specific calls declared in /core/sys/clock.h
00053  * CLOCK_SECOND is the number of ticks per second.
00054  * It is defined through CONF_CLOCK_SECOND in the contiki-conf.h for each platform.
00055  * The usual AVR defaults are 128 or 125 ticks per second, counting a prescaled CPU clock
00056  * using the 8 bit timer0.
00057  * 
00058  * clock_time_t is usually declared by the platform as an unsigned 16 bit data type,
00059  * thus intervals up to 512 or 524 seconds can be measured with ~8 millisecond precision.
00060  * For longer intervals the 32 bit clock_seconds() is available.
00061  * 
00062  * Since a carry to a higer byte can occur during an interrupt, declaring them non-static
00063  * for direct examination can cause occasional time reversals!
00064  *
00065  * clock-avr.h contains the specific setup code for each mcu.
00066  */
00067 #include "sys/clock.h"
00068 #include "dev/clock-avr.h"
00069 #include "sys/etimer.h"
00070 
00071 #include <avr/io.h>
00072 #include <avr/interrupt.h>
00073 
00074 /* Two tick counters avoid a software divide when CLOCK_SECOND is not a power of two. */
00075 #if CLOCK_SECOND && (CLOCK_SECOND - 1)
00076 #define TWO_COUNTERS 1
00077 #endif
00078 
00079 /* count is usually a 16 bit variable, although the platform can declare it otherwise */
00080 static volatile clock_time_t count;
00081 #if TWO_COUNTERS
00082 /* scount is the 8 bit counter that counts ticks modulo CLOCK_SECONDS */
00083 static volatile uint8_t scount;
00084 #endif
00085 /* seconds is available globally but non-atomic update during interrupt can cause time reversals */
00086 volatile unsigned long seconds;
00087 /* sleepseconds is the number of seconds sleeping since startup, available globally */
00088 long sleepseconds;
00089 
00090 /* Set RADIOSTATS to monitor radio on time (must also be set in the radio driver) */
00091 #if RF230BB && AVR_WEBSERVER
00092 #define RADIOSTATS 1
00093 #endif
00094 
00095 #if RADIOSTATS
00096 static volatile uint8_t rcount;
00097 volatile unsigned long radioontime;
00098 extern uint8_t RF230_receive_on;
00099 #endif
00100 
00101 /* Set RADIO_CONF_CALIBRATE_INTERVAL for periodic calibration of the PLL during extended radio on time.
00102  * The RF230 data sheet suggests every 5 minutes if the temperature is fluctuating.
00103  * At present the specified interval is ignored, and an 8 bit counter gives 256 second intervals.
00104  * Actual calibration is done by the driver on the next transmit request.
00105  */
00106 #if RADIO_CONF_CALIBRATE_INTERVAL
00107 extern volatile uint8_t rf230_calibrate;
00108 static uint8_t calibrate_interval;
00109 #endif
00110 
00111 /*---------------------------------------------------------------------------*/
00112 /**
00113  * Start the clock by enabling the timer comparison interrupts. 
00114  */
00115 void
00116 clock_init(void)
00117 {
00118   cli ();
00119   OCRSetup();
00120   sei ();
00121 }
00122 /*---------------------------------------------------------------------------*/
00123 /**
00124  * Return the tick counter. When 16 bit it typically wraps every 10 minutes.
00125  * The comparison avoids the need to disable clock interrupts for an atomic
00126  * read of the multi-byte variable.
00127  */
00128 clock_time_t
00129 clock_time(void)
00130 {
00131   clock_time_t tmp;
00132   do {
00133     tmp = count;
00134   } while(tmp != count);
00135   return tmp;
00136 }
00137 /*---------------------------------------------------------------------------*/
00138 /**
00139  * Return seconds, default is time since startup.
00140  * The comparison avoids the need to disable clock interrupts for an atomic
00141  * read of the four-byte variable.
00142  */
00143 unsigned long
00144 clock_seconds(void)
00145 {
00146   unsigned long tmp;
00147   do {
00148     tmp = seconds;
00149   } while(tmp != seconds);
00150   return tmp;
00151 }
00152 /*---------------------------------------------------------------------------*/
00153 /**
00154  * Set seconds, e.g. to a standard epoch for an absolute date/time.
00155  */
00156 void
00157 clock_set_seconds(unsigned long sec)
00158 {
00159   seconds = sec;
00160 }
00161 /*---------------------------------------------------------------------------*/
00162 /**
00163  * Wait for a number of clock ticks.
00164  */
00165 void
00166 clock_wait(clock_time_t t)
00167 {
00168   clock_time_t endticks = clock_time() + t;
00169   if (sizeof(clock_time_t) == 1) {
00170     while ((signed char )(clock_time() - endticks) < 0) {;}
00171   } else if (sizeof(clock_time_t) == 2) {
00172     while ((signed short)(clock_time() - endticks) < 0) {;}
00173   } else {
00174     while ((signed long )(clock_time() - endticks) < 0) {;}
00175   }
00176 }
00177 /*---------------------------------------------------------------------------*/
00178 /**
00179  * Delay the CPU for up to 65535*(4000000/F_CPU) microseconds.
00180  * Copied from _delay_loop_2 in AVR library delay_basic.h, 4 clocks per loop.
00181  * For accurate short delays, inline _delay_loop_2 in the caller, use a constant
00182  * value for the delay, and disable interrupts if necessary.
00183  */
00184 static inline void my_delay_loop_2(uint16_t __count) __attribute__((always_inline));
00185 void
00186 my_delay_loop_2(uint16_t __count)
00187 {
00188   __asm__ volatile (
00189     "1: sbiw %0,1" "\n\t"
00190     "brne 1b"
00191     : "=w" (__count)
00192     : "0" (__count)
00193   );
00194 }
00195 void
00196 clock_delay_usec(uint16_t howlong)
00197 {
00198 #if 0
00199 /* Accurate delay at any frequency, but introduces a 64 bit intermediate
00200   * and has a 279 clock overhead.
00201  */
00202   if(howlong<=(uint16_t)(279000000UL/F_CPU)) return;
00203   howlong-=(uint16_t) (279000000UL/F_CPU);
00204   my_delay_loop_2(((uint64_t)(howlong) * (uint64_t) F_CPU) / 4000000ULL);
00205   /* Remaining numbers tweaked for the breakpoint CPU frequencies */
00206   /* Add other frequencies as necessary */
00207 #elif F_CPU>=16000000UL
00208   if(howlong<1) return;
00209   my_delay_loop_2((howlong*(uint16_t)(F_CPU/3250000)));
00210 #elif F_CPU >= 12000000UL
00211   if(howlong<2) return;
00212   howlong-=(uint16_t) (3*12000000/F_CPU);
00213   my_delay_loop_2((howlong*(uint16_t)(F_CPU/3250000)));
00214 #elif F_CPU >= 8000000UL
00215   if(howlong<4) return;
00216   howlong-=(uint16_t) (3*8000000/F_CPU);
00217   my_delay_loop_2((howlong*(uint16_t)(F_CPU/2000000))/2);
00218 #elif F_CPU >= 4000000UL
00219   if(howlong<5) return;
00220   howlong-=(uint16_t) (4*4000000/F_CPU);
00221   my_delay_loop_2((howlong*(uint16_t)(F_CPU/2000000))/2);
00222 #elif F_CPU >= 2000000UL
00223   if(howlong<11) return;
00224   howlong-=(uint16_t) (10*2000000/F_CPU);
00225   my_delay_loop_2((howlong*(uint16_t)(F_CPU/1000000))/4);
00226 #elif F_CPU >= 1000000UL
00227   if(howlong<=17) return;
00228   howlong-=(uint16_t) (17*1000000/F_CPU);
00229   my_delay_loop_2((howlong*(uint16_t)(F_CPU/1000000))/4);
00230 #else
00231   howlong >> 5;
00232   if (howlong < 1) return;
00233   my_delay_loop_2(howlong);
00234 #endif
00235 }
00236 #if 0
00237 /*---------------------------------------------------------------------------*/
00238 /**
00239  * Legacy delay. The original clock_delay for the msp430 used a granularity
00240  * of 2.83 usec. This approximates that delay for values up to 1456 usec.
00241  * (The largest core call in leds.c uses 400).
00242  */
00243 void
00244 clock_delay(unsigned int howlong)
00245 {
00246   if(howlong<2) return;
00247   clock_delay_usec((45*howlong)>>4);
00248 }
00249 #endif
00250 /*---------------------------------------------------------------------------*/
00251 /**
00252  * Delay up to 65535 milliseconds.
00253  * \param dt   How many milliseconds to delay.
00254  *
00255  * Neither interrupts nor the watchdog timer is disabled over the delay.
00256  * Platforms are not required to implement this call.
00257  * \note This will break for CPUs clocked above 260 MHz.
00258  */
00259 void
00260 clock_delay_msec(uint16_t howlong)
00261 {
00262 
00263 #if F_CPU>=16000000
00264   while(howlong--) clock_delay_usec(1000);
00265 #elif F_CPU>=8000000
00266   uint16_t i=996;
00267   while(howlong--) {clock_delay_usec(i);i=999;}
00268 #elif F_CPU>=4000000
00269   uint16_t i=992;
00270   while(howlong--) {clock_delay_usec(i);i=999;}
00271 #elif F_CPU>=2000000
00272   uint16_t i=989;
00273   while(howlong--) {clock_delay_usec(i);i=999;}
00274 #else
00275   uint16_t i=983;
00276   while(howlong--) {clock_delay_usec(i);i=999;}
00277 #endif
00278 }
00279 /*---------------------------------------------------------------------------*/
00280 /**
00281  * Adjust the system current clock time.
00282  * \param dt   How many ticks to add
00283  *
00284  * Typically used to add ticks after an MCU sleep
00285  * clock_seconds will increment if necessary to reflect the tick addition.
00286   * Leap ticks or seconds can (rarely) be introduced if the ISR is not blocked.
00287  */
00288 void
00289 clock_adjust_ticks(clock_time_t howmany)
00290 {
00291   uint8_t sreg = SREG;cli();
00292   count  += howmany;
00293 #if TWO_COUNTERS
00294   howmany+= scount;
00295 #endif
00296   while(howmany >= CLOCK_SECOND) {
00297     howmany -= CLOCK_SECOND;
00298     seconds++;
00299     sleepseconds++;
00300 #if RADIOSTATS
00301     if (RF230_receive_on) radioontime += 1;
00302 #endif
00303   }
00304 #if TWO_COUNTERS
00305   scount = howmany;
00306 #endif
00307   SREG=sreg;
00308 }
00309 /*---------------------------------------------------------------------------*/
00310 /* This it the timer comparison match interrupt.
00311  * It maintains the tick counter, clock_seconds, and etimer updates.
00312  *
00313  * If the interrupts derive from an external crystal, the CPU instruction
00314  * clock can optionally be phase locked to it. This allows accurate rtimer
00315  * interrupts for strobe detection during radio duty cycling.
00316  * Phase lock is accomplished by adjusting OSCCAL based on the phase error
00317  * since the last interrupt.
00318  */
00319 /*---------------------------------------------------------------------------*/
00320 #if defined(DOXYGEN)
00321 /** \brief ISR for the TIMER0 or TIMER2 interrupt as defined in
00322  *  clock-avr.h for the particular MCU.
00323  */
00324 void AVR_OUTPUT_COMPARE_INT(void);
00325 #else
00326 ISR(AVR_OUTPUT_COMPARE_INT)
00327 {
00328     count++;
00329 #if TWO_COUNTERS
00330   if(++scount >= CLOCK_SECOND) {
00331     scount = 0;
00332 #else
00333   if(count%CLOCK_SECOND==0) {
00334 #endif
00335     seconds++;
00336 
00337 #if RADIO_CONF_CALIBRATE_INTERVAL
00338    /* Force a radio PLL frequency calibration every 256 seconds */
00339     if (++calibrate_interval==0) {
00340       rf230_calibrate=1;
00341     }
00342 #endif
00343 
00344   }
00345 
00346 #if RADIOSTATS
00347    /* Sample radio on time. Less accurate than ENERGEST but a smaller footprint */
00348   if (RF230_receive_on) {
00349     if (++rcount >= CLOCK_SECOND) {
00350       rcount=0;
00351       radioontime++;
00352     }
00353   }
00354 #endif
00355  
00356 #if F_CPU == 0x800000 && USE_32K_CRYSTAL
00357 /* Special routine to phase lock CPU to 32768 watch crystal.
00358  * We are interrupting 128 times per second.
00359  * If RTIMER_ARCH_SECOND is a multiple of 128 we can use the residual modulo
00360  * 128 to determine whether the clock is too fast or too slow.
00361  * E.g. for 8192 the phase should be constant modulo 0x40
00362  * OSCCAL is started in the lower range at 90, allowed to stabilize, then
00363  * rapidly raised or lowered based on the phase comparison.
00364  * It gives less phase noise to do this every tick and doesn't seem to hurt anything.
00365  */
00366 #include "rtimer-arch.h"
00367 {
00368 volatile static uint8_t lockcount;
00369 volatile static int16_t last_phase;
00370 volatile static uint8_t osccalhigh,osccallow;
00371   if (seconds < 60) { //give a minute to stabilize
00372     if(++lockcount >= 8192UL*128/RTIMER_ARCH_SECOND) {
00373       lockcount=0;
00374       rtimer_phase = TCNT3 & 0x0fff;
00375       if (seconds < 2) OSCCAL=100;
00376       if (last_phase > rtimer_phase) osccalhigh=++OSCCAL; else osccallow=--OSCCAL;
00377       last_phase = rtimer_phase;
00378     }
00379   } else {
00380     uint8_t error = (TCNT3 - last_phase) & 0x3f;
00381     if (error == 0) {
00382     } else if (error<32) {
00383       OSCCAL=osccallow-1;
00384     } else {
00385       OSCCAL=osccalhigh+1;
00386     }
00387   }
00388 }
00389 #endif
00390 
00391 #if 1
00392 /*  gcc will save all registers on the stack if an external routine is called */
00393   if(etimer_pending()) {
00394     etimer_request_poll();
00395   }
00396 #else
00397 /* doing this locally saves 9 pushes and 9 pops, but these etimer.c and process.c variables have to lose the static qualifier */
00398   extern struct etimer *timerlist;
00399   extern volatile unsigned char poll_requested;
00400 
00401 #define PROCESS_STATE_NONE        0
00402 #define PROCESS_STATE_RUNNING     1
00403 #define PROCESS_STATE_CALLED      2
00404 
00405   if (timerlist) {
00406     if(etimer_process.state == PROCESS_STATE_RUNNING || etimer_process.state == PROCESS_STATE_CALLED) {
00407       etimer_process.needspoll = 1;
00408       poll_requested = 1;
00409     }
00410   }
00411 #endif
00412 }
00413 #endif /* defined(DOXYGEN) */
00414 /*---------------------------------------------------------------------------*/
00415 /* Debugging aids */
00416 
00417 #ifdef HANDLE_UNSUPPORTED_INTERRUPTS
00418 /* Ignore unsupported interrupts, optionally hang for debugging */
00419 /* BADISR is a gcc weak symbol that matches any undefined interrupt */
00420 ISR(BADISR_vect) {
00421 //static volatile uint8_t x;while (1) x++;
00422 }
00423 #endif
00424 #ifdef HANG_ON_UNKNOWN_INTERRUPT
00425 /* Hang on any unsupported interrupt */
00426 /* Useful for diagnosing unknown interrupts that reset the mcu.
00427  * Currently set up for 12mega128rfa1.
00428  * For other mcus, enable all and then disable the conflicts.
00429  */
00430 static volatile uint8_t x;
00431 ISR( _VECTOR(0)) {while (1) x++;}
00432 ISR( _VECTOR(1)) {while (1) x++;}
00433 ISR( _VECTOR(2)) {while (1) x++;}
00434 ISR( _VECTOR(3)) {while (1) x++;}
00435 ISR( _VECTOR(4)) {while (1) x++;}
00436 ISR( _VECTOR(5)) {while (1) x++;}
00437 ISR( _VECTOR(6)) {while (1) x++;}
00438 ISR( _VECTOR(7)) {while (1) x++;}
00439 ISR( _VECTOR(8)) {while (1) x++;}
00440 ISR( _VECTOR(9)) {while (1) x++;}
00441 ISR( _VECTOR(10)) {while (1) x++;}
00442 ISR( _VECTOR(11)) {while (1) x++;}
00443 ISR( _VECTOR(12)) {while (1) x++;}
00444 ISR( _VECTOR(13)) {while (1) x++;}
00445 ISR( _VECTOR(14)) {while (1) x++;}
00446 ISR( _VECTOR(15)) {while (1) x++;}
00447 ISR( _VECTOR(16)) {while (1) x++;}
00448 ISR( _VECTOR(17)) {while (1) x++;}
00449 ISR( _VECTOR(18)) {while (1) x++;}
00450 ISR( _VECTOR(19)) {while (1) x++;}
00451 //ISR( _VECTOR(20)) {while (1) x++;}
00452 //ISR( _VECTOR(21)) {while (1) x++;}
00453 ISR( _VECTOR(22)) {while (1) x++;}
00454 ISR( _VECTOR(23)) {while (1) x++;}
00455 ISR( _VECTOR(24)) {while (1) x++;}
00456 //ISR( _VECTOR(25)) {while (1) x++;}
00457 ISR( _VECTOR(26)) {while (1) x++;}
00458 //ISR( _VECTOR(27)) {while (1) x++;}
00459 ISR( _VECTOR(28)) {while (1) x++;}
00460 ISR( _VECTOR(29)) {while (1) x++;}
00461 ISR( _VECTOR(30)) {while (1) x++;}
00462 ISR( _VECTOR(31)) {while (1) x++;}
00463 //ISR( _VECTOR(32)) {while (1) x++;}
00464 ISR( _VECTOR(33)) {while (1) x++;}
00465 ISR( _VECTOR(34)) {while (1) x++;}
00466 ISR( _VECTOR(35)) {while (1) x++;}
00467 //ISR( _VECTOR(36)) {while (1) x++;}
00468 ISR( _VECTOR(37)) {while (1) x++;}
00469 //ISR( _VECTOR(38)) {while (1) x++;}
00470 ISR( _VECTOR(39)) {while (1) x++;}
00471 ISR( _VECTOR(40)) {while (1) x++;}
00472 ISR( _VECTOR(41)) {while (1) x++;}
00473 ISR( _VECTOR(42)) {while (1) x++;}
00474 ISR( _VECTOR(43)) {while (1) x++;}
00475 ISR( _VECTOR(44)) {while (1) x++;}
00476 ISR( _VECTOR(45)) {while (1) x++;}
00477 ISR( _VECTOR(46)) {while (1) x++;}
00478 ISR( _VECTOR(47)) {while (1) x++;}
00479 ISR( _VECTOR(48)) {while (1) x++;}
00480 ISR( _VECTOR(49)) {while (1) x++;}
00481 ISR( _VECTOR(50)) {while (1) x++;}
00482 ISR( _VECTOR(51)) {while (1) x++;}
00483 ISR( _VECTOR(52)) {while (1) x++;}
00484 ISR( _VECTOR(53)) {while (1) x++;}
00485 ISR( _VECTOR(54)) {while (1) x++;}
00486 ISR( _VECTOR(55)) {while (1) x++;}
00487 ISR( _VECTOR(56)) {while (1) x++;}
00488 //ISR( _VECTOR(57)) {while (1) x++;}
00489 //ISR( _VECTOR(58)) {while (1) x++;}
00490 //ISR( _VECTOR(59)) {while (1) x++;}
00491 //ISR( _VECTOR(60)) {while (1) x++;}
00492 ISR( _VECTOR(61)) {while (1) x++;}
00493 ISR( _VECTOR(62)) {while (1) x++;}
00494 ISR( _VECTOR(63)) {while (1) x++;}
00495 ISR( _VECTOR(64)) {while (1) x++;}
00496 ISR( _VECTOR(65)) {while (1) x++;}
00497 ISR( _VECTOR(66)) {while (1) x++;}
00498 ISR( _VECTOR(67)) {while (1) x++;}
00499 ISR( _VECTOR(68)) {while (1) x++;}
00500 ISR( _VECTOR(69)) {while (1) x++;}
00501 ISR( _VECTOR(70)) {while (1) x++;}
00502 ISR( _VECTOR(71)) {while (1) x++;}
00503 ISR( _VECTOR(72)) {while (1) x++;}
00504 ISR( _VECTOR(73)) {while (1) x++;}
00505 ISR( _VECTOR(74)) {while (1) x++;}
00506 ISR( _VECTOR(75)) {while (1) x++;}
00507 ISR( _VECTOR(76)) {while (1) x++;}
00508 ISR( _VECTOR(77)) {while (1) x++;}
00509 ISR( _VECTOR(78)) {while (1) x++;}
00510 ISR( _VECTOR(79)) {while (1) x++;}
00511 #endif
00512 /** @} */
00513 /** @} */