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00001 /* 00002 * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors 00003 * to the MC1322x project (http://mc1322x.devl.org) 00004 * All rights reserved. 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 1. Redistributions of source code must retain the above copyright 00010 * notice, this list of conditions and the following disclaimer. 00011 * 2. Redistributions in binary form must reproduce the above copyright 00012 * notice, this list of conditions and the following disclaimer in the 00013 * documentation and/or other materials provided with the distribution. 00014 * 3. Neither the name of the Institute nor the names of its contributors 00015 * may be used to endorse or promote products derived from this software 00016 * without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 00019 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00020 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00021 * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 00022 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00023 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 00024 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 00025 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00026 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00027 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00028 * SUCH DAMAGE. 00029 * 00030 * This file is part of libmc1322x: see http://mc1322x.devl.org 00031 * for details. 00032 * 00033 * 00034 */ 00035 00036 #ifndef UART_H 00037 #define UART_H 00038 00039 #include <stdint.h> 00040 00041 /* Timer registers are all 16-bit wide with 16-bit access only */ 00042 #define UART1_BASE (0x80005000) 00043 #define UART2_BASE (0x8000B000) 00044 00045 struct UART_struct { 00046 union { 00047 uint32_t CON; 00048 struct UART_CON { 00049 uint32_t :16; 00050 uint32_t TST:1; 00051 uint32_t MRXR:1; 00052 uint32_t MTXR:1; 00053 uint32_t FCE:1; 00054 uint32_t FCP:1; 00055 uint32_t XTIM:1; 00056 uint32_t :2; 00057 uint32_t TXOENB:1; 00058 uint32_t CONTX:1; 00059 uint32_t SB:1; 00060 uint32_t ST2:1; 00061 uint32_t EP:1; 00062 uint32_t PEN:1; 00063 uint32_t RXE:1; 00064 uint32_t TXE:1; 00065 } CONbits; 00066 }; 00067 union { 00068 uint32_t STAT; 00069 struct UART_STAT { 00070 uint32_t :24; 00071 uint32_t TXRDY:1; 00072 uint32_t RXRDY:1; 00073 uint32_t RUE:1; 00074 uint32_t ROE:1; 00075 uint32_t TOE:1; 00076 uint32_t FE:1; 00077 uint32_t PE:1; 00078 uint32_t SE:1; 00079 } USTATbits; 00080 }; 00081 union { 00082 uint32_t DATA; 00083 struct UART_DATA { 00084 uint32_t :24; 00085 uint32_t DATA:8; 00086 } DATAbits; 00087 }; 00088 union { 00089 uint32_t RXCON; 00090 struct UART_URXCON { 00091 uint32_t :26; 00092 uint32_t LVL:6; 00093 } RXCONbits; 00094 }; 00095 union { 00096 uint32_t TXCON; 00097 struct UART_TXCON { 00098 uint32_t :26; 00099 uint32_t LVL:6; 00100 } TXCONbits; 00101 }; 00102 union { 00103 uint32_t CTS; 00104 struct UART_CTS { 00105 uint32_t :27; 00106 uint32_t LVL:5; 00107 } CTSbits; 00108 }; 00109 union { 00110 uint32_t BR; 00111 struct UART_BR { 00112 uint32_t INC:16; 00113 uint32_t MOD:16; 00114 } BRbits; 00115 }; 00116 }; 00117 00118 static volatile struct UART_struct * const UART1 = (void *) (UART1_BASE); 00119 static volatile struct UART_struct * const UART2 = (void *) (UART2_BASE); 00120 00121 /* Old uart definitions, for compatibility */ 00122 #ifndef REG_NO_COMPAT 00123 00124 #define UCON (0) 00125 /* UCON bits */ 00126 #define UCON_SAMP 10 00127 #define UCON_SAMP_8X 0 00128 #define UCON_SAMP_16X 1 00129 00130 #define USTAT (0x04) 00131 #define UDATA (0x08) 00132 #define URXCON (0x0c) 00133 #define UTXCON (0x10) 00134 #define UCTS (0x14) 00135 #define UBRCNT (0x18) 00136 00137 #define UART1_UCON ((volatile uint32_t *) ( UART1_BASE + UCON )) 00138 #define UART1_USTAT ((volatile uint32_t *) ( UART1_BASE + USTAT )) 00139 #define UART1_UDATA ((volatile uint32_t *) ( UART1_BASE + UDATA )) 00140 #define UART1_URXCON ((volatile uint32_t *) ( UART1_BASE + URXCON )) 00141 #define UART1_UTXCON ((volatile uint32_t *) ( UART1_BASE + UTXCON )) 00142 #define UART1_UCTS ((volatile uint32_t *) ( UART1_BASE + UCTS )) 00143 #define UART1_UBRCNT ((volatile uint32_t *) ( UART1_BASE + UBRCNT )) 00144 00145 #define UART2_UCON ((volatile uint32_t *) ( UART2_BASE + UCON )) 00146 #define UART2_USTAT ((volatile uint32_t *) ( UART2_BASE + USTAT )) 00147 #define UART2_UDATA ((volatile uint32_t *) ( UART2_BASE + UDATA )) 00148 #define UART2_URXCON ((volatile uint32_t *) ( UART2_BASE + URXCON )) 00149 #define UART2_UTXCON ((volatile uint32_t *) ( UART2_BASE + UTXCON )) 00150 #define UART2_UCTS ((volatile uint32_t *) ( UART2_BASE + UCTS )) 00151 #define UART2_UBRCNT ((volatile uint32_t *) ( UART2_BASE + UBRCNT )) 00152 00153 #endif /* REG_NO_COMPAT */ 00154 00155 /* The mc1322x has a 32 byte hardware FIFO for transmitted characters. 00156 * Currently it is always filled from a larger RAM buffer. It would be 00157 * possible to eliminate that overhead by filling directly from a chain 00158 * of data buffer pointers, but printf's would be not so easy. 00159 */ 00160 #define UART1_TX_BUFFERSIZE 1024 00161 extern volatile uint32_t u1_tx_head, u1_tx_tail; 00162 void uart1_putc(char c); 00163 00164 /* The mc1322x has a 32 byte hardware FIFO for received characters. 00165 * If a larger rx buffersize is specified the FIFO will be extended into RAM. 00166 * RAM transfers will occur on interrupt when the FIFO is nearly full. 00167 * If a smaller buffersize is specified hardware flow control will be 00168 * initiated at that FIFO level. 00169 * Set to 32 for no flow control or RAM buffer. 00170 */ 00171 #define UART1_RX_BUFFERSIZE 128 00172 #if UART1_RX_BUFFERSIZE > 32 00173 extern volatile uint32_t u1_rx_head, u1_rx_tail; 00174 #define uart1_can_get() ((u1_rx_head!=u1_rx_tail) || (*UART1_URXCON > 0)) 00175 #else 00176 #define uart1_can_get() (*UART1_URXCON > 0) 00177 #endif 00178 uint8_t uart1_getc(void); 00179 00180 00181 #define UART2_TX_BUFFERSIZE 1024 00182 extern volatile uint32_t u2_tx_head, u2_tx_tail; 00183 void uart2_putc(char c); 00184 00185 #define UART2_RX_BUFFERSIZE 128 00186 #if UART2_RX_BUFFERSIZE > 32 00187 extern volatile uint32_t u2_rx_head, u2_rx_tail; 00188 #define uart2_can_get() ((u2_rx_head!=u2_rx_tail) || (*UART2_URXCON > 0)) 00189 #else 00190 #define uart2_can_get() (*UART2_URXCON > 0) 00191 #endif 00192 uint8_t uart2_getc(void); 00193 00194 #endif