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00001 /* 00002 * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors 00003 * to the MC1322x project (http://mc1322x.devl.org) 00004 * All rights reserved. 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 1. Redistributions of source code must retain the above copyright 00010 * notice, this list of conditions and the following disclaimer. 00011 * 2. Redistributions in binary form must reproduce the above copyright 00012 * notice, this list of conditions and the following disclaimer in the 00013 * documentation and/or other materials provided with the distribution. 00014 * 3. Neither the name of the Institute nor the names of its contributors 00015 * may be used to endorse or promote products derived from this software 00016 * without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 00019 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00020 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00021 * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 00022 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00023 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 00024 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 00025 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00026 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00027 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00028 * SUCH DAMAGE. 00029 * 00030 * This file is part of libmc1322x: see http://mc1322x.devl.org 00031 * for details. 00032 * 00033 * 00034 */ 00035 00036 #ifndef CRM_H 00037 #define CRM_H 00038 00039 #include <stdint.h> 00040 00041 #define CRM_BASE (0x80003000) 00042 00043 /* Structure-based CRM access */ 00044 struct CRM_struct { 00045 union { 00046 uint32_t SYS_CNTL; 00047 struct CRM_SYS_CNTL { 00048 uint32_t PWR_SOURCE:2; 00049 uint32_t PADS_1P8V_SEL:1; 00050 uint32_t :1; 00051 uint32_t JTAG_SECU_OFF:1; 00052 uint32_t XTAL32_EXISTS:1; 00053 uint32_t :2; 00054 uint32_t XTAL_CLKDIV:6; 00055 uint32_t :18; 00056 } SYS_CNTLbits; 00057 }; 00058 union { 00059 uint32_t WU_CNTL; 00060 struct CRM_WU_CNTL { 00061 uint32_t TIMER_WU_EN:1; 00062 uint32_t RTC_WU_EN:1; 00063 uint32_t HOST_WAKE:1; 00064 uint32_t AUTO_ADC:1; 00065 uint32_t EXT_WU_EN:4; 00066 uint32_t EXT_WU_EDGE:4; 00067 uint32_t EXT_WU_POL:4; 00068 uint32_t TIMER_WU_IEN:1; 00069 uint32_t RTC_WU_IEN:1; 00070 uint32_t :2; 00071 uint32_t EXT_WU_IEN:4; 00072 uint32_t :4; 00073 uint32_t EXT_OUT_POL:4; 00074 } WU_CNTLbits; 00075 }; 00076 union { 00077 uint32_t SLEEP_CNTL; 00078 struct CRM_SLEEP_CNTL { 00079 uint32_t HIB:1; 00080 uint32_t DOZE:1; 00081 uint32_t :2; 00082 uint32_t RAM_RET:2; 00083 uint32_t MCU_RET:1; 00084 uint32_t DIG_PAD_EN:1; 00085 uint32_t :24; 00086 } SLEEP_CNTLbits; 00087 }; 00088 union { 00089 uint32_t BS_CNTL; 00090 struct CRM_BS_CNTL { 00091 uint32_t BS_EN:1; 00092 uint32_t WAIT4IRQ:1; 00093 uint32_t BS_MAN_EN:1; 00094 uint32_t :2; 00095 uint32_t ARM_OFF_TIME:6; 00096 uint32_t :18; 00097 } BS_CNTLbits; 00098 }; 00099 union { 00100 uint32_t COP_CNTL; 00101 struct CRM_COP_CNTL { 00102 uint32_t COP_EN:1; 00103 uint32_t COP_OUT:1; 00104 uint32_t COP_WP:1; 00105 uint32_t :5; 00106 uint32_t COP_TIMEOUT:7; 00107 uint32_t :1; 00108 uint32_t COP_COUNT:7; 00109 uint32_t :9; 00110 } COP_CNTLbits; 00111 }; 00112 uint32_t COP_SERVICE; 00113 union { 00114 uint32_t STATUS; 00115 struct CRM_STATUS { 00116 uint32_t SLEEP_SYNC:1; 00117 uint32_t HIB_WU_EVT:1; 00118 uint32_t DOZE_WU_EVT:1; 00119 uint32_t RTC_WU_EVT:1; 00120 uint32_t EXT_WU_EVT:4; 00121 uint32_t :1; 00122 uint32_t CAL_DONE:1; 00123 uint32_t COP_EVT:1; 00124 uint32_t :6; 00125 uint32_t VREG_BUCK_RDY:1; 00126 uint32_t VREG_1P8V_RDY:1; 00127 uint32_t VREG_1P5V_RDY:1; 00128 uint32_t :12; 00129 } STATUSbits; 00130 }; 00131 union { 00132 uint32_t MOD_STATUS; 00133 struct CRM_MOD_STATUS { 00134 uint32_t ARM_EN:1; 00135 uint32_t MACA_EN:1; 00136 uint32_t ASM_EN:1; 00137 uint32_t SPI_EN:1; 00138 uint32_t GPIO_EN:1; 00139 uint32_t UART1_EN:1; 00140 uint32_t UART2_EN:1; 00141 uint32_t TMR_EN:1; 00142 uint32_t RIF_EN:1; 00143 uint32_t I2C_EN:1; 00144 uint32_t SSI_EN:1; 00145 uint32_t SPIF_EN:1; 00146 uint32_t ADC_EN:1; 00147 uint32_t :1; 00148 uint32_t JTA_EN:1; 00149 uint32_t NEX_EN:1; 00150 uint32_t :1; 00151 uint32_t AIM_EN:1; 00152 uint32_t :14; 00153 } MOD_STATUSbits; 00154 }; 00155 uint32_t WU_COUNT; 00156 uint32_t WU_TIMEOUT; 00157 uint32_t RTC_COUNT; 00158 uint32_t RTC_TIMEOUT; 00159 uint32_t reserved1; 00160 union { 00161 uint32_t CAL_CNTL; 00162 struct CRM_CAL_CNTL { 00163 uint32_t CAL_TIMEOUT:16; 00164 uint32_t CAL_EN:1; 00165 uint32_t CAL_IEN:1; 00166 uint32_t :14; 00167 } CAL_CNTLbits; 00168 }; 00169 uint32_t CAL_COUNT; 00170 union { 00171 uint32_t RINGOSC_CNTL; 00172 struct CRM_RINGOSC_CNTL { 00173 uint32_t ROSC_EN:1; 00174 uint32_t :3; 00175 uint32_t ROSC_FTUNE:5; 00176 uint32_t ROSC_CTUNE:4; 00177 uint32_t :19; 00178 } RINGOSC_CNTLbits; 00179 }; 00180 union { 00181 uint32_t XTAL_CNTL; 00182 struct CRM_XTAL_CNTL { 00183 uint32_t :8; 00184 uint32_t XTAL_IBIAS_SEL:4; 00185 uint32_t :4; 00186 uint32_t XTAL_FTUNE:5; 00187 uint32_t XTAL_CTUNE:5; 00188 uint32_t :6; 00189 } XTAL_CNTLbits; 00190 }; 00191 union { 00192 uint32_t XTAL32_CNTL; 00193 struct CRM_XTAL32_CNTL { 00194 uint32_t XTAL32_EN:1; 00195 uint32_t :3; 00196 uint32_t XTAL32_GAIN:2; 00197 uint32_t :26; 00198 } XTAL32_CNTLbits; 00199 }; 00200 union { 00201 uint32_t VREG_CNTL; 00202 struct CRM_VREG_CNTL { 00203 uint32_t BUCK_EN:1; 00204 uint32_t BUCK_SYNC_REC_EN:1; 00205 uint32_t BUCK_BYPASS_EN:1; 00206 uint32_t VREG_1P5V_EN:2; 00207 uint32_t VREG_1P5V_SEL:2; 00208 uint32_t VREG_1P8V_EN:1; 00209 uint32_t BUCK_CLKDIV:4; 00210 uint32_t :20; 00211 } VREG_CNTLbits; 00212 }; 00213 uint32_t reserved2; 00214 uint32_t SW_RST; 00215 uint32_t reserved3; 00216 uint32_t reserved4; 00217 uint32_t reserved5; 00218 uint32_t reserved6; 00219 }; 00220 00221 static volatile struct CRM_struct * const CRM = (void *) (CRM_BASE); 00222 00223 /* COP watchdog timer helpers */ 00224 00225 /* set the cop timout in milliseconds */ 00226 #define cop_timeout_ms(x) (CRM->COP_CNTLbits.COP_TIMEOUT = x/87) 00227 #define cop_service() (CRM->COP_SERVICE = 0xc0de5afe) 00228 00229 /* Old register definitions, for compatibility */ 00230 #ifndef REG_NO_COMPAT 00231 00232 static volatile uint32_t * const CRM_SYS_CNTL = ((volatile uint32_t *) (CRM_BASE+0x00)); 00233 static volatile uint32_t * const CRM_WU_CNTL = ((volatile uint32_t *) (CRM_BASE+0x04)); 00234 static volatile uint32_t * const CRM_SLEEP_CNTL = ((volatile uint32_t *) (CRM_BASE+0x08)); 00235 static volatile uint32_t * const CRM_BS_CNTL = ((volatile uint32_t *) (CRM_BASE+0x0c)); 00236 static volatile uint32_t * const CRM_COP_CNTL = ((volatile uint32_t *) (CRM_BASE+0x10)); 00237 static volatile uint32_t * const CRM_COP_SERVICE= ((volatile uint32_t *) (CRM_BASE+0x14)); 00238 static volatile uint32_t * const CRM_STATUS = ((volatile uint32_t *) (CRM_BASE+0x18)); 00239 static volatile uint32_t * const CRM_MOD_STATUS = ((volatile uint32_t *) (CRM_BASE+0x1c)); 00240 static volatile uint32_t * const CRM_WU_COUNT = ((volatile uint32_t *) (CRM_BASE+0x20)); 00241 static volatile uint32_t * const CRM_WU_TIMEOUT = ((volatile uint32_t *) (CRM_BASE+0x24)); 00242 static volatile uint32_t * const CRM_RTC_COUNT = ((volatile uint32_t *) (CRM_BASE+0x28)); 00243 static volatile uint32_t * const CRM_RTC_TIMEOUT= ((volatile uint32_t *) (CRM_BASE+0x2c)); 00244 static volatile uint32_t * const CRM_CAL_CNTL = ((volatile uint32_t *) (CRM_BASE+0x34)); 00245 static volatile uint32_t * const CRM_CAL_COUNT = ((volatile uint32_t *) (CRM_BASE+0x38)); 00246 static volatile uint32_t * const CRM_RINGOSC_CNT= ((volatile uint32_t *) (CRM_BASE+0x3c)); 00247 static volatile uint32_t * const CRM_XTAL_CNTL = ((volatile uint32_t *) (CRM_BASE+0x40)); 00248 static volatile uint32_t * const CRM_XTAL32_CNTL= ((volatile uint32_t *) (CRM_BASE+0x44)); 00249 static volatile uint32_t * const CRM_VREG_CNTL = ((volatile uint32_t *) (CRM_BASE+0x48)); 00250 static volatile uint32_t * const CRM_SW_RST = ((volatile uint32_t *) (CRM_BASE+0x50)); 00251 00252 /* CRM_SYS_CNTL bit locations */ 00253 static const int XTAL32_EXISTS = 5; 00254 00255 /* CRM_WU_CNTL bit locations */ 00256 static const int EXT_WU_IEN = 20; /* 4 bits */ 00257 static const int EXT_WU_EN = 4; /* 4 bits */ 00258 static const int EXT_WU_EDGE = 8; /* 4 bits */ 00259 static const int EXT_WU_POL = 12; /* 4 bits */ 00260 static const int TIMER_WU_EN = 0; 00261 static const int RTC_WU_EN = 1; 00262 static const int TIMER_WU_IEN = 16; 00263 static const int RTC_WU_IEN = 17; 00264 00265 /* CRM_STATUS bit locations */ 00266 static const int EXT_WU_EVT = 4; /* 4 bits, rw1c */ 00267 static const int RTC_WU_EVT = 3; /* rw1c */ 00268 00269 /* RINGOSC_CNTL bit locations */ 00270 static const int ROSC_CTUNE = 9; /* 4 bits */ 00271 static const int ROSC_FTUNE = 4; /* 4 bits */ 00272 static const int ROSC_EN = 0; 00273 00274 #define ring_osc_on() (CRM->RINGOSC_CNTLbits.ROSC_EN = 1) 00275 #define ring_osc_off() (CRM->RINGOSC_CNTLbits.ROSC_EN = 0) 00276 00277 #define REF_OSC 24000000UL /* reference osc. frequency */ 00278 #define NOMINAL_RING_OSC_SEC 2000 /* nominal ring osc. frequency */ 00279 extern uint32_t cal_rtc_secs; /* calibrated 2khz rtc seconds */ 00280 00281 /* XTAL32_CNTL bit locations */ 00282 static const int XTAL32_GAIN = 4; /* 2 bits */ 00283 static const int XTAL32_EN = 0; 00284 00285 #define xtal32_on() (set_bit(*CRM_XTAL32_CNTL,XTAL32_EN)) 00286 #define xtal32_off() (clear_bit(*CRM_XTAL32_CNTL,XTAL32_EN)) 00287 #define xtal32_exists() (set_bit(*CRM_SYS_CNTL,XTAL32_EXISTS)) 00288 00289 /* enable external wake-ups on kbi 4-7 */ 00290 /* see kbi.h for other kbi specific macros */ 00291 #define enable_ext_wu(kbi) (set_bit(*CRM_WU_CNTL,(EXT_WU_EN+kbi-4))) 00292 #define disable_ext_wu(kbi) (clear_bit(*CRM_WU_CNTL,(EXT_WU_EN+kbi-4))) 00293 00294 #define is_ext_wu_evt(kbi) (bit_is_set(*CRM_STATUS,(EXT_WU_EVT+kbi-4))) 00295 #define clear_ext_wu_evt(kbi) (set_bit(*CRM_STATUS,(EXT_WU_EVT+kbi-4))) /* r1wc bit */ 00296 00297 /* enable wake-up timer */ 00298 #define enable_timer_wu_irq() ((set_bit(*CRM_WU_CNTL,(TIMER_WU_IEN)))) 00299 #define disable_timer_wu_irq() ((clear_bit(*CRM_WU_CNTL,(TIMER_WU_IEN)))) 00300 00301 #define enable_timer_wu() ((set_bit(*CRM_WU_CNTL,(TIMER_WU_EN)))) 00302 #define disable_timer_wu() ((clear_bit(*CRM_WU_CNTL,(TIMER_WU_EN)))) 00303 00304 /* enable wake-up from RTC compare */ 00305 #define enable_rtc_wu_irq() (set_bit(*CRM_WU_CNTL,RTC_WU_IEN)) 00306 #define disable_rtc_wu_irq() (clear_bit(*CRM_WU_CNTL,RTC_WU_IEN)) 00307 00308 #define enable_rtc_wu() ((set_bit(*CRM_WU_CNTL,(RTC_WU_EN)))) 00309 #define disable_rtc_wu() ((clear_bit(*CRM_WU_CNTL,(RTC_WU_EN)))) 00310 00311 #define clear_rtc_wu_evt() (set_bit(*CRM_STATUS,RTC_WU_EVT)) 00312 #define rtc_wu_evt() (bit_is_set(*CRM_STATUS,RTC_WU_EVT)) 00313 00314 #define SLEEP_MODE_HIBERNATE bit(0) 00315 #define SLEEP_MODE_DOZE bit(1) 00316 00317 #define SLEEP_PAD_PWR bit(7) 00318 #define SLEEP_RETAIN_MCU bit(6) 00319 #define sleep_ram_retain(x) (x<<4) /* 0-3 */ 00320 #define SLEEP_RAM_8K sleep_ram_retain(0) 00321 #define SLEEP_RAM_32K sleep_ram_retain(1) 00322 #define SLEEP_RAM_64K sleep_ram_retain(2) 00323 #define SLEEP_RAM_96K sleep_ram_retain(3) 00324 00325 #define pack_XTAL_CNTL(ctune4pf, ctune, ftune, ibias) \ 00326 (*CRM_XTAL_CNTL = ((ctune4pf << 25) | (ctune << 21) | ( ftune << 16) | (ibias << 8) | 0x52)) 00327 00328 #endif /* REG_NO_COMPAT */ 00329 00330 #endif
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