Contiki 2.6

isr.h

00001 /*
00002  * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
00003  * to the MC1322x project (http://mc1322x.devl.org)
00004  * All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the Institute nor the names of its contributors
00015  *    may be used to endorse or promote products derived from this software
00016  *    without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
00019  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00021  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
00022  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00023  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00024  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00025  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00026  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00027  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * This file is part of libmc1322x: see http://mc1322x.devl.org
00031  * for details. 
00032  *
00033  *
00034  */
00035 
00036 #ifndef ISR_H
00037 #define ISR_H
00038 
00039 #define INTBASE        (0x80020000)
00040 
00041 #include <stdint.h>
00042 
00043 /* Structure-based ITC access */
00044 #define __INTERRUPT_union(x)              \
00045                 union {                   \
00046                         uint32_t x;       \
00047                         struct ITC_##x {  \
00048                         uint32_t ASM:1;   \
00049                         uint32_t UART1:1; \
00050                         uint32_t UART2:1; \
00051                         uint32_t CRM:1;   \
00052                         uint32_t I2C:1;   \
00053                         uint32_t TMR:1;   \
00054                         uint32_t SPIF:1;  \
00055                         uint32_t MACA:1;  \
00056                         uint32_t SSI:1;   \
00057                         uint32_t ADC:1;   \
00058                         uint32_t SPI:1;   \
00059                         uint32_t :21;     \
00060                         } x##bits; \
00061                 };
00062 
00063 struct ITC_struct {
00064         union {
00065                 uint32_t INTCNTL;
00066                 struct ITC_INTCNTL {
00067                         uint32_t :19;
00068                         uint32_t FIAD:1;
00069                         uint32_t NIAD:1;
00070                         uint32_t :11;
00071                 } INTCNTLbits;
00072         };
00073         uint32_t NIMASK;
00074         uint32_t INTENNUM;
00075         uint32_t INTDISNUM;
00076         __INTERRUPT_union(INTENABLE);
00077         __INTERRUPT_union(INTTYPE);
00078         uint32_t reserved[4];
00079         uint32_t NIVECTOR;
00080         uint32_t FIVECTOR;
00081         __INTERRUPT_union(INTSRC);
00082         __INTERRUPT_union(INTFRC);
00083         __INTERRUPT_union(NIPEND);
00084         __INTERRUPT_union(FIPEND);
00085 };
00086 #undef __INTERRUPT_union
00087 
00088 static volatile struct ITC_struct * const ITC = (void *) (INTBASE);
00089 
00090 
00091 /* Old register definitions, for compatibility */
00092 #ifndef REG_NO_COMPAT
00093 
00094 #define INTCNTL_OFF           (0x0)
00095 #define INTENNUM_OFF          (0x8)
00096 #define INTDISNUM_OFF         (0xC)
00097 #define INTENABLE_OFF        (0x10)
00098 #define INTSRC_OFF           (0x30)
00099 #define INTFRC_OFF           (0x34)
00100 #define NIPEND_OFF           (0x38)
00101 
00102 static volatile uint32_t * const INTCNTL   =   ((volatile uint32_t *) (INTBASE + INTCNTL_OFF));
00103 static volatile uint32_t * const INTENNUM  =   ((volatile uint32_t *) (INTBASE + INTENNUM_OFF));
00104 static volatile uint32_t * const INTDISNUM =   ((volatile uint32_t *) (INTBASE + INTDISNUM_OFF));
00105 static volatile uint32_t * const INTENABLE =   ((volatile uint32_t *) (INTBASE + INTENABLE_OFF));
00106 static volatile uint32_t * const INTSRC    =   ((volatile uint32_t *) (INTBASE + INTSRC_OFF));
00107 static volatile uint32_t * const INTFRC    =   ((volatile uint32_t *) (INTBASE + INTFRC_OFF));
00108 static volatile uint32_t * const NIPEND    =   ((volatile uint32_t *) (INTBASE + NIPEND_OFF));
00109 
00110 enum interrupt_nums {
00111         INT_NUM_ASM = 0,
00112         INT_NUM_UART1,
00113         INT_NUM_UART2,
00114         INT_NUM_CRM,
00115         INT_NUM_I2C,
00116         INT_NUM_TMR,
00117         INT_NUM_SPIF,
00118         INT_NUM_MACA,
00119         INT_NUM_SSI,
00120         INT_NUM_ADC,
00121         INT_NUM_SPI,
00122 };
00123 
00124 #define global_irq_disable() (set_bit(*INTCNTL,20))
00125 #define global_irq_enable()  (clear_bit(*INTCNTL,20))
00126 
00127 #define enable_irq(irq)  (*INTENNUM  = INT_NUM_##irq)
00128 #define disable_irq(irq) (*INTDISNUM = INT_NUM_##irq)
00129 
00130 #define safe_irq_disable(x)  volatile uint32_t saved_irq; saved_irq = *INTENABLE; disable_irq(x)
00131 #define irq_restore() *INTENABLE = saved_irq
00132 
00133 #endif /* REG_NO_COMPAT */
00134 
00135 /* Macro to safely disable all interrupts for a block of code.
00136    Use it like this:
00137    disable_int({
00138        asdf = 1234;
00139        printf("hi\r\n");
00140    });
00141 */
00142 #define __int_top() volatile uint32_t saved_intenable
00143 #define __int_disable() saved_intenable = ITC->INTENABLE; ITC->INTENABLE = 0
00144 #define __int_enable() ITC->INTENABLE = saved_intenable
00145 #define disable_int(x) do { \
00146         __int_top(); \
00147         __int_disable(); \
00148         x; \
00149         __int_enable(); } while(0)
00150 
00151 
00152 extern void tmr0_isr(void) __attribute__((weak));
00153 extern void tmr1_isr(void) __attribute__((weak));
00154 extern void tmr2_isr(void) __attribute__((weak));
00155 extern void tmr3_isr(void) __attribute__((weak));
00156 
00157 extern void rtc_isr(void) __attribute__((weak));
00158 extern void kbi4_isr(void) __attribute__((weak));
00159 extern void kbi5_isr(void) __attribute__((weak));
00160 extern void kbi6_isr(void) __attribute__((weak));
00161 extern void kbi7_isr(void) __attribute__((weak));
00162 
00163 extern void cal_isr(void) __attribute__((weak));
00164 
00165 extern void uart1_isr(void) __attribute__((weak));
00166 extern void uart2_isr(void) __attribute__((weak));
00167 
00168 extern void maca_isr(void) __attribute__((weak));
00169 
00170 extern void asm_isr(void) __attribute__((weak));
00171 
00172 extern void i2c_isr(void) __attribute__((weak));
00173 
00174 #endif