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00001 /* 00002 * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors 00003 * to the MC1322x project (http://mc1322x.devl.org) 00004 * All rights reserved. 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 1. Redistributions of source code must retain the above copyright 00010 * notice, this list of conditions and the following disclaimer. 00011 * 2. Redistributions in binary form must reproduce the above copyright 00012 * notice, this list of conditions and the following disclaimer in the 00013 * documentation and/or other materials provided with the distribution. 00014 * 3. Neither the name of the Institute nor the names of its contributors 00015 * may be used to endorse or promote products derived from this software 00016 * without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 00019 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00020 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00021 * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 00022 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00023 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 00024 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 00025 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00026 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00027 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00028 * SUCH DAMAGE. 00029 * 00030 * This file is part of libmc1322x: see http://mc1322x.devl.org 00031 * for details. 00032 * 00033 * 00034 */ 00035 00036 #ifndef _MACA_H_ 00037 #define _MACA_H_ 00038 00039 #include <packet.h> 00040 #include <stdint.h> 00041 #include <utils.h> 00042 00043 /* maca initialization and on off routines */ 00044 void maca_init(void); 00045 void maca_off(void); 00046 void maca_on(void); 00047 00048 /* run periodically to make sure the maca is still doing right */ 00049 void check_maca(void); 00050 00051 /* maca configuration interface */ 00052 void set_power(uint8_t power); 00053 void set_channel(uint8_t chan); 00054 00055 extern uint8_t (*get_lqi)(void); 00056 00057 #define DEMOD_DCD 1 /* -96dBm, 22.2mA */ 00058 #define DEMOD_NCD 0 /* -100dBm, 24.2mA */ 00059 void set_demodulator_type(uint8_t demod); 00060 00061 /* set_fcs_mode(NO_FCS) to disable checksum filtering */ 00062 extern volatile uint8_t fcs_mode; 00063 #define set_fcs_mode(x) fcs_mode = (x) 00064 00065 /* set_prm_mode(PROMISC) to disable address filtering */ 00066 /* set_prm_mode(AUTOACK) to enable address filtering AND autoack */ 00067 extern volatile uint8_t prm_mode; 00068 #define set_prm_mode(x) prm_mode = (x) 00069 00070 /* maca packet interface */ 00071 void tx_packet(volatile packet_t *p); 00072 volatile packet_t* rx_packet(void); 00073 volatile packet_t* get_free_packet(void); 00074 void free_packet(volatile packet_t *p); 00075 void free_all_packets(void); 00076 00077 extern volatile packet_t *rx_head, *tx_head; 00078 extern volatile uint32_t maca_entry; 00079 00080 extern void maca_rx_callback(volatile packet_t *p) __attribute__((weak)); 00081 extern void maca_tx_callback(volatile packet_t *p) __attribute__((weak)); 00082 00083 /* maca lowlevel routines */ 00084 /* most applications won't need to use them */ 00085 void reset_maca(void); 00086 void init_phy(void); 00087 void flyback_init(void); 00088 void ResumeMACASync(void); 00089 void radio_init(void); 00090 uint32_t init_from_flash(uint32_t addr); 00091 00092 #define MAX_PACKET_SIZE (MAX_PAYLOAD_SIZE + 2) /* packet includes 2 bytes of checksum */ 00093 00094 /* maca register and field defines */ 00095 00096 #define MACA_BASE (0x80004000) 00097 #define MACA_RESET ((volatile uint32_t *) (MACA_BASE+0x04)) 00098 #define MACA_RANDOM ((volatile uint32_t *) (MACA_BASE+0x08)) 00099 #define MACA_CONTROL ((volatile uint32_t *) (MACA_BASE+0x0c)) 00100 00101 /* MACA_CONTROL bits and fields */ 00102 #define ISM 20 00103 #define PRECOUNT 16 /* preamble reapeat counter */ 00104 #define PRECOUNT_MASK bit_mask(4,PRECOUNT) 00105 #define RTSO 15 /* reset slot counter */ 00106 #define ROLE 13 /* set if PAN coordinator */ 00107 #define NOFC 12 /* set to disable FCS */ 00108 enum { 00109 USE_FCS = 0, 00110 NO_FCS = 1, 00111 }; 00112 #define PRM 11 /* set for promiscuous mode */ 00113 enum { 00114 AUTOACK = 0, 00115 PROMISC = 1, 00116 }; 00117 #define REL 10 /* 1 for relative, 0 for absolute */ 00118 #define ASAP 9 /* 1 start now, 0 timer start */ 00119 #define BCN 8 /* 1 beacon only, 0 for a */ 00120 #define AUTO 7 /* 1 continuous rx, rx only once */ 00121 #define LFSR 6 /* 1 use polynomial for Turbolink */ 00122 #define TM 5 00123 00124 #define MACA_MODE 3 00125 #define MODE_MASK bit_mask(2,MACA_MODE) 00126 #define NO_CCA 0 00127 #define NO_SLOT_CCA 1 00128 #define SLOT_CCA 2 00129 00130 #define SEQUENCE 0 00131 #define SEQUENCE_MASK bit_mask(3,SEQUENCE) 00132 /* end of MACA_CONTROL bits and fields */ 00133 00134 #define MACA_STATUS ((volatile uint32_t *) (MACA_BASE+0x10)) 00135 /* MACA_STATUS bits and fields */ 00136 #define STATUS_TIMEOUT 15 00137 #define CRC 14 00138 #define BUSY 13 00139 #define OVR 12 00140 #define CODE 0 00141 #define CODE_MASK bit_mask(4,CODE) 00142 /* status codes */ 00143 #define SUCCESS 0 00144 #define CODE_TIMEOUT 1 00145 #define CHANNEL_BUSY 2 00146 #define CRC_FAILED 3 00147 #define ABORTED 4 00148 #define NO_ACK 5 00149 #define NO_DATA 6 00150 #define LATE_START 7 00151 #define EXT_TIMEOUT 8 00152 #define EXT_PND_TIMEOUT 9 00153 #define PLL_UNLOCK 12 00154 #define EXTERNAL_ABORT 13 00155 #define NOT_COMPLETED 14 00156 #define DMA_BUS_ERROR 15 00157 /* end of MACA_CONTROL bits and fields */ 00158 00159 #define MACA_FRMPND ((volatile uint32_t *) (MACA_BASE+0x14)) 00160 #define MACA_TMREN ((volatile uint32_t *) (MACA_BASE+0x40)) 00161 #define MACA_TMRDIS ((volatile uint32_t *) (MACA_BASE+0x44)) 00162 #define MACA_CLK ((volatile uint32_t *) (MACA_BASE+0x48)) 00163 #define MACA_STARTCLK ((volatile uint32_t *) (MACA_BASE+0x4c)) 00164 #define MACA_CPLCLK ((volatile uint32_t *) (MACA_BASE+0x50)) 00165 #define MACA_SFTCLK ((volatile uint32_t *) (MACA_BASE+0x54)) 00166 #define MACA_CLKOFFSET ((volatile uint32_t *) (MACA_BASE+0x58)) 00167 #define MACA_RELCLK ((volatile uint32_t *) (MACA_BASE+0x5c)) 00168 #define MACA_CPLTIM ((volatile uint32_t *) (MACA_BASE+0x60)) 00169 #define MACA_SLOTOFFSET ((volatile uint32_t *) (MACA_BASE+0x64)) 00170 #define MACA_TIMESTAMP ((volatile uint32_t *) (MACA_BASE+0x68)) 00171 #define MACA_DMARX ((volatile uint32_t *) (MACA_BASE+0x80)) 00172 #define MACA_DMATX ((volatile uint32_t *) (MACA_BASE+0x84)) 00173 #define MACA_DMAPOLL ((volatile uint32_t *) (MACA_BASE+0x88)) 00174 #define MACA_TXLEN ((volatile uint32_t *) (MACA_BASE+0x8c)) 00175 #define MACA_TXSEQNR ((volatile uint32_t *) (MACA_BASE+0x90)) 00176 #define MACA_SETRXLVL ((volatile uint32_t *) (MACA_BASE+0x94)) 00177 #define MACA_GETRXLVL ((volatile uint32_t *) (MACA_BASE+0x98)) 00178 #define MACA_IRQ ((volatile uint32_t *) (MACA_BASE+0xc0)) 00179 #define MACA_CLRIRQ ((volatile uint32_t *) (MACA_BASE+0xc4)) 00180 #define MACA_SETIRQ ((volatile uint32_t *) (MACA_BASE+0xc8)) 00181 #define MACA_MASKIRQ ((volatile uint32_t *) (MACA_BASE+0xcc)) 00182 #define MACA_MACPANID ((volatile uint32_t *) (MACA_BASE+0x100)) 00183 #define MACA_MAC16ADDR ((volatile uint32_t *) (MACA_BASE+0x104)) 00184 #define MACA_MAC64HI ((volatile uint32_t *) (MACA_BASE+0x108)) 00185 #define MACA_MAC64LO ((volatile uint32_t *) (MACA_BASE+0x10c)) 00186 #define MACA_FLTREJ ((volatile uint32_t *) (MACA_BASE+0x110)) 00187 #define MACA_CLKDIV ((volatile uint32_t *) (MACA_BASE+0x114)) 00188 #define MACA_WARMUP ((volatile uint32_t *) (MACA_BASE+0x118)) 00189 #define MACA_PREAMBLE ((volatile uint32_t *) (MACA_BASE+0x11c)) 00190 #define MACA_WHITESEED ((volatile uint32_t *) (MACA_BASE+0x120)) 00191 #define MACA_FRAMESYNC0 ((volatile uint32_t *) (MACA_BASE+0x124)) 00192 #define MACA_FRAMESYNC1 ((volatile uint32_t *) (MACA_BASE+0x128)) 00193 #define MACA_TXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x140)) 00194 #define MACA_RXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x144)) 00195 #define MACA_EOFDELAY ((volatile uint32_t *) (MACA_BASE+0x148)) 00196 #define MACA_CCADELAY ((volatile uint32_t *) (MACA_BASE+0x14c)) 00197 #define MACA_RXEND ((volatile uint32_t *) (MACA_BASE+0x150)) 00198 #define MACA_TXCCADELAY ((volatile uint32_t *) (MACA_BASE+0x154)) 00199 #define MACA_KEY3 ((volatile uint32_t *) (MACA_BASE+0x158)) 00200 #define MACA_KEY2 ((volatile uint32_t *) (MACA_BASE+0x15c)) 00201 #define MACA_KEY1 ((volatile uint32_t *) (MACA_BASE+0x160)) 00202 #define MACA_KEY0 ((volatile uint32_t *) (MACA_BASE+0x164)) 00203 #define MACA_OPTIONS ((volatile uint32_t *) (MACA_BASE+0x180)) 00204 00205 00206 /******************************************************************************/ 00207 /* everything under this comment is messy, needs cleaning, and will */ 00208 /* probably change in the future */ 00209 /******************************************************************************/ 00210 00211 #define control_pre_count (7<<16) /* preamble reapeat counter */ 00212 #define control_rst_slot (1<<15) /* reset slot counter */ 00213 #define control_role (1<<13) /* set if PAN coordinator */ 00214 #define control_nofc (1<<12) /* set to disable FCS */ 00215 #define control_prm (1<<11) /* set for promiscuous mode */ 00216 #define control_relative (1<<10) /* 1 for relative, 0 for absolute */ 00217 #define control_asap (1<<9) /* 1 start now, 0 timer start */ 00218 #define control_bcn (1<<8) /* 1 beacon only, 0 for a */ 00219 #define control_auto (1<<7) /* 1 continuous rx, rx only once */ 00220 #define control_lfsr (1<<6) /* 1 use polynomial for Turbolink */ 00221 00222 #define gMACA_Clock_DIV_c 95 00223 00224 //rom_base_adr equ 0x00000000 ; rom base address 00225 //ram_base_adr equ 0x00400000 ; ram base address 00226 //ram0_base_adr equ 0x00400000 ; ram0 base address (2K words = 8K 00227 //bytes) 00228 //ram1_base_adr equ 0x00402000 ; ram1 base address (6K words = 24K 00229 //bytes) 00230 //ram2_base_adr equ 0x00408000 ; ram2 base address (8K words = 32K 00231 //bytes) 00232 //ram3_base_adr equ 0x00410000 ; ram3 base address (8K words 00233 enum { 00234 cc_success = 0, 00235 cc_timeout = 1, 00236 cc_channel_busy = 2, 00237 cc_crc_fail = 3, 00238 cc_aborted = 4, 00239 cc_no_ack = 5, 00240 cc_no_data = 6, 00241 cc_late_start = 7, 00242 cc_ext_timeout = 8, 00243 cc_ext_pnd_timeout = 9, 00244 cc_nc1 = 10, 00245 cc_nc2 = 11, 00246 cc_nc3 = 12, 00247 cc_cc_external_abort= 13, 00248 cc_not_completed = 14, 00249 cc_bus_error = 15 00250 }; 00251 //control codes for mode bits 00252 00253 enum { 00254 control_mode_no_cca = 0, 00255 control_mode_non_slotted = (1<<3), 00256 control_mode_slotted = (1<<4) 00257 }; 00258 //control codes for sequence bits 00259 enum { 00260 control_seq_nop = 0, 00261 control_seq_abort = 1, 00262 control_seq_wait = 2, 00263 control_seq_tx = 3, 00264 control_seq_rx = 4, 00265 control_seq_txpoll = 5, 00266 control_seq_cca = 6, 00267 control_seq_ed = 7 00268 }; 00269 00270 #define maca_version (*((volatile uint32_t *)(0x80004000))) 00271 #define maca_reset (*((volatile uint32_t *)(0x80004004))) 00272 #define maca_random (*((volatile uint32_t *)(0x80004008))) 00273 #define maca_control (*((volatile uint32_t *)(0x8000400c))) 00274 #define maca_status (*((volatile uint32_t *)(0x80004010))) 00275 #define maca_frmpnd (*((volatile uint32_t *)(0x80004014))) 00276 00277 #define maca_edvalue (*((volatile uint32_t *)(0x8000401c))) 00278 #define maca_tmren (*((volatile uint32_t *)(0x80004040))) 00279 #define maca_tmrdis (*((volatile uint32_t *)(0x80004044))) 00280 #define maca_clk (*((volatile uint32_t *)(0x80004048))) 00281 #define maca_startclk (*((volatile uint32_t *)(0x8000404c))) 00282 #define maca_cplclk (*((volatile uint32_t *)(0x80004050))) 00283 #define maca_sftclk (*((volatile uint32_t *)(0x80004054))) 00284 #define maca_clkoffset (*((volatile uint32_t *)(0x80004058))) 00285 #define maca_relclk (*((volatile uint32_t *)(0x8000405c))) 00286 #define maca_cpltim (*((volatile uint32_t *)(0x80004060))) 00287 #define maca_slotoffset (*((volatile uint32_t *)(0x80004064))) 00288 #define maca_timestamp (*((volatile uint32_t *)(0x80004068))) 00289 #define maca_dmarx (*((volatile uint32_t *)(0x80004080))) 00290 #define maca_dmatx (*((volatile uint32_t *)(0x80004084))) 00291 #define maca_dmatxpoll (*((volatile uint32_t *)(0x80004088))) 00292 #define maca_txlen (*((volatile uint32_t *)(0x8000408c))) 00293 #define maca_txseqnr (*((volatile uint32_t *)(0x80004090))) 00294 #define maca_setrxlvl (*((volatile uint32_t *)(0x80004094))) 00295 #define maca_getrxlvl (*((volatile uint32_t *)(0x80004098))) 00296 #define maca_irq (*((volatile uint32_t *)(0x800040c0))) 00297 #define maca_clrirq (*((volatile uint32_t *)(0x800040c4))) 00298 #define maca_setirq (*((volatile uint32_t *)(0x800040c8))) 00299 #define maca_maskirq (*((volatile uint32_t *)(0x800040cc))) 00300 #define maca_panid (*((volatile uint32_t *)(0x80004100))) 00301 #define maca_addr16 (*((volatile uint32_t *)(0x80004104))) 00302 #define maca_maca64hi (*((volatile uint32_t *)(0x80004108))) 00303 #define maca_maca64lo (*((volatile uint32_t *)(0x8000410c))) 00304 #define maca_fltrej (*((volatile uint32_t *)(0x80004110))) 00305 #define maca_divider (*((volatile uint32_t *)(0x80004114))) 00306 #define maca_warmup (*((volatile uint32_t *)(0x80004118))) 00307 #define maca_preamble (*((volatile uint32_t *)(0x8000411c))) 00308 #define maca_whiteseed (*((volatile uint32_t *)(0x80004120))) 00309 #define maca_framesync (*((volatile uint32_t *)(0x80004124))) 00310 #define maca_framesync2 (*((volatile uint32_t *)(0x80004128))) 00311 #define maca_txackdelay (*((volatile uint32_t *)(0x80004140))) 00312 #define maca_rxackdelay (*((volatile uint32_t *)(0x80004144))) 00313 #define maca_eofdelay (*((volatile uint32_t *)(0x80004148))) 00314 #define maca_ccadelay (*((volatile uint32_t *)(0x8000414c))) 00315 #define maca_rxend (*((volatile uint32_t *)(0x80004150))) 00316 #define maca_txccadelay (*((volatile uint32_t *)(0x80004154))) 00317 #define maca_key3 (*((volatile uint32_t *)(0x80004158))) 00318 #define maca_key2 (*((volatile uint32_t *)(0x80004158))) 00319 #define maca_key1 (*((volatile uint32_t *)(0x80004158))) 00320 #define maca_key0 (*((volatile uint32_t *)(0x80004158))) 00321 00322 00323 typedef union maca_version_reg_tag 00324 { 00325 struct 00326 { 00327 uint32_t MINOR:8; 00328 uint32_t RESERVED1:8; 00329 uint32_t MAJOR:8; 00330 uint32_t RESERVED2:8; 00331 } Bits; 00332 uint32_t Reg; 00333 } maca_version_reg_t; 00334 00335 #define maca_version_reg_st ((maca_version_reg_t)(maca_version)) 00336 00337 00338 typedef union maca_reset_reg_tag 00339 { 00340 struct 00341 { 00342 uint32_t RESERVED:30; 00343 uint32_t CLK_ON:1; 00344 uint32_t RST:1; 00345 } Bits; 00346 uint32_t Reg; 00347 } maca_reset_reg_t; 00348 00349 #define maca_reset_reg_st ((maca_reset_reg_t)(maca_reset)) 00350 00351 00352 /* typedef union maca_ctrl_reg_tag */ 00353 /* { */ 00354 /* struct */ 00355 /* { */ 00356 /* uint32_t RESERVED:11; */ 00357 /* uint32_t ISM:1; */ 00358 /* uint32_t PRE_COUNT:4; */ 00359 /* uint32_t RSTO:1; */ 00360 /* uint32_t RSV:1; */ 00361 /* uint32_t ROLE:1; */ 00362 /* uint32_t NOFC:1; */ 00363 /* uint32_t PRM:1; */ 00364 /* uint32_t rel:1; */ 00365 /* uint32_t ASAP:1; */ 00366 /* uint32_t BCN:1; */ 00367 /* uint32_t AUTO:1; */ 00368 /* uint32_t LFSR:1; */ 00369 /* uint32_t TM:1; */ 00370 /* uint32_t MODE:2; */ 00371 /* uint32_t SEQUENCE:3; */ 00372 /* } Bits; */ 00373 /* uint32_t Reg; */ 00374 /* } maca_ctrl_reg_t; */ 00375 00376 #define maca_control_ism (1<<20) 00377 #define maca_control_zigbee (~maca_control_ism) 00378 00379 #define maca_ctrl_reg_st ((maca_ctrl_reg_t *)(&maca_reset)) 00380 #define _set_maca_test_mode(x) (maca_ctrl_reg_st->Bits.TM = x) 00381 #define _set_maca_sequence(x) (maca_ctrl_reg_st->Bits.SEQUENCE = x) 00382 #define _set_maca_asap(x) (maca_ctrl_reg_st->Bits.ASAP = x) 00383 00384 00385 #define MACA_CTRL_ZIGBEE_MODE (0) 00386 #define MACA_CTRL_ISM_MODE (1) 00387 #define MACA_CTRL_PRM_NORMAL_MODE (0) 00388 #define MACA_CTRL_PRM_PROMISCUOUS_MODE (1) 00389 #define MACA_CTRL_BCN_ALL (0) 00390 #define MACA_CTRL_BCN_BEACON (1) 00391 #define MACA_CTRL_TM_NORMAL (0) 00392 #define MACA_CTRL_TM_TEST (1) 00393 #define MACA_CTRL_MODE_NO_CCA (0) 00394 #define MACA_CTRL_MODE_NON_SLOTTED (1) 00395 #define MACA_CTRL_MODE_SLOTTED (2) 00396 00397 typedef enum maca_freq_chann_tag 00398 { 00399 SMAC_CHANN_11 = 0, 00400 SMAC_CHANN_12, 00401 SMAC_CHANN_13, 00402 SMAC_CHANN_14, 00403 SMAC_CHANN_15, 00404 SMAC_CHANN_16, 00405 SMAC_CHANN_17, 00406 SMAC_CHANN_18, 00407 SMAC_CHANN_19, 00408 SMAC_CHANN_20, 00409 SMAC_CHANN_21, 00410 SMAC_CHANN_22, 00411 SMAC_CHANN_23, 00412 SMAC_CHANN_24, 00413 SMAC_CHANN_25, 00414 SMAC_CHANN_26, 00415 MAX_SMAC_CHANNELS 00416 } maca_freq_chann_t; 00417 00418 00419 /* Sequence complete codes */ 00420 enum maca_complete_code { 00421 maca_cc_success = 0, 00422 maca_cc_timeout = 1, 00423 maca_cc_channel_busy = 2, 00424 maca_cc_crc_fail = 3, 00425 maca_cc_aborted = 4, 00426 maca_cc_no_ack = 5, 00427 maca_cc_no_data = 6, 00428 maca_cc_late_start = 7, 00429 maca_cc_ext_timeout = 8, 00430 maca_cc_ext_pnd_timeout = 9, 00431 maca_cc_nc1 = 10, 00432 maca_cc_nc2 = 11, 00433 maca_cc_nc3 = 12, 00434 maca_cc_cc_external_abort= 13, 00435 maca_cc_not_completed = 14, 00436 maca_cc_bus_error = 15 00437 }; 00438 00439 /* control sequence codes */ 00440 enum maca_ctrl_seq { 00441 maca_ctrl_seq_nop = 0, 00442 maca_ctrl_seq_abort = 1, 00443 maca_ctrl_seq_wait = 2, 00444 maca_ctrl_seq_tx = 3, 00445 maca_ctrl_seq_rx = 4, 00446 maca_ctrl_seq_txpoll = 5, 00447 maca_ctrl_seq_cca = 6, 00448 maca_ctrl_seq_ed = 7 00449 }; 00450 00451 /* transmission modes */ 00452 enum maca_ctrl_modes { 00453 maca_ctrl_mode_no_cca = 0, 00454 maca_ctrl_mode_non_slotted_csma_ca = 1, 00455 maca_ctrl_mode_slotted_csma_ca = 2, 00456 }; 00457 00458 /* MACA_CONTROL bits */ 00459 enum maca_ctrl_bits { 00460 maca_ctrl_seq = 0, /* 3 bits */ 00461 maca_ctrl_mode = 3, /* 2 bits */ 00462 maca_ctrl_tm = 5, 00463 maca_ctrl_lfsr = 6, 00464 maca_ctrl_auto = 7, 00465 maca_ctrl_bcn = 8, 00466 maca_ctrl_asap = 9, 00467 maca_ctrl_rel = 10, 00468 maca_ctrl_prm = 11, 00469 maca_ctrl_nofc = 12, 00470 maca_ctrl_role = 13, 00471 /* 14 reserved */ 00472 maca_ctrl_rsto = 15, 00473 maca_ctrl_pre_count = 16, /* 4 bits */ 00474 maca_ctrl_ism = 20, 00475 }; 00476 00477 /* MACA_IRQ bits */ 00478 enum maca_irqs { 00479 maca_irq_acpl = 0, 00480 maca_irq_poll = 1, 00481 maca_irq_di = 2, 00482 maca_irq_wu = 3, 00483 maca_irq_rst = 4, 00484 maca_irq_lvl = 9, 00485 maca_irq_sftclk = 10, 00486 maca_irq_flt = 11, 00487 maca_irq_crc = 12, 00488 maca_irq_cm = 13, 00489 maca_irq_sync = 14, 00490 maca_irq_strt = 15, 00491 }; 00492 00493 /* MACA_RESET bits */ 00494 enum maca_reset_bits { 00495 maca_reset_rst = 0, 00496 maca_reset_clkon = 1, 00497 }; 00498 00499 /* MACA_TMREN bits */ 00500 enum maca_tmren_bits { 00501 maca_tmren_strt = 0, 00502 maca_tmren_cpl = 1, 00503 maca_tmren_sft = 2, 00504 }; 00505 00506 enum maca_status_bits { 00507 maca_status_ovr = 12, 00508 maca_status_busy = 13, 00509 maca_status_crc = 14, 00510 maca_status_to = 15, 00511 }; 00512 00513 #define action_complete_irq() bit_is_set(*MACA_IRQ,maca_irq_acpl) 00514 #define filter_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_flt) 00515 #define checksum_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_crc) 00516 #define data_indication_irq() bit_is_set(*MACA_IRQ,maca_irq_di) 00517 #define softclock_irq() bit_is_set(*MACA_IRQ,maca_irq_sftclk) 00518 #define poll_irq() bit_is_set(*MACA_IRQ,maca_irq_poll) 00519 00520 #define status_is_not_completed() ((*MACA_STATUS & 0xffff) == maca_cc_not_completed) 00521 #define status_is_success() ((*MACA_STATUS & 0xffff) == maca_cc_success) 00522 00523 #define SMAC_MACA_CNTL_INIT_STATE ( control_prm | control_nofc | control_mode_non_slotted ) 00524 00525 #define MACA_WRITE(reg, src) (reg = src) 00526 #define MACA_READ(reg) reg 00527 00528 #endif // _MACA_H_