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platform-conf.h

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00001 /*
00002  * Copyright (c) 2010, Swedish Institute of Computer Science.
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the Institute nor the names of its contributors
00014  *    may be used to endorse or promote products derived from this software
00015  *    without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
00018  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00020  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
00021  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00022  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00023  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00024  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00027  * SUCH DAMAGE.
00028  */
00029 
00030 /**
00031  * \file
00032  *         Platform configuration for the Z1SP platform
00033  * \author
00034  *         Joakim Eriksson <joakime@sics.se>
00035  */
00036 
00037 #ifndef __PLATFORM_CONF_H__
00038 #define __PLATFORM_CONF_H__
00039 
00040 /*
00041  * Definitions below are dictated by the hardware and not really
00042  * changeable!
00043  */
00044 #define ZOLERTIA_Z1   0  /* Enric */
00045 #define ZOLERTIA_Z1SP 1  /* Enric */
00046 
00047 /* CPU target speed in Hz */
00048 #define F_CPU 8000000uL /* 8MHz by default */
00049 //Enric #define F_CPU 3900000uL /*2457600uL*/
00050 
00051 /* Our clock resolution, this is the same as Unix HZ. */
00052 #define CLOCK_CONF_SECOND 128UL
00053 
00054 #define BAUD2UBR(baud) ((F_CPU/baud))
00055 
00056 #define CCIF
00057 #define CLIF
00058 
00059 #define HAVE_STDINT_H
00060 #include "msp430def.h"
00061 
00062 /* XXX Temporary place for defines that are lacking in mspgcc4's gpio.h */
00063 #ifdef __IAR_SYSTEMS_ICC__
00064 #ifndef P1SEL2_
00065 #define P1SEL2_              (0x0041u)  /* Port 1 Selection 2*/
00066 DEFC(   P1SEL2             , P1SEL2_)
00067 #endif
00068 #ifndef P5SEL2_
00069 #define P5SEL2_              (0x0045u)  /* Port 5 Selection 2*/
00070 DEFC(   P5SEL2             , P5SEL2_)
00071 #endif
00072 #else /* __IAR_SYSTEMS_ICC__ */
00073 #ifdef __GNUC__
00074 #ifndef P1SEL2_
00075   #define P1SEL2_             0x0041  /* Port 1 Selection 2*/
00076   sfrb(P1SEL2, P1SEL2_);
00077 #endif
00078 #ifndef P5SEL2_
00079   #define P5SEL2_             0x0045  /* Port 5 Selection 2*/
00080   sfrb(P5SEL2, P5SEL2_);
00081 #endif
00082 #endif /* __GNUC__ */
00083 #endif /* __IAR_SYSTEMS_ICC__ */
00084 
00085 /* Types for clocks and uip_stats */
00086 typedef unsigned short uip_stats_t;
00087 typedef unsigned long clock_time_t;
00088 typedef unsigned long off_t;
00089 
00090 /* the low-level radio driver */
00091 #define NETSTACK_CONF_RADIO   cc2420_driver
00092 
00093 /*
00094  * Definitions below are dictated by the hardware and not really
00095  * changeable!
00096  */
00097 
00098 /* LED ports */
00099 #define LEDS_PxDIR P4DIR
00100 #define LEDS_PxOUT P4OUT
00101 #define LEDS_CONF_RED    0x04
00102 #define LEDS_CONF_GREEN  0x01
00103 #define LEDS_CONF_YELLOW 0x80
00104 
00105 /* DCO speed resynchronization for more robust UART, etc. */
00106 #define DCOSYNCH_CONF_ENABLED 0
00107 #define DCOSYNCH_CONF_PERIOD 30
00108 
00109 #define ROM_ERASE_UNIT_SIZE  512
00110 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
00111 
00112 
00113 #define CFS_CONF_OFFSET_TYPE    long
00114 
00115 /* Use the first 64k of external flash for node configuration */
00116 #define NODE_ID_XMEM_OFFSET     (0 * XMEM_ERASE_UNIT_SIZE)
00117 
00118 /* Use the second 64k of external flash for codeprop. */
00119 #define EEPROMFS_ADDR_CODEPROP  (1 * XMEM_ERASE_UNIT_SIZE)
00120 
00121 #define CFS_XMEM_CONF_OFFSET    (2 * XMEM_ERASE_UNIT_SIZE)
00122 #define CFS_XMEM_CONF_SIZE      (1 * XMEM_ERASE_UNIT_SIZE)
00123 
00124 #define CFS_RAM_CONF_SIZE 4096
00125 
00126 /*
00127  * SPI bus configuration for the TMote Sky.
00128  */
00129 
00130 /* SPI input/output registers. */
00131 #define SPI_TXBUF UCB0TXBUF
00132 #define SPI_RXBUF UCB0RXBUF
00133 
00134                                 /* USART0 Tx ready? */
00135 #define SPI_WAITFOREOTx() while ((UCB0STAT & UCBUSY) != 0)
00136                                 /* USART0 Rx ready? */
00137 #define SPI_WAITFOREORx() while ((IFG2 & UCB0RXIFG) == 0)
00138                                 /* USART0 Tx buffer ready? */
00139 #define SPI_WAITFORTxREADY() while ((IFG2 & UCB0TXIFG) == 0)
00140 
00141 #define MOSI           1  /* P3.1 - Output: SPI Master out - slave in (MOSI) */
00142 #define MISO           2  /* P3.2 - Input:  SPI Master in - slave out (MISO) */
00143 #define SCK            3  /* P3.3 - Output: SPI Serial Clock (SCLK) */
00144 
00145 /*
00146  * SPI bus - M25P80 external flash configuration.
00147  */
00148 //#define FLASH_PWR     3       /* P4.3 Output */ ALWAYS POWERED ON Z1
00149 #define FLASH_CS        4       /* P4.4 Output */
00150 #define FLASH_HOLD      7       /* P5.7 Output */
00151 
00152 /* Enable/disable flash access to the SPI bus (active low). */
00153 
00154 #define SPI_FLASH_ENABLE()  ( P4OUT &= ~BV(FLASH_CS) )
00155 #define SPI_FLASH_DISABLE() ( P4OUT |=  BV(FLASH_CS) )
00156 
00157 #define SPI_FLASH_HOLD()                ( P5OUT &= ~BV(FLASH_HOLD) )
00158 #define SPI_FLASH_UNHOLD()              ( P5OUT |=  BV(FLASH_HOLD) )
00159 
00160 
00161 /*
00162  * SPI bus - CC2420 pin configuration.
00163  */
00164 
00165 #define CC2420_CONF_SYMBOL_LOOP_COUNT 1302      /* 326us msp430X @ 8MHz */
00166 
00167 /* P1.2 - Input: FIFOP from CC2420 */
00168 #define CC2420_FIFOP_PORT(type)   P1##type
00169 #define CC2420_FIFOP_PIN          2
00170 /* P1.3 - Input: FIFO from CC2420 */
00171 #define CC2420_FIFO_PORT(type)     P1##type
00172 #define CC2420_FIFO_PIN            3
00173 /* P1.4 - Input: CCA from CC2420 */
00174 #define CC2420_CCA_PORT(type)      P1##type
00175 #define CC2420_CCA_PIN             4
00176 /* P4.1 - Input:  SFD from CC2420 */
00177 #define CC2420_SFD_PORT(type)      P4##type
00178 #define CC2420_SFD_PIN             1
00179  /* P3.0 - Output: SPI Chip Select (CS_N) */
00180 #define CC2420_CSN_PORT(type)      P3##type
00181 #define CC2420_CSN_PIN             0
00182 /* P4.5 - Output: VREG_EN to CC2420 */
00183 #define CC2420_VREG_PORT(type)     P4##type
00184 #define CC2420_VREG_PIN            5
00185 /* P4.6 - Output: RESET_N to CC2420 */
00186 #define CC2420_RESET_PORT(type)    P4##type
00187 #define CC2420_RESET_PIN           6
00188 
00189 
00190 #define CC2420_IRQ_VECTOR PORT1_VECTOR
00191 
00192 /* Pin status. */
00193 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
00194 #define CC2420_FIFO_IS_1  (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
00195 #define CC2420_CCA_IS_1   (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
00196 #define CC2420_SFD_IS_1   (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
00197 
00198 /* The CC2420 reset pin. */
00199 #define SET_RESET_INACTIVE()   (CC2420_RESET_PORT(OUT) |=  BV(CC2420_RESET_PIN))
00200 #define SET_RESET_ACTIVE()     (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
00201 
00202 /* CC2420 voltage regulator enable pin. */
00203 #define SET_VREG_ACTIVE()       (CC2420_VREG_PORT(OUT) |=  BV(CC2420_VREG_PIN))
00204 #define SET_VREG_INACTIVE()     (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
00205 
00206 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
00207 #define CC2420_FIFOP_INT_INIT() do {                  \
00208     CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN);  \
00209     CC2420_CLEAR_FIFOP_INT();                         \
00210   } while(0)
00211 
00212 /* FIFOP on external interrupt 0. */
00213 #define CC2420_ENABLE_FIFOP_INT()  do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
00214 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
00215 #define CC2420_CLEAR_FIFOP_INT()   do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
00216 
00217 /*
00218  * Enables/disables CC2420 access to the SPI bus (not the bus).
00219  * (Chip Select)
00220  */
00221 
00222  /* ENABLE CSn (active low) */
00223 #define CC2420_SPI_ENABLE()     (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
00224  /* DISABLE CSn (active low) */
00225 #define CC2420_SPI_DISABLE()    (CC2420_CSN_PORT(OUT) |=  BV(CC2420_CSN_PIN))
00226 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
00227 
00228 #endif /* __PLATFORM_CONF_H__ */