Contiki 2.6

platform-conf.h

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00001 /*
00002  * Copyright (c) 2010, Swedish Institute of Computer Science.
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the Institute nor the names of its contributors
00014  *    may be used to endorse or promote products derived from this software
00015  *    without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
00018  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00020  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
00021  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00022  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00023  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00024  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00027  * SUCH DAMAGE.
00028  *
00029  * $Id: platform-conf.h,v 1.1 2010/06/23 10:25:54 joxe Exp $
00030  */
00031 
00032 /**
00033  * \file
00034  *         A brief description of what this file is
00035  * \author
00036  *         Niclas Finne <nfi@sics.se>
00037  *         Joakim Eriksson <joakime@sics.se>
00038  */
00039 
00040 #ifndef __PLATFORM_CONF_H__
00041 #define __PLATFORM_CONF_H__
00042 
00043 /*
00044  * Definitions below are dictated by the hardware and not really
00045  * changeable!
00046  */
00047  /* Platform name, type, and MCU clock rate */
00048 #define PLATFORM_NAME  "MicaZ"
00049 #define PLATFORM_TYPE  MICAZ
00050 #ifndef F_CPU
00051 #define F_CPU          7372800UL
00052 #endif
00053 
00054 /* The AVR tick interrupt usually is done with an 8 bit counter around 128 Hz.
00055  * 125 Hz needs slightly more overhead during the interrupt, as does a 32 bit
00056  * clock_time_t.
00057  */
00058  /* Clock ticks per second */
00059 #define CLOCK_CONF_SECOND 128
00060 #if 1
00061 /* 16 bit counter overflows every ~10 minutes */
00062 typedef unsigned short clock_time_t;
00063 #define CLOCK_LT(a,b)  ((signed short)((a)-(b)) < 0)
00064 #define INFINITE_TIME 0xffff
00065 #define RIME_CONF_BROADCAST_ANNOUNCEMENT_MAX_TIME INFINITE_TIME/CLOCK_CONF_SECOND /* Default uses 600 */
00066 #define COLLECT_CONF_BROADCAST_ANNOUNCEMENT_MAX_TIME INFINITE_TIME/CLOCK_CONF_SECOND /* Default uses 600 */
00067 #else
00068 typedef unsigned long clock_time_t;
00069 #define CLOCK_LT(a,b)  ((signed long)((a)-(b)) < 0)
00070 #define INFINITE_TIME 0xffffffff
00071 #endif
00072 /* These routines are not part of the contiki core but can be enabled in cpu/avr/clock.c */
00073 void clock_delay_msec(uint16_t howlong);
00074 void clock_adjust_ticks(clock_time_t howmany);
00075 
00076 /* LED ports */
00077 #define LEDS_PxDIR DDRA // port direction register
00078 #define LEDS_PxOUT PORTA // port register
00079 #define LEDS_CONF_RED    0x04 //red led
00080 #define LEDS_CONF_GREEN  0x02 // green led
00081 #define LEDS_CONF_YELLOW 0x01 // yellow led
00082 
00083 /* COM port to be used for SLIP connection */
00084 #define SLIP_PORT RS232_PORT_0
00085 
00086 /* Pre-allocated memory for loadable modules heap space (in bytes)*/
00087 #define MMEM_CONF_SIZE 256
00088 
00089 /* Use the following address for code received via the codeprop
00090  * facility
00091  */
00092 #define EEPROMFS_ADDR_CODEPROP 0x8000
00093 
00094 #define EEPROM_NODE_ID_START 0x00
00095 
00096 
00097 #define NETSTACK_CONF_RADIO   cc2420_driver
00098 
00099 
00100 /*
00101  * SPI bus configuration for the TMote Sky.
00102  */
00103 
00104 /* SPI input/output registers. */
00105 #define SPI_TXBUF SPDR
00106 #define SPI_RXBUF SPDR
00107 
00108 #define BV(bitno) _BV(bitno)
00109 
00110 #define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
00111 #define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
00112 
00113 #define SCK            1  /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
00114 #define MOSI           2  /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
00115 #define MISO           3  /* - Input:  SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
00116 
00117 /*
00118  * SPI bus - M25P80 external flash configuration.
00119  */
00120 
00121 #define FLASH_PWR       3       /* P4.3 Output */
00122 #define FLASH_CS        4       /* P4.4 Output */
00123 #define FLASH_HOLD      7       /* P4.7 Output */
00124 
00125 /* Enable/disable flash access to the SPI bus (active low). */
00126 
00127 #define SPI_FLASH_ENABLE()  ( P4OUT &= ~BV(FLASH_CS) )
00128 #define SPI_FLASH_DISABLE() ( P4OUT |=  BV(FLASH_CS) )
00129 
00130 #define SPI_FLASH_HOLD()                ( P4OUT &= ~BV(FLASH_HOLD) )
00131 #define SPI_FLASH_UNHOLD()              ( P4OUT |=  BV(FLASH_HOLD) )
00132 
00133 /*
00134  * SPI bus - CC2420 pin configuration.
00135  */
00136 
00137 #define CC2420_CONF_SYMBOL_LOOP_COUNT 500
00138 
00139 /*
00140  * SPI bus - CC2420 pin configuration.
00141  */
00142 
00143 #define FIFO_P         6
00144 #define FIFO           7
00145 #define CCA            6
00146 
00147 #define SFD            4
00148 #define CSN            0
00149 #define VREG_EN        5
00150 #define RESET_N        6
00151 
00152 
00153 /* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */
00154 #define CC2420_FIFOP_PORT(type)   P##type##E
00155 #define CC2420_FIFOP_PIN          6
00156 /* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */
00157 #define CC2420_FIFO_PORT(type)     P##type##B
00158 #define CC2420_FIFO_PIN            7
00159 /* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */
00160 #define CC2420_CCA_PORT(type)      P##type##D
00161 #define CC2420_CCA_PIN             6
00162 /* - Input:  SFD from CC2420 - ATMEGA128 PORTD, PIN4 */
00163 #define CC2420_SFD_PORT(type)      P##type##D
00164 #define CC2420_SFD_PIN             4
00165 /* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */
00166 #define CC2420_CSN_PORT(type)      P##type##B
00167 #define CC2420_CSN_PIN             0
00168 /* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */
00169 #define CC2420_VREG_PORT(type)     P##type##A
00170 #define CC2420_VREG_PIN            5
00171 /* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */
00172 #define CC2420_RESET_PORT(type)    P##type##A
00173 #define CC2420_RESET_PIN           6
00174 
00175 #define CC2420_IRQ_VECTOR INT6_vect
00176 
00177 /* Pin status. */
00178 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
00179 #define CC2420_FIFO_IS_1  (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
00180 #define CC2420_CCA_IS_1   (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
00181 #define CC2420_SFD_IS_1   (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
00182 
00183 /* The CC2420 reset pin. */
00184 #define SET_RESET_INACTIVE()   (CC2420_RESET_PORT(ORT) |=  BV(CC2420_RESET_PIN))
00185 #define SET_RESET_ACTIVE()     (CC2420_RESET_PORT(ORT) &= ~BV(CC2420_RESET_PIN))
00186 
00187 /* CC2420 voltage regulator enable pin. */
00188 #define SET_VREG_ACTIVE()       (CC2420_VREG_PORT(ORT) |=  BV(CC2420_VREG_PIN))
00189 #define SET_VREG_INACTIVE()     (CC2420_VREG_PORT(ORT) &= ~BV(CC2420_VREG_PIN))
00190 
00191 /* CC2420 rising edge trigger for external interrupt 6 (FIFOP).
00192  * Enable the external interrupt request for INT6.
00193  * See Atmega128 datasheet about EICRB Register
00194  */
00195 #define CC2420_FIFOP_INT_INIT() do {\
00196   EICRB |= 0x30; \
00197   CC2420_CLEAR_FIFOP_INT(); \
00198 } while (0)
00199 
00200 /* FIFOP on external interrupt 6. */
00201 #define CC2420_ENABLE_FIFOP_INT()          do { EIMSK |= 0x40; } while (0)
00202 #define CC2420_DISABLE_FIFOP_INT()         do { EIMSK &= ~0x40; } while (0)
00203 #define CC2420_CLEAR_FIFOP_INT()           do { EIFR = 0x40; } while (0)
00204 
00205 /*
00206  * Enables/disables CC2420 access to the SPI bus (not the bus).
00207  * (Chip Select)
00208  */
00209 #define CC2420_SPI_ENABLE() (PORTB &= ~BV(CSN)) /* ENABLE CSn (active low) */
00210 #define CC2420_SPI_DISABLE() (PORTB |=  BV(CSN)) /* DISABLE CSn (active low) */
00211 
00212 #endif /* __PLATFORM_CONF_H__ */