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00001 /* 00002 * Copyright (c) 2011, Swedish Institute of Computer Science. 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without 00006 * modification, are permitted provided that the following conditions 00007 * are met: 00008 * 1. Redistributions of source code must retain the above copyright 00009 * notice, this list of conditions and the following disclaimer. 00010 * 2. Redistributions in binary form must reproduce the above copyright 00011 * notice, this list of conditions and the following disclaimer in the 00012 * documentation and/or other materials provided with the distribution. 00013 * 3. Neither the name of the Institute nor the names of its contributors 00014 * may be used to endorse or promote products derived from this software 00015 * without specific prior written permission. 00016 * 00017 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 00018 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00019 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00020 * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 00021 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00022 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 00023 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 00024 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00025 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00026 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00027 * SUCH DAMAGE. 00028 */ 00029 00030 /** 00031 * \file 00032 * Platform configuration for the Sentilla JCreate 00033 * \author 00034 * Niclas Finne <nfi@sics.se> 00035 * Joakim Eriksson <joakime@sics.se> 00036 */ 00037 00038 #ifndef __PLATFORM_CONF_H__ 00039 #define __PLATFORM_CONF_H__ 00040 00041 /* 00042 * Definitions below are dictated by the hardware and not really 00043 * changeable! 00044 */ 00045 /* Platform TMOTE_SKY */ 00046 #define TMOTE_SKY 1 00047 00048 #define LEDS_CONF_ALL 255 00049 #define PLATFORM_HAS_LEDS 1 00050 #define PLATFORM_HAS_BUTTON 0 00051 00052 /* CPU target speed in Hz */ 00053 #define F_CPU 3900000uL /*2457600uL*/ 00054 00055 /* Our clock resolution, this is the same as Unix HZ. */ 00056 #define CLOCK_CONF_SECOND 128UL 00057 00058 #define BAUD2UBR(baud) ((F_CPU/baud)) 00059 00060 #define CCIF 00061 #define CLIF 00062 00063 #define HAVE_STDINT_H 00064 #include "msp430def.h" 00065 00066 00067 /* Types for clocks and uip_stats */ 00068 typedef unsigned short uip_stats_t; 00069 typedef unsigned long clock_time_t; 00070 typedef unsigned long off_t; 00071 00072 /* the low-level radio driver */ 00073 #define NETSTACK_CONF_RADIO cc2420_driver 00074 00075 /* LED ports */ 00076 #define LEDS_PxDIR P5DIR 00077 #define LEDS_PxOUT P5OUT 00078 #define LEDS_CONF_RED 0x10 00079 #define LEDS_CONF_GREEN 0x20 00080 #define LEDS_CONF_YELLOW 0x40 00081 00082 /* DCO speed resynchronization for more robust UART, etc. */ 00083 #ifndef DCOSYNCH_CONF_ENABLED 00084 #define DCOSYNCH_CONF_ENABLED 1 00085 #endif /* DCOSYNCH_CONF_ENABLED */ 00086 #ifndef DCOSYNCH_CONF_PERIOD 00087 #define DCOSYNCH_CONF_PERIOD 30 00088 #endif /* DCOSYNCH_CONF_PERIOD */ 00089 00090 #define ROM_ERASE_UNIT_SIZE 512 00091 #define XMEM_ERASE_UNIT_SIZE (64*1024L) 00092 00093 00094 #define CFS_CONF_OFFSET_TYPE long 00095 00096 00097 /* Use the first 64k of external flash for node configuration */ 00098 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE) 00099 00100 /* Use the second 64k of external flash for codeprop. */ 00101 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE) 00102 00103 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE) 00104 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE) 00105 00106 #define CFS_RAM_CONF_SIZE 4096 00107 00108 /* 00109 * SPI bus configuration for the TMote Sky. 00110 */ 00111 00112 /* SPI input/output registers. */ 00113 #define SPI_TXBUF U0TXBUF 00114 #define SPI_RXBUF U0RXBUF 00115 00116 /* USART0 Tx ready? */ 00117 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0) 00118 /* USART0 Rx ready? */ 00119 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0) 00120 /* USART0 Tx buffer ready? */ 00121 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0) 00122 00123 #define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */ 00124 #define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */ 00125 #define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */ 00126 00127 /* 00128 * SPI bus - M25P80 external flash configuration. 00129 */ 00130 00131 #define FLASH_PWR 3 /* P4.3 Output */ 00132 #define FLASH_CS 4 /* P4.4 Output */ 00133 #define FLASH_HOLD 7 /* P4.7 Output */ 00134 00135 /* Enable/disable flash access to the SPI bus (active low). */ 00136 00137 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) ) 00138 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) ) 00139 00140 #define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) ) 00141 #define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) ) 00142 00143 /* 00144 * SPI bus - CC2420 pin configuration. 00145 */ 00146 00147 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800 00148 00149 /* P1.0 - Input: FIFOP from CC2420 */ 00150 #define CC2420_FIFOP_PORT(type) P1##type 00151 #define CC2420_FIFOP_PIN 0 00152 /* P1.3 - Input: FIFO from CC2420 */ 00153 #define CC2420_FIFO_PORT(type) P1##type 00154 #define CC2420_FIFO_PIN 3 00155 /* P1.4 - Input: CCA from CC2420 */ 00156 #define CC2420_CCA_PORT(type) P1##type 00157 #define CC2420_CCA_PIN 4 00158 /* P4.1 - Input: SFD from CC2420 */ 00159 #define CC2420_SFD_PORT(type) P4##type 00160 #define CC2420_SFD_PIN 1 00161 /* P4.2 - Output: SPI Chip Select (CS_N) */ 00162 #define CC2420_CSN_PORT(type) P4##type 00163 #define CC2420_CSN_PIN 2 00164 /* P4.5 - Output: VREG_EN to CC2420 */ 00165 #define CC2420_VREG_PORT(type) P4##type 00166 #define CC2420_VREG_PIN 5 00167 /* P4.6 - Output: RESET_N to CC2420 */ 00168 #define CC2420_RESET_PORT(type) P4##type 00169 #define CC2420_RESET_PIN 6 00170 00171 #define CC2420_IRQ_VECTOR PORT1_VECTOR 00172 00173 /* Pin status. */ 00174 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN))) 00175 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN))) 00176 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN))) 00177 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN))) 00178 00179 /* The CC2420 reset pin. */ 00180 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN)) 00181 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN)) 00182 00183 /* CC2420 voltage regulator enable pin. */ 00184 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN)) 00185 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN)) 00186 00187 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */ 00188 #define CC2420_FIFOP_INT_INIT() do { \ 00189 CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \ 00190 CC2420_CLEAR_FIFOP_INT(); \ 00191 } while(0) 00192 00193 /* FIFOP on external interrupt 0. */ 00194 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0) 00195 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0) 00196 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0) 00197 00198 /* 00199 * Enables/disables CC2420 access to the SPI bus (not the bus). 00200 * (Chip Select) 00201 */ 00202 00203 /* ENABLE CSn (active low) */ 00204 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN)) 00205 /* DISABLE CSn (active low) */ 00206 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN)) 00207 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN)) 00208 00209 #endif /* __PLATFORM_CONF_H__ */